Am 23.08.24 um 06:54 schrieb Matthew Brost:
Using a chain fence is problematic as these cannot be installed in
timeout drm sync objects. Use a dma-fence-array instead at the cost of
an extra failure point.
Mhm, IIRC we converted chain objects into dma-fence-arrays while
installing them into a
Am 23.08.24 um 06:54 schrieb Matthew Brost:
Useful to preallocate dma fence array and then arm in path of reclaim or
a dma fence.
Exactly that was rejected before because it allows to create circle
dependencies.
You would need a really really good argument why that is necessary.
Regards,
Ch
Hi Jinjie,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20240821]
url:
https://github.com/intel-lab-lkp/linux/commits/Jinjie-Ruan/drm-amd-display-Remove-unused-dcn35_fpga_funcs/20240822-095139
base: next-20240821
patch link:
https
On 22/08/24 9:36 PM, Nícolas F. R. A. Prado wrote:
On Thu, Aug 22, 2024 at 06:46:50AM +, Rohit Agarwal wrote:
Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
Signed-off-by: Rohit Agarwal
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20
1 file changed, 2
Using a chain fence is problematic as these cannot be installed in
timeout drm sync objects. Use a dma-fence-array instead at the cost of
an extra failure point.
Also fixup reserve fence count to include media GT invalidation fence.
v2:
- Fix reserve fence count (Casey Bowman)
v3:
- Prealloc dm
Useful to preallocate dma fence array and then arm in path of reclaim or
a dma fence.
Cc: Sumit Semwal
Cc: Christian König
Signed-off-by: Matthew Brost
---
drivers/dma-buf/dma-fence-array.c | 81 ++-
include/linux/dma-fence-array.h | 7 +++
2 files changed, 66 in
Third try, requires spliting out dma fence array alloc and arm into new
functions to avoid memory allocations under notifier lock.
Matt
Matthew Brost (2):
dma-buf: Split out dma fence array create into alloc and arm functions
drm/xe: Use dma-fence array for media GT TLB invalidations in PT c
Hi Jinjie,
kernel test robot noticed the following build warnings:
[auto build test WARNING on next-20240821]
url:
https://github.com/intel-lab-lkp/linux/commits/Jinjie-Ruan/drm-amd-display-Remove-unused-dcn35_fpga_funcs/20240822-095139
base: next-20240821
patch link:
https
Add hwmon support for fan1_input attribute, which will expose fan speed
in RPM. With this in place we can monitor fan speed using lm-sensors tool.
$ sensors
i915-pci-0300
Adapter: PCI adapter
in0: 653.00 mV
fan1:3833 RPM
power1: N/A (max = 43.00 W)
energy1: 32.02 k
Hi, Liviu,
I'm sorry for my carelessness and thanks for your correction, the corrected
patch is as follows.
And we do have an extra patch to set layer_split, but this part of the code is
owned by my colleague,
So that I cannot upload it, sorry about this.
Signed-off-by: hongchi.peng
---
driv
cocci report a double assignment warning. 'as_sdp->duration_incr_ms'
was assigned twice in intel_dp_compute_as_sdp().
Signed-off-by: Yuesong Li
---
drivers/gpu/drm/i915/display/intel_dp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/dr
Do you have any problems with the variant below? The only changes are
in commit message and added comment for new helper...
commit 8c291056e3e88153ef4b6316d5247547da200757
Author: Al Viro
Date: Fri Aug 2 09:56:28 2024 -0400
new helper: drm_gem_prime_handle_to_dmabuf()
Once someth
dcn35_fpga_funcs is not used anywhere, remove it.
And also remove related not used dcn35_init_clocks_fpga()
and dcn35_update_clocks_fpga().
Signed-off-by: Jinjie Ruan
---
v3:
- Also remove related unused functions.
- Update the commit message.
v2:
- Remove it instead of making it static.
---
..
On 2024/8/23 2:01, Alex Deucher wrote:
> On Thu, Aug 22, 2024 at 5:20 AM Jinjie Ruan wrote:
>>
>> dcn35_fpga_funcs is not used anywhere, remove it.
>
> This will lead to warnings about unused functions. The fpga specific
> functions should be removed as well. I'd suggest compile testing your
Hi，
在 2024-08-22 19:59:43，"Cristian Ciocaltea"
写道：
>On 8/22/24 11:41 AM, Conor Dooley wrote:
>> On Thu, Aug 22, 2024 at 09:01:34AM +0200, Heiko Stübner wrote:
>>> @Conor: just for me, did some shift happen in our understanding of dt-
>>> best-practices in terms of syscon via phandle vs. syscon
This commit removes the unnecessary semicolon (`;`) following the
closing brace of the switch statement in the function
'dml2_core_utils_get_tile_block_size_bytes'.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9804
Signed-off-by: Yang Li
---
.../amd/display/dc
On 8/22/24 9:23 PM, Akhil P Oommen wrote:
On Wed, Aug 21, 2024 at 04:34:15PM +0200, Antonino Maniscalco wrote:
On 8/19/24 10:08 PM, Akhil P Oommen wrote:
On Thu, Aug 15, 2024 at 08:26:14PM +0200, Antonino Maniscalco wrote:
This patch implements preemption feature for A6xx targets, this allows
On Thu, Aug 22, 2024 at 8:29 AM Sergio Lopez Pascual wrote:
> Gurchetan Singh writes:
>
> > On Thu, Aug 8, 2024 at 3:38 AM Sergio Lopez Pascual
> wrote:
> >
> >> Gurchetan Singh writes:
> >>
> >> > On Tue, Aug 6, 2024 at 1:15 PM Rob Clark wrote:
> >> >
> >> >> On Tue, Aug 6, 2024 at 9:15 AM G
On 8/22/24 9:21 PM, Akhil P Oommen wrote:
On Tue, Aug 20, 2024 at 11:48:33AM +0100, Connor Abbott wrote:
On Mon, Aug 19, 2024 at 9:31 PM Akhil P Oommen wrote:
On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote:
Some userspace changes are necessary so add a flag for userspace
Hello Dave, Sima,
The following changes since commit 11df68c265460d4dff5d19a1313f0fff69470f98:
Merge tag 'drm-misc-next-2024-08-16' of
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next (2024-08-22
09:42:23 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/
On Thu, Aug 22, 2024 at 1:34 PM Akhil P Oommen wrote:
>
> On Tue, Aug 20, 2024 at 10:16:47AM -0700, Rob Clark wrote: > From: Rob Clark
>
> >
> > In the case of iova fault triggered devcore dumps, include additional
> > debug information based on what we think is the current page tables,
> > incl
On 8/22/2024 3:20 PM, Laurent Pinchart wrote:
The msm_atomic_state_clear() and msm_atomic_state_free() functions are
declared but never defined. Remove their prototypes.
Signed-off-by: Laurent Pinchart
Reviewed-by: Kieran Bingham
---
drivers/gpu/drm/msm/msm_drv.h | 2 --
1 file changed,
The msm_atomic_state_clear() and msm_atomic_state_free() functions are
declared but never defined. Remove their prototypes.
Signed-off-by: Laurent Pinchart
Reviewed-by: Kieran Bingham
---
drivers/gpu/drm/msm/msm_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_
Hi Dave and Sima,
Second drm-xe-next pull request for the 6.12 cycle.
Several fixes here that are also going through drm-xe-fixes. Most of the
other changes are the missing bits for Xe2 (LNL and BMG) and general
refactors.
The only UAPI change is actually a fix for building with gcc 5.
I left
Don't populate the const read-only array possible_nvram_sizes on the
stack at run time, instead make it static.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/tegra/hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/
On Wed, Aug 21, 2024 at 09:21:34AM +0800, Li Zetao wrote:
> Use kvmemdup instead of kvmalloc() + memcpy() to simplify the code.
>
> No functional change intended.
>
> Signed-off-by: Li Zetao
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++
> 1 f
On Tue, Aug 20, 2024 at 10:16:47AM -0700, Rob Clark wrote: > From: Rob Clark
>
> In the case of iova fault triggered devcore dumps, include additional
> debug information based on what we think is the current page tables,
> including the TTBR0 value (which should match what we have in
> adreno_s
On Wed, Aug 21, 2024 at 05:02:56PM +0100, Connor Abbott wrote:
> On Mon, Aug 19, 2024 at 9:09 PM Akhil P Oommen
> wrote:
> >
> > On Thu, Aug 15, 2024 at 08:26:14PM +0200, Antonino Maniscalco wrote:
> > > This patch implements preemption feature for A6xx targets, this allows
> > > the GPU to switc
"struct drm_edid" is the safe and recommended alternative to "struct edid".
Rename the member to make sure that no usage sites are missed,
as "struct drm_edid" has some restrictions, for example it can not be
used with kfree().
Signed-off-by: Thomas Weißschuh
---
Changes in v2:
- Simplify some l
On Wed, Aug 21, 2024 at 04:34:15PM +0200, Antonino Maniscalco wrote:
> On 8/19/24 10:08 PM, Akhil P Oommen wrote:
> > On Thu, Aug 15, 2024 at 08:26:14PM +0200, Antonino Maniscalco wrote:
> > > This patch implements preemption feature for A6xx targets, this allows
> > > the GPU to switch to a higher
On Tue, Aug 20, 2024 at 11:48:33AM +0100, Connor Abbott wrote:
> On Mon, Aug 19, 2024 at 9:31 PM Akhil P Oommen
> wrote:
> >
> > On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote:
> > > Some userspace changes are necessary so add a flag for userspace to
> > > advertise support f
On Thu, 22 Aug 2024, Doug Anderson wrote:
> Jiri / Ben,
[ ... snip ... ]
> I think this series is ready for you to merge at your leisure. If
> there's anything blocking it then please yell. Thanks! :-)
Hmm, for some reason the only mentions of this series in my inbox are your
Reviewed-by: from J
On Thu, Aug 22, 2024 at 2:57 AM Yu Jiaoliang wrote:
>
> *** BLURB HERE ***
>
> Yu Jiaoliang (6):
> drm/amd/display: Use max/min macro
> drm/amd/display: Use max/min macro
> drm/amd/display: Use max/min macro
> drm/amd/display: Use max/min macro
> drm/amd/display: Use max/min macro
> dr
On Mon, Aug 05, 2024 at 02:22:13PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/1/2024 8:10 PM, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > ARL and MTL share a single GSC firmware blob. However, ARL requires a
> > newer version of it.
> >
> > So add differentiate of the
On Wed, Aug 21, 2024 at 8:29 PM Al Viro wrote:
>
> On Wed, Aug 14, 2024 at 06:15:46PM -0400, Felix Kuehling wrote:
> >
> > On 2024-08-12 02:59, Al Viro wrote:
> > > Using drm_gem_prime_handle_to_fd() to set dmabuf up and insert it into
> > > descriptor table, only to have it looked up by file desc
On Thu, Aug 22, 2024 at 5:20 AM Jinjie Ruan wrote:
>
> dcn35_fpga_funcs is not used anywhere, remove it.
This will lead to warnings about unused functions. The fpga specific
functions should be removed as well. I'd suggest compile testing your
changes first to catch these types of warnings.
Al
Applied. Thanks!
On Wed, Aug 21, 2024 at 3:45 AM Ma Ke wrote:
>
> Instead of using state->fb->obj[0] directly, get object from framebuffer
> by calling drm_gem_fb_get_obj() and return error code when object is
> null to avoid using null object of framebuffer.
>
> Cc: sta...@vger.kernel.org
> Fix
Jiri / Ben,
On Mon, Jul 22, 2024 at 12:31 AM Zhaoxiong Lv
wrote:
>
> Elan-ekth6a12nay requires reset to pull down time greater than 10ms,
> so the configuration post_power_delay_ms is 10, and the chipset
> initial time is required to be greater than 300ms, so the
> post_gpio_reset_on_delay_ms is
Prefer the struct drm_edid based functions for allocating the EDID and
updating the connector.
Signed-off-by: Jani Nikula
---
Cc: Hans de Goede
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/tiny/gm12u320.c | 13 +++
Prefer the struct drm_edid based functions for storing the EDID and
updating the connector.
Signed-off-by: Jani Nikula
---
Cc: Philipp Zabel
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: dri
Prefer the struct drm_edid based functions for reading the EDID and
updating the connector.
Signed-off-by: Jani Nikula
---
Cc: Thierry Reding
Cc: Mikko Perttunen
Cc: Jonathan Hunter
Cc: linux-te...@vger.kernel.org
---
drivers/gpu/drm/tegra/drm.h| 2 +-
drivers/gpu/drm/tegra/output.c |
Prefer the struct drm_edid based functions for reading the EDID and
updating the connector.
The functional change is that the CEC physical address gets invalidated
when the EDID could not be read.
v2:
- display info usage was split to a separate patch
- check drm_edid_connector_update() return va
Look up display dimensions from display_info instead of the EDID
directly. This will be helpful for the follow-up work.
Signed-off-by: Jani Nikula
---
Cc: Inki Dae
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Cc: Krzysztof Kozlowski
Cc: Alim Akhtar
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux
Prefer the struct drm_edid based functions for reading the EDID and
updating the connector.
The functional change is that the CEC physical address gets invalidated
when the EDID could not be read.
v2: Use drm_edid_read() instead of drm_edid_read_ddc() (Sima)
Reviewed-by: Daniel Vetter
Signed-of
The umerged patches from [1] and then some.
BR,
Jani.
[1] https://lore.kernel.org/r/cover.1715691257.git.jani.nik...@intel.com
Jani Nikula (6):
drm/sti/sti_hdmi: convert to struct drm_edid
drm/exynos: hdmi: use display_info for printing display dimensions
drm/exynos: hdmi: convert to struc
In preparation for upcoming patches, we need routines to
dynamically create and destroy CCS engines based on the CCS mode
that the user wants to set.
The process begins by calculating the engine mask for the engines
that need to be added or removed. We then update the UABI list of
exposed engines
Create the 'ccs_mode' file under
/sys/class/drm/cardX/gt/gt0/ccs_mode
This file allows the user to read and set the current CCS mode.
- Reading: The user can read the current CCS mode, which can be
1, 2, or 4. This value is derived from the current engine
mask.
- Writing: The user can s
In preparation for upcoming patches, we need the ability to
create and remove individual sysfs files. To facilitate this,
extract from the intel_engines_add_sysfs() function the creation
of individual files.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/sysfs_engines.c | 74 +
Until now, the UABI engines list has been accessed in read-only
mode, as it was created once during boot and destroyed upon
module unload.
In upcoming commits, we will be modifying this list by changing
the CCS mode, allowing compute engines to be dynamically added
and removed at runtime based on
To support upcoming patches, we need to store the current mask
for active CCS engines.
Active engines refer to those exposed to userspace via the UABI
engine list.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 41 +++--
drivers/gpu/drm/i915/gt/intel
Upcoming commits will need to access engine-related kobjects to
enable the creation and destruction of sysfs interfaces at
runtime.
For this, store the "engine" directory (i915->sysfs_engine), the
engine files (gt->kobj), and the default data
(gt->kobj_defaults).
Signed-off-by: Andi Shyti
---
d
Implement a sysfs interface to show the number of available CCS
slices. The displayed number does not take into account the CCS
balancing mode.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 21 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 +
Following the decision to manage CCS engine creation within UABI
engines, the "cslices" variable in the "ccs" structure in the
"gt" is no longer needed. Remove it is now redundant.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_
In commit ea315f98e5d6 ("drm/i915/gt: Do not generate the command
streamer for all the CCS"), we restricted the creation of
physical CCS engines to only one stream. This allowed the user to
submit a single compute workload, with all CCS slices sharing the
workload from that stream.
This patch remo
Selftests should run only on enabled engines, as disabled engines
are not intended for use. A practical example is when, on DG2
machines, the user chooses to utilize only one CCS stream instead
of all four.
To address this, introduce the for_each_enabled_engine() loop,
which will skip engines when
Mark engines as invalid when they are not added to the UABI list
to prevent accidental assignment of batch buffers.
Currently, this change is mostly precautionary with minimal
impact. However, in the future, when CCS engines will be
dynamically added and removed by the user, this mechanism will
be
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i9
Until now, we have only set CCS mode balancing to 1, which means
that only one compute engine is exposed to the user. The stream
of compute commands submitted to that engine is then shared among
all the dedicated execution units.
This is done by calling the 'intel_gt_apply_ccs_mode(); function.
W
Store the CCS mode value in the intel_gt->ccs structure to make
it available for future instances that may need to change its
value.
Name it mode_reg_val because it holds the value that will
be written into the CCS_MODE register, determining the CCS
balancing and, consequently, the number of engin
When setting the CCS mode, we mistakenly used wa_masked_en() to
apply the workaround, which reads from the register and masks the
existing value with the new one.
Our intention was to write the value directly, without masking
it.
So far, this hasn't caused issues because we've been using a
regist
Hi,
This patch series introduces static load balancing for GPUs with
multiple compute engines. It's a lengthy series, and some
challenging aspects still need to be resolved.
I have tried to split the work as much as possible to facilitate
the review process.
To summarize, in patches 1 to 14, no
On Wed, Aug 21, 2024 at 02:16:21PM -0600, Gustavo A. R. Silva wrote:
> Use the `DEFINE_RAW_FLEX()` helper for an on-stack definition of
> a flexible structure where the size of the flexible-array member
> is known at compile-time, and refactor the rest of the code,
> accordingly.
>
> So, with this
On big endian machine, fbdev wants BGRX, but gnome/wayland wants
XRGB, which wasn't possible because virtio-gpu could only support
one format. Now that it's fixed, it can supports both.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/virtio/virtgpu_display.c | 6 --
drivers/gpu/dr
The host dumb buffer command needs a format, but the
DRM_IOCTL_MODE_CREATE_DUMB only provides a buffer size.
So wait for the DRM_IOCTL_MODE_ADDFB(2), to get the format, and create
the host resources at this time.
This will allow virtio-gpu to support multiple pixel formats.
This problem was notic
On Wed, Aug 21, 2024 at 9:06 AM Thomas Zimmermann wrote:
>
> Rework fbdev probing to support fbdev_probe in struct drm_driver
> and remove the old fb_probe callback. Provide an initializer macro
> for struct drm_driver that sets the callback according to the kernel
> configuration.
>
> Call drm_cl
On Thu, Aug 22, 2024 at 3:49 AM Yang Ruibin <11162...@vivo.com> wrote:
>
> The variable highest_pcie_level_enabled is named
> hightest_pcie_level_enabled in other modules.
hightest is a typo. It should be highest. Please fix up the
misspellings instead.
Alex
> Please ensure the consistency of
On Mon, 24 Jun 2024, Daniel Vetter wrote:
> On Tue, May 14, 2024 at 03:55:15PM +0300, Jani Nikula wrote:
>> Prefer the struct drm_edid based functions for reading the EDID and
>> updating the connector.
>>
>> Signed-off-by: Jani Nikula
>>
>> ---
>>
>> Cc: Thierry Reding
>> Cc: Mikko Perttunen
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
It has DPI interface and supports a maximum resolution of WXGA along
with 2 RPFs to support the blending of two picture layers and raster
operations (ROPs).
The DU module i
Document DU found in RZ/G2UL SoC. The DU block is identical to RZ/G2L
SoC, but has only DPI interface.
While at it, add missing required property port@1 for RZ/G2L and RZ/V2L
SoCs. Currently there is no user for the DPI interface and hence there
won't be any ABI breakage for adding port@1 as requi
This patch series aims to add support for RZ/G2UL DU.
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
The output of LCDC is connected display parallel interface (DPI) and
supports a maximum resolution of WXGA along with
On Thu, Aug 22, 2024 at 06:46:50AM +, Rohit Agarwal wrote:
> Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
>
> Signed-off-by: Rohit Agarwal
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/b
Gurchetan Singh writes:
> On Thu, Aug 8, 2024 at 3:38 AM Sergio Lopez Pascual wrote:
>
>> Gurchetan Singh writes:
>>
>> > On Tue, Aug 6, 2024 at 1:15 PM Rob Clark wrote:
>> >
>> >> On Tue, Aug 6, 2024 at 9:15 AM Gurchetan Singh
>> >> wrote:
>> >> >
>> >> >
>> >> >
>> >> > On Mon, Aug 5, 2024
On Thu, Aug 22, 2024 at 04:41:59PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 12.08.24 um 08:59 schrieb Al Viro:
> > Once something had been put into descriptor table, the only thing you
> > can do with it is returning descriptor to userland - you can't withdraw
> > it on subsequent failure exit,
cocci reported a double assignment problem. Upon reviewing previous
commits, it appears this may actually be an incorrect assignment.
Fixes: 8b9550344d39 ("drm/ipp: clean up debug messages")
Signed-off-by: Yuesong Li
---
drivers/gpu/drm/exynos/exynos_drm_gsc.c | 2 +-
1 file changed, 1 insertion
In hx83102_get_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a possible NULL
pointer dereference on failure of drm_mode_duplicate(). Add a
check to avoid npd.
Fixes: 0ef94554dc40 ("drm/panel: himax-hx83102: Break out as separate driver")
Signed-off-by:
Hi Dave and Sima,
This is indeed a hectic week on our drm-xe-fixes.
- 10 of the patches here are patches that got recent merged.
- 9 are extra patches, mostly workarounds, which were already
in drm-xe-next, but not picked up for fixes due the lack of
Fixes tag. Lucas had identified them on a back
Am 21.08.24 um 21:11 schrieb Alex Deucher:
In aperture_remove_conflicting_pci_devices(), we currently only
call sysfb_disable() on vga class devices. This leads to the
following problem when the pimary device is not VGA compatible:
1. A PCI device with a non-VGA class is the boot display
2.
On Wed, May 15, 2024 at 1:25 PM Yong Wu wrote:
>
> Add a MediaTek restricted heap which uses TEE service call to restrict
> buffer. Currently this restricted heap is NULL, Prepare for the later
> patch. Mainly there are two changes:
> a) Add a heap_init ops since TEE probe late than restricted hea
Am 21.08.24 um 21:11 schrieb Alex Deucher:
In aperture_remove_conflicting_pci_devices(), we currently only
call sysfb_disable() on vga class devices. This leads to the
following problem when the pimary device is not VGA compatible:
1. A PCI device with a non-VGA class is the boot display
2.
Hi Dave, Sima,
here's this week's PR for drm-misc-next. It adds support for more
panels, and easier error handling for DSI code. Ast should finally
have decent support for BMC output. Plus the usual bug fixes.
In the kernel's string helpers there's the new function mem_is_zero(),
which the EDID c
Hi Harry,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-exynos/exynos-drm-next drm-intel/for-linux-next
drm-intel/for-linux-next-fixes drm-misc/drm-misc-next drm-tip/drm-tip
linus/master v6.11-rc4 next-20240822]
[If
Alex Deucher writes:
Hello Alex,
> In aperture_remove_conflicting_pci_devices(), we currently only
> call sysfb_disable() on vga class devices. This leads to the
> following problem when the pimary device is not VGA compatible:
>
> 1. A PCI device with a non-VGA class is the boot display
> 2. T
On 21/08/2024 13:12, Gerd Hoffmann wrote:
On Tue, Aug 20, 2024 at 11:07:40AM GMT, Jocelyn Falempe wrote:
Mesa doesn't support BGRX, that means most wayland compositors
don't work on big endian guests.
So you are doing a hard switch from native endian to little endian.
While this should be
Hi
Am 12.08.24 um 08:59 schrieb Al Viro:
Once something had been put into descriptor table, the only thing you
can do with it is returning descriptor to userland - you can't withdraw
it on subsequent failure exit, etc. You certainly can't count upon
it staying in the same slot of descriptor tab
On Mon, Aug 19, 2024 at 03:38:30PM -0700, Stephen Boyd wrote:
> @@ -671,6 +674,20 @@ static int cros_typec_configure_mux(struct
> cros_typec_data *typec, int port_num,
> if (port->mux_flags == resp.flags && port->role == pd_ctrl->role)
> return 0;
>
> + dp_enabled = resp.
On Mon, Aug 19, 2024 at 03:38:29PM -0700, Stephen Boyd wrote:
> +struct cros_typec_dp_bridge {
> + struct cros_typec_data *typec_data;
> + struct drm_dp_typec_bridge_dev *dev;
> +};
It looks like structs are all defined in cros_ec_typec.h. I think this struct
definition can be also moved
On Mon, Aug 19, 2024 at 03:38:27PM -0700, Stephen Boyd wrote:
> -title: Google Chrome OS EC(Embedded Controller) Type C port driver.
> +title: Google Chrome OS Embedded Controller (EC) USB type-c port driver
Given that it gets chance to modify, how about s/Chrome OS/ChromeOS/?
On 16 Aug 2024, at 14:32, Zack Rusin wrote:
> This is the same series I've sent out earlier but with one extra patch,
> that fixes the dumb buffer coherency on low mem systems.
>
> The second patch has also been updated to not use math functions.
>
> Zack Rusin (3):
> drm/vmwgfx: Prevent unmappi
On Wed, Aug 21, 2024 at 9:06 AM Thomas Zimmermann wrote:
>
> Call drm_client_setup() to run the kernel's default client setup
> for DRM. Set fbdev_probe in struct drm_driver, so that the client
> setup can start the common fbdev client.
>
> The amdgpu driver specifies a preferred color mode depend
Hi, Rob:
Rob Herring (Arm) 於 2024年8月1日 週四 上午4:14寫道：
>
> of_property_read_u32() returns -EINVAL if a property is not present, so
> the preceeding check for presence with of_find_property() can be
> dropped. Really, what the errno is shouldn't matter. Either the property
> can be read and used or i
Hi,
On Thu, Aug 22, 2024 at 3:02 AM cong yang
wrote:
>
> Hi,
>
> Charles Han 于2024年8月22日周四 17:34写道：
> >
> > In hx83102_get_modes(), the return value of drm_mode_duplicate()
> > is assigned to mode, which will lead to a possible NULL
> > pointer dereference on failure of drm_mode_duplicate(). Add
Hi, Angelo:
AngeloGioacchino Del Regno 於
2024年7月18日 週四 下午4:25寫道：
>
> MediaTek SoCs support multiple planes, one of which is the primary
> and all the others are overlays (and CURSOR is the last overlay).
>
> In all currently supported SoCs, the Z order of the overlays can't
> be changed with any
Hi, Jason:
Jason-JH.Lin via B4 Relay
於 2024年8月19日 週一
下午11:26寫道：
>
> From: "Jason-JH.Lin"
>
> In mtk_crtc_ddp_config(), mtk_crtc will use some configuration flags to
> generate instructions to cmdq_handle, such as:
> state->pending_config
> mtk_crtc->pending_planes
> plane_state->pending.co
Hi Hongchi,
On Wed, Aug 21, 2024 at 04:56:13PM +0800, hongchi.peng wrote:
> We use komeda_crtc_normalize_zpos to normalize zpos of affected planes
> to their blending zorder in CU. If there's only one slave plane in
> affected planes and its layer_split property is enabled, order++ for
> its split
On 8/21/24 09:00, Thomas Zimmermann wrote:
Call drm_client_setup() to run the kernel's default client setup
for DRM. Set fbdev_probe in struct drm_driver, so that the client
setup can start the common fbdev client.
The amdgpu driver specifies a preferred color mode depending on
the available vid
On Mon, 19 Aug 2024, Stephen Boyd wrote:
> This binding is about USB type-c control. Move the binding to the usb
> directory as it's a better home than chrome.
>
> Cc: Rob Herring
> Cc: Krzysztof Kozlowski
> Cc: Conor Dooley
> Cc: Lee Jones
> Cc: Benson Leung
> Cc: Guenter Roeck
> Cc: Prash
On 8/22/2024 01:14, Thomas Weißschuh wrote:
On 2024-08-21 15:54:14+, Mario Limonciello wrote:
On 8/18/2024 01:56, Thomas Weißschuh wrote:
Not all platforms provide correct PWM backlight capabilities through ATIF.
I don't think correct is an accurate term here. How about 'optimial'?
Loo
On 8/22/2024 01:12, Thomas Weißschuh wrote:
On 2024-08-21 15:51:17+, Mario Limonciello wrote:
On 8/18/2024 01:56, Thomas Weißschuh wrote:
Panels using a PWM-controlled backlight source do not have a standard
way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI thr
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