https://bugzilla.kernel.org/show_bug.cgi?id=201497
--- Comment #35 from Emre (ereno...@gmail.com) ---
Hi Artem, I did not see my issue (stated above) since the last few kernel
releases. I'm now at 6.9.9-arch1-1. These days it seemed reliable to me.
Sometimes I'm losing "4k resolution" but that may
Hi Thomas,
Sorry for the miss, and thanks for your help.
Regards,
Jammy Huang
> -Original Message-
> From: Thomas Zimmermann
> Sent: Thursday, July 18, 2024 4:02 PM
> To: Jammy Huang ; jfale...@redhat.com;
> maarten.lankho...@linux.intel.com; mrip...@kernel.org; airl...@redhat.com;
> ai
* Dmitry Baryshkov (dmitry.barysh...@linaro.org) wrote:
> On Thu, Jul 18, 2024 at 05:49:22PM GMT, Dr. David Alan Gilbert wrote:
> > * Dmitry Baryshkov (dmitry.barysh...@linaro.org) wrote:
> > > On Mon, May 20, 2024 at 01:55:51PM +0100, li...@treblig.org wrote:
> > > > From: "Dr. David Alan Gilbert"
Hi,
On Thu, Jul 18, 2024 at 11:44 AM Rob Clark wrote:
>
> From: Rob Clark
>
> The Samsung ATNA45DC02 panel needs the same power sequencing as the
> ATNA45AF01 and ATNA33XC20.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/panel/panel-samsung-atna33xc20.c | 1 +
> 1 file changed, 1 insert
Hi,
On Thu, Jul 18, 2024 at 2:36 PM Dmitry Baryshkov
wrote:
>
> On Thu, Jul 18, 2024 at 11:44:32AM GMT, Rob Clark wrote:
> > From: Rob Clark
> >
> > The Samsung ATNA45DC02 panel is an AMOLED eDP panel, similar to the
> > existing ATNA45AF01 and ATNA33XC20 panel but with a higher resolution.
> >
On 19/7/24 02:58, Danilo Krummrich wrote:
Hi Christian,
Those three patches should unblock your series to use GEM references instead of
TTM ones.
@Lyude, Dave: Can you please double check?
Hi Danilo,
These look fine to me, and appear to resolve the issues I see with just
the refcount serie
Hi Dave, Sima,
Fixes for 6.11.
The following changes since commit 1cff1010bef6f325d895db0306b59dc7232ed9b7:
drm/amdgpu/mes12: add missing opcode string (2024-07-12 11:46:46 -0400)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.1
On Thu, Jul 18, 2024 at 05:49:22PM GMT, Dr. David Alan Gilbert wrote:
> * Dmitry Baryshkov (dmitry.barysh...@linaro.org) wrote:
> > On Mon, May 20, 2024 at 01:55:51PM +0100, li...@treblig.org wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > commit 6a1688ae8794 ("drm/bridge: ptn3460: Conver
On Thu, Jul 18, 2024 at 11:44:32AM GMT, Rob Clark wrote:
> From: Rob Clark
>
> The Samsung ATNA45DC02 panel is an AMOLED eDP panel, similar to the
> existing ATNA45AF01 and ATNA33XC20 panel but with a higher resolution.
>
> Signed-off-by: Rob Clark
> ---
> .../devicetree/bindings/display/panel
On 6/24/24 09:43, Vivek Kasireddy wrote:
> +static void virtgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
> +{
> + struct drm_gem_object *obj = attach->importer_priv;
> + struct virtio_gpu_device *vgdev = obj->dev->dev_private;
> + struct virtio_gpu_object *bo = gem_to_virt
The pull request you sent on Thu, 18 Jul 2024 17:56:03 +0200:
> http://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git
> tags/fbdev-for-6.11-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/cb273eb7c8390c70a484db6c79a797e377db09b5
Thank you!
--
Dee
On 7/18/2024 6:27 PM, Matthew Auld wrote:
On 04/07/2024 09:18, Nirmoy Das wrote:
On LNL because of flat CCS, driver creates a migrate job to clear
CCS meta data. Extend that to also clear system pages using GPU.
Inform TTM to allocate pages without __GFP_ZERO to avoid double page
clearing by cl
From: Rob Clark
The Samsung ATNA45DC02 panel needs the same power sequencing as the
ATNA45AF01 and ATNA33XC20.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/panel/panel-samsung-atna33xc20.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c
b/d
From: Rob Clark
The Samsung ATNA45DC02 panel is an AMOLED eDP panel, similar to the
existing ATNA45AF01 and ATNA33XC20 panel but with a higher resolution.
Signed-off-by: Rob Clark
---
.../devicetree/bindings/display/panel/samsung,atna33xc20.yaml | 2 ++
1 file changed, 2 insertions(+)
diff
On 7/18/2024 6:40 PM, Matthew Auld wrote:
On 04/07/2024 09:18, Nirmoy Das wrote:
Clearing bo with uncompress PTE will trigger a CCS clearing as well
for XE2, so skip emit_copy_ccs() when on xe2 when clearing bo.
v2: When clearing BO, CCS clear happens with all command as long
as PTEs are
* Dmitry Baryshkov (dmitry.barysh...@linaro.org) wrote:
> On Mon, May 20, 2024 at 01:55:51PM +0100, li...@treblig.org wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > commit 6a1688ae8794 ("drm/bridge: ptn3460: Convert to I2C driver model")
> > has dropped all the users of the struct bridge_init
On Thu, Jul 18, 2024 at 9:45 AM Rob Clark wrote:
>
> On Thu, Jul 18, 2024 at 9:31 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Thu, Jul 18, 2024 at 9:25 AM Rob Clark wrote:
> > >
> > > On Thu, Jul 18, 2024 at 9:00 AM Doug Anderson
> > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > On Wed, Jul
The pull request you sent on Thu, 18 Jul 2024 15:40:08 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-next-2024-07-18
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/b3ce7a30847a54a7f96a35e609303d8afecd460b
Thank you!
--
Deet-doot-dot, I am a bot.
ht
https://bugzilla.kernel.org/show_bug.cgi?id=201497
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
CC||a...@gmx.com
--- Comm
TTM wants to get rid of the duplicate refcounting of the embedded GEM
object and its own reference count.
Hence, use of GEM object references where possible.
Also get rid of nouveau_bo_ref() and replace it with nouveau_bo_fini(),
which drops the initial reference we get from initializing a ttm_bo
Hi Christian,
Those three patches should unblock your series to use GEM references instead of
TTM ones.
@Lyude, Dave: Can you please double check?
- Danilo
Danilo Krummrich (3):
drm/nouveau: prime: fix refcount underflow
drm/nouveau: bo: remove unused functions
drm/nouveau: use GEM refere
nouveau_bo_new_pin_map() and nouveau_bo_unmap_unpin_unref() are unused,
hence remove them.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_bo.h | 29
1 file changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h
b/drivers/gpu
Calling nouveau_bo_ref() on a nouveau_bo without initializing it (and
hence the backing ttm_bo) leads to a refcount underflow.
Instead of calling nouveau_bo_ref() in the unwind path of
drm_gem_object_init(), clean things up manually.
Fixes: ab9ccb96a6e6 ("drm/nouveau: use prime helpers")
Signed-o
On Thu, Jul 18, 2024 at 9:31 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Jul 18, 2024 at 9:25 AM Rob Clark wrote:
> >
> > On Thu, Jul 18, 2024 at 9:00 AM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Wed, Jul 17, 2024 at 6:09 PM Rob Clark wrote:
> > > >
> > > > On Wed, Jul 17, 2024 at 5:1
On 04/07/2024 09:18, Nirmoy Das wrote:
Clearing bo with uncompress PTE will trigger a CCS clearing as well
for XE2, so skip emit_copy_ccs() when on xe2 when clearing bo.
v2: When clearing BO, CCS clear happens with all command as long
as PTEs are uncompress.
Cc: Himal Prasad Ghimiray
Cc:
Hi,
On Thu, Jul 18, 2024 at 9:25 AM Rob Clark wrote:
>
> On Thu, Jul 18, 2024 at 9:00 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Wed, Jul 17, 2024 at 6:09 PM Rob Clark wrote:
> > >
> > > On Wed, Jul 17, 2024 at 5:19 PM Doug Anderson
> > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > On Wed,
On 04/07/2024 09:18, Nirmoy Das wrote:
On LNL because of flat CCS, driver creates a migrate job to clear
CCS meta data. Extend that to also clear system pages using GPU.
Inform TTM to allocate pages without __GFP_ZERO to avoid double page
clearing by clearing out TTM_TT_FLAG_ZERO_ALLOC flag and s
On Thu, Jul 18, 2024 at 9:00 AM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Jul 17, 2024 at 6:09 PM Rob Clark wrote:
> >
> > On Wed, Jul 17, 2024 at 5:19 PM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Wed, Jul 17, 2024 at 2:58 PM Rob Clark wrote:
> > > >
> > > > From: Rob Clark
> > > >
>
Dumb buffers can be used in kms but also through prime with gallium's
resource_from_handle. In the second case the dumb buffers can be
rendered by the GPU where with the regular DRM kms interfaces they
are mapped and written to by the CPU. Because the same buffer can
be written to by the GPU and CP
Make vmwgfx go through the dma-buf interface to map/unmap imported
buffers. The driver used to try to directly manipulate external
buffers, assuming that everything that was coming to it had to live
in cpu accessible memory. While technically true because what's in the
vms is controlled by us, it's
Fix races issues in virtual crc generation by making sure the surface
the code uses for crc computation is properly ref counted.
Crc generation was trying to be too clever by allowing the surfaces
to go in and out of scope, with the hope of always having some kind
of screen present. That's not alw
Introduce a version of the fence ops that on release doesn't remove
the fence from the pending list, and thus doesn't require a lock to
fix poll->fence wait->fence unref deadlocks.
vmwgfx overwrites the wait callback to iterate over the list of all
fences and update their status, to do that it hol
This small series fixes all known prime/dumb_buffer/buffer dirty
tracking issues. Fixing of dumb-buffers turned out to be a lot more
complex than I wanted it to be. There's not much that can be done
there because the driver has to support old userspace (our Xorg driver
expects those to not be gem b
Hi,
On Wed, Jul 17, 2024 at 6:09 PM Rob Clark wrote:
>
> On Wed, Jul 17, 2024 at 5:19 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Wed, Jul 17, 2024 at 2:58 PM Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > Just a guess on the panel timings, but they appear to work.
> > >
> > > Sig
Hi Linus,
please pull a bunch of usual cleanups for the fbdev drivers for kernel 6.11-rc1.
Thanks!
Helge
The following changes since commit 83a7eefedc9b56fe7bfeff13b6c7356688ffa670:
Linux 6.10-rc3 (2024-06-09 14:19:43 -0700)
ar
On Tue, Jul 09, 2024 at 08:50:35AM GMT, Krzysztof Kozlowski wrote:
> On 08/07/2024 16:52, Maxime Ripard wrote:
> > On Mon, Jul 08, 2024 at 04:04:21PM GMT, Krzysztof Kozlowski wrote:
> >> On 08/07/2024 08:40, Liu Ying wrote:
> > +
> > + "^framegen@[0-9a-f]+$":
> > +type: object
> >>
Hi Dave and Sima,
It is worth to mention that although there's a fix on xe_exec ioctl,
that should not cause any uapi change. It would only fix a potential
crash in the case that xe_ioctl failed with a bad sync array as input.
Thanks,
Rodrigo.
drm-xe-next-fixes-2024-07-18:
- Xe_exec ioctl minor
On Thu, Jul 18, 2024 at 5:31 AM Dmitry Baryshkov
wrote:
>
> On Wed, Jul 17, 2024 at 06:09:29PM GMT, Rob Clark wrote:
> > On Wed, Jul 17, 2024 at 5:19 PM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Wed, Jul 17, 2024 at 2:58 PM Rob Clark wrote:
> > > >
> > > > From: Rob Clark
> > > >
> >
Applied. Thanks!
Alex
On Thu, Jul 18, 2024 at 10:17 AM Ma Ke wrote:
>
> Return 0 to avoid returning an uninitialized variable r.
>
> Cc: sta...@vger.kernel.org
> Fixes: 230dd6bb6117 ("drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10")
> Signed-off-by: Ma Ke
> ---
> Changes in v2:
> - adde
Applied. Thanks!
On Thu, Jul 18, 2024 at 10:12 AM Ma Ke wrote:
>
> In amdgpu_connector_add_common_modes(), the return value of drm_cvt_mode()
> is assigned to mode, which will lead to a NULL pointer dereference on
> failure of drm_cvt_mode(). Add a check to avoid npd.
>
> Cc: sta...@vger.kernel.
Hi,
On Thu, Jul 18, 2024 at 7:56 AM Conor Dooley wrote:
>
> On Thu, Jul 18, 2024 at 07:45:57AM -0700, Doug Anderson wrote:
> > Hi,
> >
> > On Wed, Jul 17, 2024 at 11:19 PM Krzysztof Kozlowski
> > wrote:
> > >
> > > On 18/07/2024 02:21, Doug Anderson wrote:
> > > > Conor (and/or) Krzysztof and R
On Thu, Jul 18, 2024 at 07:45:57AM -0700, Doug Anderson wrote:
> Hi,
>
> On Wed, Jul 17, 2024 at 11:19 PM Krzysztof Kozlowski wrote:
> >
> > On 18/07/2024 02:21, Doug Anderson wrote:
> > > Conor (and/or) Krzysztof and Rob,
> > >
> > > On Mon, Jul 15, 2024 at 8:31 AM Conor Dooley wrote:
> > >>
>
Hi,
On Wed, Jul 17, 2024 at 11:19 PM Krzysztof Kozlowski wrote:
>
> On 18/07/2024 02:21, Doug Anderson wrote:
> > Conor (and/or) Krzysztof and Rob,
> >
> > On Mon, Jul 15, 2024 at 8:31 AM Conor Dooley wrote:
> >>
> >> On Mon, Jul 15, 2024 at 02:15:37PM +0200, Stephan Gerhold wrote:
> >>> The Sam
Return 0 to avoid returning an uninitialized variable r.
Cc: sta...@vger.kernel.org
Fixes: 230dd6bb6117 ("drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10")
Signed-off-by: Ma Ke
---
Changes in v2:
- added Cc stable line.
---
drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 2 +-
1 file changed,
In amdgpu_connector_add_common_modes(), the return value of drm_cvt_mode()
is assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_cvt_mode(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: M
Applied. Thanks!
Alex
On Thu, Jul 18, 2024 at 9:13 AM Ma Ke wrote:
>
> In radeon_add_common_modes(), the return value of drm_cvt_mode() is
> assigned to mode, which will lead to a possible NULL pointer dereference
> on failure of drm_cvt_mode(). Add a check to avoid npd.
>
> Cc: sta...@vger.ker
In qxl_add_mode(), the return value of drm_cvt_mode() is assigned to mode,
which will lead to a possible NULL pointer dereference on failure of
drm_cvt_mode(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: 1b043677d4be ("drm/qxl: add qxl_add_mode helper function")
Signed-off-by: Ma K
In radeon_add_common_modes(), the return value of drm_cvt_mode() is
assigned to mode, which will lead to a possible NULL pointer dereference
on failure of drm_cvt_mode(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: d50ba256b5f1 ("drm/kms: start adding command line interface using f
In drm_client_modeset_probe(), the return value of drm_mode_duplicate() is
assigned to modeset->mode, which will lead to a possible NULL pointer
dereference on failure of drm_mode_duplicate(). Add a check to avoid npd.
Cc: sta...@vger.kernel.org
Fixes: cf13909aee05 ("drm/fb-helper: Move out modese
On Wed, Jul 17, 2024 at 06:09:29PM GMT, Rob Clark wrote:
> On Wed, Jul 17, 2024 at 5:19 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Wed, Jul 17, 2024 at 2:58 PM Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > Just a guess on the panel timings, but they appear to work.
> > >
> > > Sig
On 17.07.2024 6:36 PM, Rob Clark wrote:
> From: Rob Clark
>
> In the case of iova fault triggered devcore dumps, include additional
> debug information based on what we think is the current page tables,
> including the TTBR0 value (which should match what we have in
> adreno_smmu_fault_info unles
On Thu, 11 Jul 2024 14:26:55 +0300, Cristian Ciocaltea wrote:
> The recent switch to drmm allocation in drm_bridge_connector_init() may
> cause double free on bridge_connector in some of the error handling
> paths.
>
> Drop the explicit kfree() calls on bridge_connector.
>
>
> [...]
Applied, th
Hi
Am 18.07.24 um 13:34 schrieb Jocelyn Falempe:
On 18/07/2024 12:44, Thomas Zimmermann wrote:
There's no VBLANK interrupt on Matrox chipsets. The workaround that is
being used here and in other free Matrox drivers is to program
to the value of and enable the VLINE interrupt. This trigger
On 18/07/2024 12:44, Thomas Zimmermann wrote:
There's no VBLANK interrupt on Matrox chipsets. The workaround that is
being used here and in other free Matrox drivers is to program
to the value of and enable the VLINE interrupt. This triggers
an interrupt at the time when VBLANK begins.
VLIN
On 03/07/2024 07:57, Amirreza Zarrabi wrote:
> Qualcomm TEE hosts Trusted Applications and Services that run in the
> secure world. Access to these resources is provided using object
> capabilities. A TEE client with access to the capability can invoke
> the object and request a service. Similarly,
On Wed, 03 Jul 2024 14:27:15 +0200, Alexander Stein wrote:
> When -EPROBE_DEFER is returned do not raise an error, but silently return
> this error instead. Fixes error like this:
> [drm:drm_bridge_attach] *ERROR* failed to attach bridge
> /soc@0/bus@3080/mipi-dsi@30a0 to encoder None-34:
Il 18/07/24 13:10, Daniel Stone ha scritto:
Hi all,
On Thu, 18 Jul 2024 at 11:24, AngeloGioacchino Del Regno
wrote:
Il 18/07/24 11:27, Fei Shao ha scritto:
This matches my preference in [1], so of course I'd like to see it
merged... if maintainers are okay with it.
Given I've tested the exact
Il 18/07/24 13:15, Daniel Stone ha scritto:
Hi,
On Thu, 18 Jul 2024 at 09:25, AngeloGioacchino Del Regno
wrote:
MediaTek SoCs support multiple planes, one of which is the primary
and all the others are overlays (and CURSOR is the last overlay).
In all currently supported SoCs, the Z order of
On 17/07/2024 20:52, Deborah Brouwer wrote:
Before building an image, the build script looks to see if there are fixes
to apply from an upstream repository. The link for the upstream repository
git://anongit.freedesktop.org/drm/drm became obsolete with the move to
Gitlab server in March 2024.
Hi,
On Thu, 18 Jul 2024 at 09:25, AngeloGioacchino Del Regno
wrote:
> MediaTek SoCs support multiple planes, one of which is the primary
> and all the others are overlays (and CURSOR is the last overlay).
>
> In all currently supported SoCs, the Z order of the overlays can't
> be changed with any
Hi all,
On Thu, 18 Jul 2024 at 11:24, AngeloGioacchino Del Regno
wrote:
> Il 18/07/24 11:27, Fei Shao ha scritto:
> > This matches my preference in [1], so of course I'd like to see it
> > merged... if maintainers are okay with it.
> > Given I've tested the exact same change before:
> > Reviewed-
Hi,
On Thu, 18 Jul 2024 at 00:52, Deborah Brouwer
wrote:
> Before building an image, the build script looks to see if there are fixes
> to apply from an upstream repository. The link for the upstream repository
> git://anongit.freedesktop.org/drm/drm became obsolete with the move to
> Gitlab serv
Am 18.07.24 um 12:32 schrieb Arunpravin Paneer Selvam:
Add address alignment support to the DCC VRAM buffers.
v2:
- adjust size based on the max_texture_channel_caches values
only for GFX12 DCC buffers.
- used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only
for DCC buffers.
Implement support for VBLANK events in mgag200.
Patches 1 to 5 prepare mgag200's modesetting code by renaming or
adding variables for various hardware fields. This makes the code
more readable and aligns it with the programming manuals for Matrox
hardware.
Patch 6 implements support for VBLANK e
Represent fields for horizontal and vertical blanking with ,
, and . Aligns the code with the Matrox
programming manuals.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jocelyn Falempe
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 29 ++
1 file changed, 16 insertions(+),
There's no VBLANK interrupt on Matrox chipsets. The workaround that is
being used here and in other free Matrox drivers is to program
to the value of and enable the VLINE interrupt. This triggers
an interrupt at the time when VBLANK begins.
VLINE uses separate registers for enabling and clearing
Implement struct drm_crtc_funcs.get_vblank_timestamp with the DRM
helper drm_crtc_vblank_helper_get_vblank_timestamp() with its helper
get_scanout_position. Read the scanout position from the MGAREG_VCOUNT
register.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jocelyn Falempe
---
drivers/gpu/d
Use the values with the crtc_ prefix from struct drm_display_mode to
program hardware. The DRM core adjusted these values to the requirements
of CRTC hardware.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jocelyn Falempe
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 16
1 file
Replace the line-compare value of with a dedicated variable
. Improves readability and prepares for vblank support.
Signed-off-by: Thomas Zimmermann
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a
In mgag200_set_mode_regs(), use hexadecimal indices for accessing
registers. Aligns the code with the register indices in the Matrox
programming manuals. Also convert to lower-case hexadecimal values.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jocelyn Falempe
---
drivers/gpu/drm/mgag200/mgag
In mgag200_set_mode_regs(), align variable names with the field names
given in the Matrox programming manuals. Makes the code and docs grep-
able.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jocelyn Falempe
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 54 +-
1 file cha
Add address alignment support to the DCC VRAM buffers.
v2:
- adjust size based on the max_texture_channel_caches values
only for GFX12 DCC buffers.
- used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only
for DCC buffers.
- roundup non power of two DCC buffer adjusted size to nea
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in situations like if drivers would like to do address alignment
for specific requirements.
- Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this
flag to disab
Il 18/07/24 11:27, Fei Shao ha scritto:
On Thu, Jul 18, 2024 at 4:49 PM Chen-Yu Tsai wrote:
(CC-ed Fei Shao)
On Thu, Jul 18, 2024 at 4:24 PM AngeloGioacchino Del Regno
wrote:
Hardware-speaking, there is no feature-reduced cursor specific
plane, so this driver reserves the last all Overlay
The 6 panels are used on Mediatek MT8186 Chromebooks
- B116XAT04.1 (06AF/B4C4)
- NV116WHM-A4D (09E5/FA0C)
- N116BCP-EA2 (0DAE/6111)
- B116XTN02.3 (06AF/AA73)
- B116XAN06.1 (06AF/99A1)
- N116BCA-EA2 (0DAE/5D11)
Signed-off-by: Terry Hsiao
---
drivers/gpu/drm/panel/panel-edp.c | 6 ++
1 fi
Hi,
On Wed, 17 Jul 2024 at 18:01, Dmitry Baryshkov
wrote:
>
> Adding TEE mailing list and maintainers to the CC list.
Thanks. I am not going to reiterate what Jens said in the other thread
but going to cover some additional points.
>
> Amirreza, please include them in future even if you are not
Hi Easwar,
On Thu, Jul 11, 2024 at 05:27:31AM +, Easwar Hariharan wrote:
> I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced "master/slave"
> with more appropriate terms. Inspired by Wolfram's series to fix drivers/i2c/,
> fix the terminology for users of I2C_ALGOBIT bitbanging int
On Thu, Jul 18, 2024 at 4:25 PM AngeloGioacchino Del Regno
wrote:
>
> MediaTek SoCs support multiple planes, one of which is the primary
> and all the others are overlays (and CURSOR is the last overlay).
>
> In all currently supported SoCs, the Z order of the overlays can't
> be changed with any
Hi Dave, Sima,
One display fix for the merge window relating to DisplayPort LTTPR. It
fixes at least Dell UD22 dock when used on Intel N100 systems.
Regards,
Tvrtko
drm-intel-next-fixes-2024-07-18:
- Reset intel_dp->link_trained before retraining the link [dp] (Imre Deak)
- Don't switch the L
On 18/07/2024 09:04, Jocelyn Falempe wrote:
On 17/07/2024 17:08, Daniel Vetter wrote:
On Wed, Jul 17, 2024 at 10:48:39AM +0200, Jocelyn Falempe wrote:
It allows to check if the drm device supports drm_panic.
Prepare the work to have better integration with fbcon and vtconsole.
Signed-off-
On Thu, Jul 18, 2024 at 4:49 PM Chen-Yu Tsai wrote:
>
> (CC-ed Fei Shao)
>
> On Thu, Jul 18, 2024 at 4:24 PM AngeloGioacchino Del Regno
> wrote:
> >
> > Hardware-speaking, there is no feature-reduced cursor specific
> > plane, so this driver reserves the last all Overlay plane as a
> > Cursor pla
(CC-ed Fei Shao)
On Thu, Jul 18, 2024 at 4:24 PM AngeloGioacchino Del Regno
wrote:
>
> Hardware-speaking, there is no feature-reduced cursor specific
> plane, so this driver reserves the last all Overlay plane as a
> Cursor plane, but sets the maximum cursor width/height to the
> maximum value th
On Thu, Jul 18, 2024 at 06:54:17AM +, Omer Shpigelman wrote:
> On 7/17/24 15:33, Leon Romanovsky wrote:
> > On Wed, Jul 17, 2024 at 10:51:03AM +, Omer Shpigelman wrote:
> >> On 7/17/24 10:36, Leon Romanovsky wrote:
> >>> On Wed, Jul 17, 2024 at 07:08:59AM +, Omer Shpigelman wrote:
> >>>
Hi Thomas,
On 6/24/24 6:15 PM, Thomas Weißschuh wrote:
> Hi Hans!
>
> thanks for your feedback!
>
> On 2024-06-24 11:11:40+, Hans de Goede wrote:
>> On 6/23/24 10:51 AM, Thomas Weißschuh wrote:
>>> The value of "min_input_signal" returned from ATIF on a Framework AMD 13
>>> is "12". This lea
MediaTek SoCs support multiple planes, one of which is the primary
and all the others are overlays (and CURSOR is the last overlay).
In all currently supported SoCs, the Z order of the overlays can't
be changed with any fast muxing action, and can only be changed by
swapping the contents of the en
Hardware-speaking, there is no feature-reduced cursor specific
plane, so this driver reserves the last all Overlay plane as a
Cursor plane, but sets the maximum cursor width/height to the
maximum value that the full overlay plane can use.
While this could be ok, it raises issues with common usersp
Am 18.07.24 um 08:50 schrieb Thomas Zimmermann:
(Cary, this looks like it fixes the problem you reported.)
Hi Jammy
Am 18.07.24 um 05:03 schrieb Jammy Huang:
Suspend will disable pcie device. Thus, resume should do full hw
initialization again.
Add some APIs to ast_drm_thaw() before ast_pos
On 17/07/2024 17:04, Daniel Vetter wrote:
On Wed, Jul 17, 2024 at 10:48:40AM +0200, Jocelyn Falempe wrote:
This is required to avoid conflict between DRM_PANIC, and fbcon. If
a drm device already handle panic with drm_panic, it should set
the skip_panic field in fb_info, so that fbcon will st
On 17/07/2024 17:08, Daniel Vetter wrote:
On Wed, Jul 17, 2024 at 10:48:39AM +0200, Jocelyn Falempe wrote:
It allows to check if the drm device supports drm_panic.
Prepare the work to have better integration with fbcon and vtconsole.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_
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