On Wed, Jun 5, 2024 at 7:15 PM AngeloGioacchino Del Regno
wrote:
>
> Il 05/06/24 03:38, CK Hu (胡俊光) ha scritto:
> > Hi, Angelo:
> >
> > On Tue, 2024-05-21 at 09:57 +0200, AngeloGioacchino Del Regno wrote:
> >> Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths
> >> per HW insta
On Wed, Jun 5, 2024 at 7:25 PM AngeloGioacchino Del Regno
wrote:
>
> Il 05/06/24 10:25, Chen-Yu Tsai ha scritto:
> > On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
> > wrote:
> >>
> >> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> >>> The MFG_ASYNC domain, which is likely associated t
On Thu, Jun 06, 2024 at 02:17:02AM +0200, Andi Shyti wrote:
> The ce->guc_state.lock was made to protect guc_prio, which
> indicates the GuC priority level.
>
> But at the begnning of the function we perform some sanity check
> of guc_prio outside its protected section. Move them within the
> lock
On Wed, Jun 5, 2024 at 7:02 PM Barry Song <21cn...@gmail.com> wrote:
>
> From: Barry Song
>
> dma_heap_allocation_data defines the UAPI as follows:
>
> struct dma_heap_allocation_data {
> __u64 len;
> __u32 fd;
> __u32 fd_flags;
> __u64 heap_flags;
> };
>
> But dm
On Mon, Jun 3, 2024 at 1:24 PM Dr. David Alan Gilbert wrote:
>
> * li...@treblig.org (li...@treblig.org) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > 'vmw_stdu_dma' is unused since
> > commit 39985eea5a6d ("drm/vmwgfx: Abstract placement selection")
> > Remove it.
>
> Ping.
Thanks. I pushed
Hi Janusz,
On Tue, Jun 04, 2024 at 05:27:24PM +0200, Janusz Krzysztofik wrote:
> On Tuesday, 4 June 2024 02:48:43 GMT+2 Andi Shyti wrote:
> > On Mon, Jun 03, 2024 at 09:54:45PM +0200, Janusz Krzysztofik wrote:
> > > CI has been sporadically reporting the following issue triggered by
> > > igt@i915
Hi Krzysztof,
On Mon, Jun 03, 2024 at 06:20:22PM +0200, Niemiec, Krzysztof wrote:
> The test is trying to push the heartbeat frequency to the limit, which
> might sometimes fail. Such a failure does not provide valuable
> information, because it does not indicate that there is something
> necessar
On 6/5/24 2:23 PM, Yi Liu wrote:
On 2024/6/5 10:00, Baolu Lu wrote:
On 6/4/24 4:03 PM, Yi Liu wrote:
On 2024/6/4 09:51, Lu Baolu wrote:
Commit <909f4abd1097> ("iommu: Add new iommu op to create domains owned
by userspace") added a dedicated iommu op to allocate a user domain.
While IOMMUFD has
When the `power_saving_policy` property is set to bit mask
"Require color accuracy" ABM should be disabled immediately and
any requests by sysfs to update will return an -EBUSY error.
When the `power_saving_policy` property is set to bit mask
"Require low latency" PSR should be disabled.
When the
During the Display Next hackfest 2024 one of the topics discussed
was the need for compositor to be able to relay intention to drivers
that color fidelity is preferred over power savings.
To accomplish this a new optional DRM property is being introduced called
"power saving policy". This propert
The `power saving policy` DRM property is an optional property that
can be added to a connector by a driver.
This property is for compositors to indicate intent of policy of
whether a driver can use power saving features that may compromise
the experience intended by the compositor.
Acked-by: Leo
From: Barry Song
dma_heap_allocation_data defines the UAPI as follows:
struct dma_heap_allocation_data {
__u64 len;
__u32 fd;
__u32 fd_flags;
__u64 heap_flags;
};
But dma heaps are casting both fd_flags and heap_flags into
unsigned long. This patch makes dma he
On Thu, 30 May 2024 20:16:05 +
Mina Almasry wrote:
> @@ -42,51 +42,52 @@ TRACE_EVENT(page_pool_release,
> TRACE_EVENT(page_pool_state_release,
>
> TP_PROTO(const struct page_pool *pool,
> - const struct page *page, u32 release),
> + netmem_ref netmem, u32 re
On Wed, 5 Jun 2024 02:52:29 +0200
Andrew Lunn wrote:
> > How is a compiler going to know that?
>
> It might have some heuristics to try to guess unlikely/likely, but
> that is not what we are talking about here.
>
> How much difference did 'always_inline' and 'noinline' make? Hopefully
> the
This includes both DRM objects created to support queues, groups and heaps,
and also objects whose pages are shared between the GPU and the MCU.
However, this doesn't include objects that hold the firmware's binary
regions, since these aren't owned by a render context and are allocated
only once a
Some drivers must allocate a considerable amount of memory for bookkeeping
structures and GPU's MCU-kernel shared communication regions. These are
often created as a result of the invocation of the driver's ioctl()
interface functions, so it is sensible to consider them as being owned by
the render
A previous commit brought in a sysfs knob to control the driver's profiling
status. This changeset flags jobs as being profiled according to the
driver's global profiling status, and picks one of two call instruction
arrays to insert into the ring buffer. One of them includes FW logic to
sample the
Drawing from the FW-calculated values in the previous commit, we can
increase the numbers for an open file by collecting them from finished jobs
when updating their group synchronisation objects.
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panthor/panthor_devfreq.c | 10 +
drivers/gpu/
Enable calculations of job submission times in clock cycles and wall
time. This is done by expanding the boilerplate command stream when running
a job to include instructions that compute said times right before an after
a user CS.
Those numbers are stored in the queue's group's sync objects BO, r
Just like it is already present in Panfrost, this commit introduces a DRM
device sysfs file that lets UM control the job accounting status in the
device.
The present commit only brings in the sysfs knob and also hides the cycles
and engine fdinfo tags when it's disabled, but leveraging it for job
Implement drm object's status callback.
Also, we consider a PRIME imported BO to be resident if its matching
dma_buf has an open attachment, which means its backing storage had already
been allocated.
Signed-off-by: Adrián Larumbe
Reviewed-by: Liviu Dudau
---
drivers/gpu/drm/panthor/panthor_ge
This patch series enables userspace utilities like gputop and nvtop to
query a render context's fdinfo file and figure out rates of engine
and memory utilisation.
Previous discussion can be found at
https://lore.kernel.org/dri-devel/20240423213240.91412-1-adrian.laru...@collabora.com/
Changelog:
The ce->guc_state.lock was made to protect guc_prio, which
indicates the GuC priority level.
But at the begnning of the function we perform some sanity check
of guc_prio outside its protected section. Move them within the
locked region.
Use this occasion to expand the if statement to make it clea
On 6/5/2024 4:32 PM, Dmitry Baryshkov wrote:
On Thu, 6 Jun 2024 at 02:19, Abhinav Kumar wrote:
On 3/13/2024 5:02 PM, Dmitry Baryshkov wrote:
Split dpu_plane_atomic_check() function into two pieces:
dpu_plane_atomic_check_nopipe() performing generic checks on the pstate,
without touching
On 3/13/2024 5:02 PM, Dmitry Baryshkov wrote:
Move a call to dpu_plane_check_inline_rotation() to the
dpu_plane_atomic_check_pipe() function, so that the rot90 constraints
are checked for both pipes. Also move rotation field from struct
dpu_plane_state to struct dpu_sw_pipe_cfg.
Signed-off-by
On Thu, 6 Jun 2024 at 02:19, Abhinav Kumar wrote:
>
>
>
> On 3/13/2024 5:02 PM, Dmitry Baryshkov wrote:
> > Split dpu_plane_atomic_check() function into two pieces:
> >
> > dpu_plane_atomic_check_nopipe() performing generic checks on the pstate,
> > without touching the associated pipe,
> >
> > an
On Sat, Jun 01, 2024 at 04:12:34PM +0300, Cristian Ciocaltea wrote:
> Document the Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller
> found on Rockchip RK3588 SoC family.
>
> Since RK3588 uses different clocks than previous Rockchip SoCs and also
> requires a couple of reset lines and so
On 3/13/2024 5:02 PM, Dmitry Baryshkov wrote:
Split dpu_plane_atomic_check() function into two pieces:
dpu_plane_atomic_check_nopipe() performing generic checks on the pstate,
without touching the associated pipe,
and
dpu_plane_atomic_check_pipes(), which takes into account used pipes.
Sig
On Fri, 31 May 2024 22:30:18 +0200, Marek Vasut wrote:
> Keep the list sorted numerically. No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Andrzej Hajda
> Cc: Conor Dooley
> Cc: Daniel Vetter
> Cc: David Airlie
> Cc: Jernej Skrabec
> Cc: Jonas Karlman
> Cc: Krzysztof Kozl
Am Mittwoch, 5. Juni 2024, 21:58:23 CEST schrieb Luis de Arquer:
> On 6/5/24 16:48, Heiko Stübner wrote:
> > Without this change, connecting to a DVI display does not work, and
> > reading the EDID ends in the "i2c read error" below.
>
> I had a lot of problems initially with the vendor driver on
On Wed, Jun 05, 2024 at 10:15:59AM +0200, Philipp Stanner wrote:
> The bit describing whether the PCI device is currently enabled is stored
> in struct pci_devres. Besides this struct being subject of a cleanup
> process, struct pci_device is in general the right place to store this
> information,
On Thu, Apr 25, 2024 at 03:56:26PM +0300, Andy Shevchenko wrote:
> The modpost script is not happy
>
> WARNING: modpost: missing MODULE_DESCRIPTION() in
> drivers/gpu/drm/drm_mipi_dbi.o
>
> because there is a missing module description.
>
> Add it to the module.
Any comments on this?
--
Wi
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.
Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that le
Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.
Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
1 f
There is no need to reinvent the wheel for simple read-match-set logic.
Make speedbin discovery and assignment generation independent.
This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
which has no representation in hardware whatshowever.
Signed-off-by: Konrad Dybcio
---
drive
In preparation for commonizing the speedbin handling code.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno
Add speebin data for A740, as found on SM8550 and derivative SoCs.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/
Recent (SM8550+ ish) Qualcomm SoCs have a new mechanism for precisely
identifying the specific SKU and the precise speed bin (in the general
meaning of this word, anyway): a pair of values called Product Code
and Feature Code.
Based on this information, we can deduce the available frequencies for
In preparation for parsing the chip "feature code" (FC) and "product
code" (PC) (essentially the parameters that let us conclusively
characterize the sillicon we're running on, including various speed
bins), move the socinfo version defines to the public header.
Signed-off-by: Konrad Dybcio
---
k up rbs
- Rebase on next-20240605
- Drop the already-applied ("Avoid a nullptr dereference when speedbin
setting fails")
Changes in v2:
- Separate moving existing and adding new defines
- Fix kerneldoc copypasta
- Remove some wrong comments and defines
- Remove assumed "max" v
On Tue, 27 Feb 2024 00:34:45 +0200, Dmitry Baryshkov wrote:
> The function dp_wait_hpd_asserted() uses pm_runtime_get_sync() and
> doesn't care about the return value. Potentially this can lead to
> unclocked access if for some reason resuming of the DP controller fails.
>
> Change the function
On Thu, 09 May 2024 21:40:41 +0200, Barnabás Czémán wrote:
> The irq_idx is unsigned so it cannot be lower than zero, better
> to change the condition to check if it is equal with zero.
> It could not cause any issue because a valid irq index starts from one.
>
>
Applied, thanks!
[1/1] drm/ms
On Wed, 22 May 2024 13:24:28 +0300, Dmitry Baryshkov wrote:
> In the DPU driver blank IRQ handling is called from a vblank worker and
> can happen outside of the irq_enable / irq_disable pair. Using the
> worker makes that completely asynchronous with the rest of the code.
> Revert commit d13f638
On Fri, 24 May 2024 23:01:12 +0800, Junhao Xie wrote:
> There are duplicate items in wb2_formats_rgb and wb2_formats_rgb_yuv,
> which cause weston assertions failed.
>
> weston: libweston/drm-formats.c:131: weston_drm_format_array_add_format:
> Assertion `!weston_drm_format_array_find_format(for
On 4.06.2024 8:10 PM, Barnabás Czémán wrote:
> From: Daniil Titov
>
> This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz),
> SDM439 (650 MHz).
>
> Signed-off-by: Daniil Titov
> Signed-off-by: Barnabás Czémán
> ---
Reviewed-by: Konrad Dybcio
Konrad
GCC diagnostic pragma method throws below warnings in some of the versions
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:16:9: warning: unknown
option after '#pragma GCC diagnostic' kind [-Wpragmas]
#pragma GCC diagnostic ignored "-Wunused-const-variable"
^
In file included from drivers/
Hi Nathan
On 6/5/2024 11:05 AM, Nathan Chancellor wrote:
Hi Abhinav,
Just a drive by style comment.
On Tue, Jun 04, 2024 at 05:38:28PM -0700, Abhinav Kumar wrote:
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 0a7717a4fc2f..a958e2
On Fri, May 24, 2024 at 07:27:00PM +0100, Dave Stevenson wrote:
> From: Phil Elwell
>
> Slave addresses for DMA are meant to be supplied as physical addresses
> (contrary to what struct snd_dmaengine_dai_dma_data does).
Can you use the same content for patch 14-17?
Frank
>
> Signed-off-by: Ph
On Fri, May 24, 2024 at 07:26:55PM +0100, Dave Stevenson wrote:
> There is a need to account for dma-ranges and iommus in the
> dma mapping process, and the public API for handling that is
> dma_map_resource.
what's means?
>
> Add support for mapping addresses to the DMA driver.
>
> Signed-off-
On Fri, May 24, 2024 at 07:26:53PM +0100, Dave Stevenson wrote:
> The code handling DMA mapping is currently incorrect and
> needs a sequence of fixups.
Can you descript what incorrect here?
> Move the mapping out into a separate function and structure
> to allow for those fixes to be applied mo
Hi Abhinav,
Just a drive by style comment.
On Tue, Jun 04, 2024 at 05:38:28PM -0700, Abhinav Kumar wrote:
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> index 0a7717a4fc2f..a958e2b3c025 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_g
On Fri, May 24, 2024 at 07:26:52PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> In preparation to support more platforms pass the dma_chan to the
> generic functions. This provides access to the DMA device and possible
> platform specific data.
why need this change? you can easy conver
On Fri, May 24, 2024 at 07:26:51PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> The parameters info and finalextrainfo are platform specific. So drop
> them by generating them within bcm2835_dma_create_cb_chain().
Drop 'info' and 'finalextrainfo' because these can be generated by
bcm2
On Fri, May 24, 2024 at 07:26:50PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Actually the criteria to increment source & destination address doesn't
> based on platform specific bits. It's just the DMA transfer direction which
> is translated into the info bits. So introduce two new
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enab
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as s
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
--v3:
- vrr.enable and cmrr.enable check together is not required as both
will be true at the same point in time. (Ankit)
-
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/inte
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++
drivers/gpu/drm/i915/i915_reg.h | 101 ---
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 234cb065ad82915ff8d06ce01e01c3e640b674d2 Add linux-next specific
files for 20240605
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202406051521.mroqvr5l-...@intel.com
https
On Wed, Jun 05, 2024 at 12:56:59PM +0200, Krzysztof Kozlowski wrote:
> DSI-attached devices could respond to more than one virtual channel
> number, thus their bindings are supposed to constrain the 'reg' property
> to match hardware. Add missing 'reg' constrain for DSI-attached display
> panels,
On 6/5/24 6:05 PM, Rob Herring wrote:
diff --git
a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml
b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml
index 2ad0cd6dd49e0..dcf56e996ee22 100644
--- a/Documentation/devicetree/bindings/display/bridge/to
On 6/5/24 6:03 PM, Rob Herring wrote:
Hi,
diff --git
a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml
b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml
index 2ad0cd6dd49e0..dcf56e996ee22 100644
--- a/Documentation/devicetree/bindings/display/brid
rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -324,7 +324,7 @@ static int mtk_mdp_rdma_probe(struct platform_device *pdev)
ret = component_add(dev, &mtk_mdp_rdma_component_ops);
if (ret != 0) {
pm_runtime_disable(dev);
- dev_err(dev, "Failed to add co
On Tue, Jun 04, 2024 at 06:06:22PM +, Matthew Brost wrote:
> On Mon, Jun 03, 2024 at 08:00:07PM +0200, Thorsten Blum wrote:
> > The if condition !A || A && B can be simplified to !A || B.
> >
> > Fixes the following Coccinelle/coccicheck warning reported by
> > excluded_middle.cocci:
> >
> >
On 6/5/24 12:52 PM, Alexander Stein wrote:
Hi Marek,
Hi,
The accuracy degrades with each call, until a full kHz frequency is reached,
because drm_display_mode.clock only accounts for kHz, but the PLL
calculation takes Hz into account.
Hm, I need to take a closer look at this one.
Do yo
On Fri, May 24, 2024 at 07:26:49PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Similar to the info generation, generate the final extra info with a
> separate function. This is necessary to introduce other platforms
> with different info bits.
Each patch commit is independent.
Intro
On Tue, Jun 04, 2024 at 11:42:31AM +0200, Alexander Stein wrote:
> Hi Marek,
>
> Am Freitag, 31. Mai 2024, 22:42:03 CEST schrieb Marek Vasut:
> > Document default DP port preemphasis configurable via new DT property
> > "toshiba,pre-emphasis". This is useful in case the DP link properties
> > are
On Fri, May 24, 2024 at 07:26:48PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Actually the generation of the Control Block info follows some simple
> rules. So handle this with a separate function to avoid open coding
> for every DMA operation. Another advantage is that we can easier
On Fri, May 31, 2024 at 10:42:03PM +0200, Marek Vasut wrote:
> Document default DP port preemphasis configurable via new DT property
> "toshiba,pre-emphasis". This is useful in case the DP link properties
> are known and starting link training from preemphasis setting of 0 dB
> is not useful. The p
On Fri, May 24, 2024 at 07:26:46PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Nowadays there is a generic property for dma-channel-mask in the DMA
> controller binding. So prefer this one instead of the old vendor specific
> one. Print a warning in case the old one is used. Btw use th
On Tue, Jun 04, 2024 at 10:02:29AM +0800, kernel test robot wrote:
> Hi Mario,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on drm-misc/drm-misc-next]
> [also build test ERROR on drm/drm-next drm-exynos/exynos-drm-next
> drm-intel/for-linux-next drm-intel/
Am Samstag, 1. Juni 2024, 15:12:35 CEST schrieb Cristian Ciocaltea:
> The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller supports
> the following features, among others:
>
> * Fixed Rate Link (FRL)
> * 4K@120Hz and 8K@60Hz video modes
> * Variable Refresh Rate (VRR) including Quick Med
Hello Sima,
thanks again for your comments. Not yet enough for me to clearly focus
what you are suggesting, but getting closer. See my questions below.
On Tue, 21 May 2024 14:01:19 +0200
Daniel Vetter wrote:
> On Mon, May 20, 2024 at 02:01:48PM +0200, Luca Ceresoli wrote:
> > Hello Daniel,
> >
On Tue, May 14, 2024 at 06:51:25PM +0200, Luca Ceresoli wrote:
> Hello Rob,
>
> +cc Srinivas and Miquèl for the NVMEM cell discussion below
>
> On Fri, 10 May 2024 11:36:25 -0500
> Rob Herring wrote:
>
> > On Fri, May 10, 2024 at 09:10:37AM +0200, Luca Ceresoli wrote:
> > > Add bindings for the
Applied. Thanks!
Alex
On Tue, Jun 4, 2024 at 9:07 AM Thorsten Blum wrote:
>
> The if conditions !A || A && B can be simplified to !A || B.
>
> Fixes the following Coccinelle/coccicheck warnings reported by
> excluded_middle.cocci:
>
> WARNING !A || A && B is equivalent to !A || B
>
On 6/5/24 2:48 PM, Neil Armstrong wrote:
> On 05/06/2024 12:11, Cristian Ciocaltea wrote:
>> On 6/5/24 12:34 AM, Cristian Ciocaltea wrote:
>>> On 6/4/24 11:41 PM, Sam Ravnborg wrote:
Hi Cristian.
On Tue, Jun 04, 2024 at 10:32:04PM +0300, Cristian Ciocaltea wrote:
> Hi Sam,
>
Hi,
Similar to Patch #1 this was sent by mistake. Please ignore this patch. I will
rebase my patch series and send the correct version.
Sorry for inconvenience.
Regards,
Mitul
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Wednesday, June 5, 2024 5:58 PM
>
Hi,
I made a mistake while creating patch and this was sent by mistake. Please
ignore this patch. I will rebase my patch series and send the correct version.
Sorry for inconvenience.
Regards,
Mitul
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Wednesday, J
On Fri, May 31, 2024 at 08:17:34PM +0300, Andy Shevchenko wrote:
> +Cc: Johan (via kernel.org)
>
> On Fri, May 31, 2024 at 08:14:43PM +0300, Andy Shevchenko wrote:
> > On Fri, May 31, 2024 at 07:56:12PM +0300, Andy Shevchenko wrote:
> > > Driver is quite outdated from the Linux kernel internal API
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enab
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enab
On 05/06/2024 12:43, AngeloGioacchino Del Regno wrote:
> Il 05/06/24 11:18, Steven Price ha scritto:
>> On 04/06/2024 13:39, AngeloGioacchino Del Regno wrote:
>>> MediaTek MT8188 has a Mali-G57 MC3 (Valhall-JM): add a new
>>> compatible and platform data using the same supplies and the
>>> same pow
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/inte
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enab
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++
drivers/gpu/drm/i915/i915_reg.h | 101 ---
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
From: Ville Syrjälä
It's probably a good idea to start protecting all macro arguments
to avoid any cargo-cult mistakes when people go looking for examples
of how to define these things.
Signed-off-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-8-ville
From: Ville Syrjälä
---
integration-manifest | 28
1 file changed, 28 insertions(+)
create mode 100644 integration-manifest
diff --git a/integration-manifest b/integration-manifest
new file mode 100644
index ..d840964a2208
--- /dev/null
+++ b/integratio
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
On Thu, 23 May 2024, Jani Nikula wrote:
> Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
> across the subsystem"), most of the extra warnings in the driver
> Makefile are redundant. Remove them.
>
> Note that -Wmissing-declarations and -Wmissing-prototypes are always
> enab
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