Hi Adam,
> -Original Message-
> From: Adam Ford
> Sent: Sunday, February 18, 2024 11:26 PM
> Subject: Re: RE: RE: [PATCH v2] drm/imagination: DRM_POWERVR should depend
> on ARCH_K3
>
> On Fri, Feb 16, 2024 at 8:14 AM Maxime Ripard wrote:
> >
> > On Fri, Feb 16, 2024 at 09:13:14AM +,
drm-misc-next
patch link:
https://lore.kernel.org/r/20240213064835.139464-17-uma.shankar%40intel.com
patch subject: [PATCH 16/28] drm/i915/color: Create a transfer function color
pipeline
config: i386-randconfig-141-20240217
(https://download.01.org/0day-ci/archive/20240218/202402180310
Hi Alexander,
Thanks for your comments,
get_edid function will be replace by edid_read as community update in the next
version.
B.R
Sandor
>
>
> Hi Sandor,
>
> thanks for the update.
>
> Am Sonntag, 4. Februar 2024, 11:21:49 CET schrieb Sandor Yu:
> > Add a new DRM DisplayPort and HDMI bridge d
Hi Maíra,
On 10/02/24 23:53, Maíra Canal wrote:
Hi Vignesh,
On 2/1/24 03:53, Vignesh Raman wrote:
Add job that runs igt on top of vkms.
Signed-off-by: Vignesh Raman
Acked-by: Jessica Zhang
Tested-by: Jessica Zhang
Acked-by: Maxime Ripard
Signed-off-by: Helen Koike
---
v2:
- do not mv mo
Hi Helen,
On 09/02/24 23:17, Helen Koike wrote:
On 01/02/2024 03:53, Vignesh Raman wrote:
Add job that runs igt on top of vkms.
Signed-off-by: Vignesh Raman
Acked-by: Jessica Zhang
Tested-by: Jessica Zhang
Acked-by: Maxime Ripard
Signed-off-by: Helen Koike
---
v2:
- do not mv modules t
Hi all,
After merging the drm tree, today's linux-next build (htmldocs) produced
these warnings:
include/uapi/drm/i915_drm.h:3579: warning: Function parameter or struct member
'branch' not described in 'drm_i915_query_guc_submission_version'
include/uapi/drm/i915_drm.h:3579: warning: Function pa
Hi all,
After merging the drm-intel tree, today's linux-next build (htmldocs)
produced this warning:
Documentation/gpu/i915:222: drivers/gpu/drm/i915/display/intel_cdclk.c:69:
ERROR: Unexpected indentation.
Introduced by commit
79e2ea2eaaa6 ("drm/i915/cdclk: Document CDCLK update methods")
Hi Christian,
On 2/16/2024 5:29 PM, Christian König wrote:
Am 16.02.24 um 12:46 schrieb Arunpravin Paneer Selvam:
On 2/16/2024 4:41 PM, Matthew Auld wrote:
On 16/02/2024 10:00, Arunpravin Paneer Selvam wrote:
Remove the duplicate list_splice_tail call when the
total_allocated < size condi
Hi Ondrej:
On 2/18/24 23:17, Ondřej Jirman wrote:
Hi Andy,
On Sun, Feb 18, 2024 at 07:14:56PM +0800, Andy Yan wrote:
Hi,
On 2/18/24 02:39, Ondřej Jirman wrote:
From: Ondrej Jirman
On RK3399 one MIPI DSI device can be alternatively used with the ISP1,
to provide RX DPHY. When this is the ca
On 2/16/24 19:02, Thierry Reding wrote:
On Wed Feb 14, 2024 at 12:40 PM CET, Mikko Perttunen wrote:
From: Mikko Perttunen
On Tegra186, other software components may rely on the kernel to
keep Host1x operational even during suspend. As such, as a quirk,
skip asserting Host1x's reset on Tegra186
On Fri, Feb 16, 2024 at 8:14 AM Maxime Ripard wrote:
>
> On Fri, Feb 16, 2024 at 09:13:14AM +, Biju Das wrote:
> > Hi Maxime Ripard,
> >
> > > -Original Message-
> > > From: Maxime Ripard
> > > Sent: Friday, February 16, 2024 9:05 AM
> > > Subject: Re: RE: [PATCH v2] drm/imagination:
MMU and VM management is related and placed in the same source file.
Page table updates are delegated to the io-pgtable-arm driver that's in
the iommu subsystem.
The VM management logic is based on drm_gpuva_mgr, and is assuming the
VA space is mostly managed by the usermode driver, except for a
This is the piece of software interacting with the FW scheduler, and
taking care of some scheduling aspects when the FW comes short of slots
scheduling slots. Indeed, the FW only expose a few slots, and the kernel
has to give all submission contexts, a chance to execute their jobs.
The kernel-side
Tiler heap growing requires some kernel driver involvement: when the
tiler runs out of heap memory, it will raise an exception which is
either directly handled by the firmware if some free heap chunks are
available in the heap context, or passed back to the kernel otherwise.
The heap helpers will b
From: Liviu Dudau
Arm has introduced a new v10 GPU architecture that replaces the Job Manager
interface with a new Command Stream Frontend. It adds firmware driven
command stream queues that can be used by kernel and user space to submit
jobs to the GPU.
Add the initial schema for the device tre
Handles everything that's not related to the FW, the MMU or the
scheduler. This is the block dealing with the GPU property retrieval,
the GPU block power on/off logic, and some global operations, like
global cache flushing.
v5:
- Fix GPU_MODEL() kernel doc
- Fix test in panthor_gpu_block_power_off
Every thing related to devfreq in placed in panthor_devfreq.c, and
helpers that can be called by other logical blocks are exposed through
panthor_devfreq.h.
This implementation is loosely based on the panfrost implementation,
the only difference being that we don't count device users, because
the
Now that all blocks are available, we can add/update Kconfig/Makefile
files to allow compilation.
v4:
- Add Steve's R-b
v3:
- Add a dep on DRM_GPUVM
- Fix dependencies in Kconfig
- Expand help text to (hopefully) describe which GPUs are to be
supported by this driver and which are for panfrost.
Add an entry for the Panthor driver to the MAINTAINERS file.
v4:
- Add Steve's R-b
v3:
- Add bindings document as an 'F:' line.
- Add Steven and Liviu as co-maintainers.
Signed-off-by: Boris Brezillon
Reviewed-by: Steven Price
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
Contains everything that's FW related, that includes the code dealing
with the microcontroller unit (MCU) that's running the FW, and anything
related to allocating memory shared between the FW and the CPU.
A few global FW events are processed in the IRQ handler, the rest is
forwarded to the schedu
This is the last piece missing to expose the driver to the outside
world.
This is basically a wrapper between the ioctls and the other logical
blocks.
v5:
- Account for the drm_exec_init() prototype change
- Include platform_device.h
v4:
- Add an ioctl to let the UMD query the VM state
- Fix ker
Those are the registers directly accessible through the MMIO range.
FW registers are exposed in panthor_fw.h.
v4:
- Add the CORE_FEATURES register (needed for GPU variants)
- Add Steve's R-b
v3:
- Add macros to extract GPU ID info
- Formatting changes
- Remove AS_TRANSCFG_ADRMODE_LEGACY - it doe
The panthor driver is designed in a modular way, where each logical
block is dealing with a specific HW-block or software feature. In order
for those blocks to communicate with each other, we need a central
panthor_device collecting all the blocks, and exposing some common
features, like interrupt
Anything relating to GEM object management is placed here. Nothing
particularly interesting here, given the implementation is based on
drm_gem_shmem_object, which is doing most of the work.
v5:
- Add Liviu's and Steve's R-b
v4:
- Force kernel BOs to be GPU mapped
- Make panthor_kernel_bo_destroy(
Hello,
This is the 5th version of the kernel driver for Mali CSF-based GPUs,
and, unless someone has good reasons to block the merging of this
driver, I expect it to be the last one (the gallium driver is now
in a decent state, and is mostly waiting for the kernel driver to
be accepted).
A branch
Panthor follows the lead of other recently submitted drivers with
ioctls allowing us to support modern Vulkan features, like sparse memory
binding:
- Pretty standard GEM management ioctls (BO_CREATE and BO_MMAP_OFFSET),
with the 'exclusive-VM' bit to speed-up BO reservation on job submission
- V
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
to zero decimal places.
Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn).
Add this as machine = "qcom,sm7150", because speed-bin values a
This patch adds support for SM7150 SoC machine.
Reason for RESEND:
The discussion was resolved. As far as I understand, everything remains
unchanged. Let's make a RESEND for the patch so it doesn't get lost.
- Link to v2:
https://lore.kernel.org/all/20230926174243.161422-1-dan...@jiaxyga.com/
Cha
Hi Thomas,
kernel test robot noticed the following build errors:
[auto build test ERROR on staging/staging-testing]
[also build test ERROR on staging/staging-next staging/staging-linus
drm-misc/drm-misc-next linus/master v6.8-rc4 next-20240216]
[If your patch is applied to the wrong git tree, ki
Rename meson_encoder_{cvbs,dsi,hdmi}_init() to
meson_encoder_{cvbs,dsi,hdmi}_probe() so it's clear that these functions
are used at probe time during driver initialization. Also switch all
error prints inside those functions to use dev_err_probe() for
consistency.
This makes the code more straight
If 'list_limit' is set to a very high value, 'lsize' computation could
overflow if 'head.count' is big enough.
In such a case, udmabuf_create() would access to memory beyond 'list'.
Use memdup_array_user() which checks for overflow.
While at it, include .
Fixes: fbb0de795078 ("Add udmabuf misc
Create entry for Renesas RZ DRM drivers and add my self as a maintainer.
Signed-off-by: Biju Das
Reviewed-by: Laurent Pinchart
---
v16->v17:
* No change
v15->v16:
* No change
v14->v15:
* Added drm-misc tree entry.
* Sorted the entry(Placed before SHMOBILE)
v13->v14:
* Now SHMOBILE has maint
The rcar-du has never been maintained in drm-misc. So exclude only
this driver from drm-misc. Also, add the tree entry for sh_mobile.
Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Acked-by: Geert Uytterhoeven # shmob_drm
---
v16->v17:
* No change.
v15->v16:
* Added Rb and Ack tag fr
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support the blending of two picture layers and
raster operations (ROPs).
The DU mo
Document DU found in RZ/V2L SoC. The DU block is identical to RZ/G2L
SoC and therefore use RZ/G2L fallback to avoid any driver changes.
Signed-off-by: Biju Das
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
---
v16->v17:
* No change.
v15->v16:
* No cha
The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timi
This path series aims to add support for RZ/G2L DU DRM driver.
RZ/G2L LCD controller composed of Frame compression Processor(FCPVD), Video
signal processor (VSPD) and Display unit(DU). The output of LCDC is
connected to Display parallel interface and MIPI link video interface.
The output from DS
Hi,
On Thu, Nov 30, 2023 at 06:14:16PM +0100, Marco Pagani wrote:
> This patch introduces an initial KUnit test suite for GEM objects
> backed by shmem buffers.
>
> Suggested-by: Javier Martinez Canillas
> Signed-off-by: Marco Pagani
When running this in qemu, I get lots of warnings backtraces
Hi Andy,
On Sun, Feb 18, 2024 at 07:14:56PM +0800, Andy Yan wrote:
> Hi,
>
> On 2/18/24 02:39, Ondřej Jirman wrote:
> > From: Ondrej Jirman
> >
> > On RK3399 one MIPI DSI device can be alternatively used with the ISP1,
> > to provide RX DPHY. When this is the case (ISP1 is enabled in device
> >
Historically the Adreno driver has not been updating memory
configuration registers on a618 (SC7180 platform) implying that the
default configuration is fine. After the rework performed in the commit
8814455a0e54 ("drm/msm: Refactor UBWC config setting") the function
a6xx_calc_ubwc_config() still c
On Sat, 17 Feb 2024 at 13:39, Abel Vesa wrote:
>
> On 24-02-16 12:32:02, Rob Herring wrote:
> >
> > On Fri, 16 Feb 2024 19:01:06 +0200, Abel Vesa wrote:
> > > Document the MDSS hardware found on the Qualcomm X1E80100 platform.
> > >
> > > Reviewed-by: Krzysztof Kozlowski
> > > Signed-off-by: Abel
Hi,
On 2/18/24 02:39, Ondřej Jirman wrote:
From: Ondrej Jirman
On RK3399 one MIPI DSI device can be alternatively used with the ISP1,
to provide RX DPHY. When this is the case (ISP1 is enabled in device
tree), probe success of DRM is tied to probe success of ISP1 connected
camera sensor. This
Clean unnecessary braces in dc/dcn32/dcn32_resource_helpers.c and
dc/dcn32/dcn201_link_encoder.c
Signed-off-by: Túlio Fernandes
---
.../display/dc/dcn32/dcn32_resource_helpers.c| 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/d
Hi Maxime,
On 2024-02-08 at 13:16:27 +0100, Maxime Ripard wrote:
> [[PGP Signed Part:Undecided]]
> On Mon, Feb 05, 2024 at 04:22:26PM +0100, Frank Oltmanns wrote:
>> According to the Allwinner User Manual, the Allwinner A64 requires
>> PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu
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