tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 0f067394dd3b2af3263339cf7183bdb6ee0ac1f8 Add linux-next specific
files for 20240109
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202401101414.8gvbgmxw-...@intel.com
Error
On 1/10/24 16:19, Krzysztof Kozlowski wrote:
> On 10/01/2024 03:06, Damien Le Moal wrote:
>> On 1/9/24 17:23, Yoshinori Sato wrote:
>>> Added new ata-generic target.
>>> - iodata,usl-5p-ata
>>> - renesas,rts7751r2d-ata
>>>
>>> Each boards have simple IDE Interface. Use ATA generic driver.
>>
>> Thi
On 10/01/2024 03:06, Damien Le Moal wrote:
> On 1/9/24 17:23, Yoshinori Sato wrote:
>> Added new ata-generic target.
>> - iodata,usl-5p-ata
>> - renesas,rts7751r2d-ata
>>
>> Each boards have simple IDE Interface. Use ATA generic driver.
>
> This looks OK to me, so feel free to add:
>
> Acked-by:
Hi Philipp,
kernel test robot noticed the following build errors:
[auto build test ERROR on v6.7]
[also build test ERROR on linus/master]
[cannot apply to drm-misc/drm-misc-next next-20240109]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
In drm_kms_helper_poll_disable() check if output polling
support is initialized before disabling polling.
For drivers like hyperv-drm, that do not initialize connector
polling, if suspend is called without this check, it leads to
suspend failure with following stack
[ 770.719392] Freezing remainin
I think this is fine, but I was wondering if it would be simpler and
easier to just remove the sched cleanup from v3d_job_init and instead
always rely on callers to eventually call v3d_job_cleanup for fail
paths, where we are already calling v3d_job_cleanup.
Iago
El mar, 09-01-2024 a las 11:28 -0
Hi Philipp,
kernel test robot noticed the following build errors:
[auto build test ERROR on v6.7]
[also build test ERROR on linus/master next-20240109]
[cannot apply to drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
My plan is to obtain the process priority and convert it into the drm-scheduler's priority, so that the user is unaware and does not need to use environment variables to set it.
This is my patch:--- a/amdgpu/amdgpu_cs.c+++ b/amdgpu/amdgpu_cs.c@@ -31,6 +31,7 @@#if HAVE_ALLOCA_H# include #endif+#inc
On 1/9/24 17:23, Yoshinori Sato wrote:
> Added new ata-generic target.
> - iodata,usl-5p-ata
> - renesas,rts7751r2d-ata
>
> Each boards have simple IDE Interface. Use ATA generic driver.
This looks OK to me, so feel free to add:
Acked-by: Damien Le Moal
Note: The "DO NOT MERGE" patch prefix al
tree: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
head: 632ca3c92f3840d91ba7ddda0271f84813036a11
commit: d3e040f450ec8e46ff42fa495a433b976ab47686 [6/21] drm/rockchip:
inno_hdmi: Get rid of mode_set
config: s390-randconfig-001-20240109
(https://download.01.org/0day-ci/archive
From: Dave Airlie
It appears on TU106 GPUs (2070), that some of the nvdec engines
are in the runlist but have no valid nonstall interrupt, nouveau
didn't handle that too well.
This should let nouveau/gsp work on those.
Cc: sta...@vger.kernel.org # v6.7+
---
drivers/gpu/drm/nouveau/nvkm/engine/
Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
HDMI PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
Tested-by: Alexander Stein
---
v11->v12:
- Adjust clk disable order.
- Return er
Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
DisplayPort PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
---
v11->v12:
- Return error code to replace -1 for function wait_fo
Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
SOC's ROM code. Bootload binary incl
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu
Reviewed-by: Rob Herring
---
v9->v12:
*No change.
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/fsl
Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.
Signed-off-by: Sandor Yu
Reviewed-by: Krzysztof Kozlowski
---
v9->v12:
*No change.
.../display/bridge/cdns,mhdp8501.yaml | 104 ++
1 file changed, 104 insertions(+)
create mode 100644
Documentation/devicetree
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
Reviewed-by: D
MHDP8546 mailbox access functions will be share to other mhdp driver
and Cadence HDP-TX HDMI/DP PHY drivers.
Create a new mhdp helper driver and move all those functions into.
cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(),
because it use the DPTX command ID DPTX_WRITE_REGISTER.
New
The patch set initial support Cadence MHDP8501(HDMI/DP) DRM bridge
driver and Cadence HDP-TX PHY(HDMI/DP) drivers for Freescale i.MX8MQ.
The patch set compose of DRM bridge drivers and PHY drivers.
Both of them need patch #1 and #2 to pass build.
DRM bridges driver patches:
#1: drm: bridge: Ca
Hi Philipp,
kernel test robot noticed the following build errors:
[auto build test ERROR on v6.7]
[also build test ERROR on linus/master next-20240109]
[cannot apply to drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
On Tue, Jan 9, 2024 at 11:06 AM Xaver Hugl wrote:
>
> Hi,
>
> KWin does use DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT.
Can you point me to the code that implements it? Just wanted to take a
quick look, because I didn't see the cursor on KDE 6 after fixing the
kernel oops.
> Tying the check to
> DRM_CL
Fix a build error when using GCC 13.2.0 from kernel.org crosstools
by changing ARRAY_SIZE() to the macro PVR_MIPS_PT_PAGE_COUNT:
drivers/gpu/drm/imagination/pvr_vm_mips.c: In function 'pvr_vm_mips_fini':
../include/linux/array_size.h:11:25: warning: overflow in conversion from 'long
unsigned int'
On Mon, Jan 8, 2024 at 4:57 PM Ian Forbes wrote:
>
> Without this definition device errors will display the command name
> as (null) when debug logging is enabled.
>
> Signed-off-by: Ian Forbes
> ---
> drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --g
Hi,
On Tue, Jan 9, 2024 at 1:35 PM Uwe Kleine-König
wrote:
>
> Apart from the two of_xlate implementations this member is write-only.
> In the of_xlate functions of_pwm_xlate_with_flags() and
> of_pwm_single_xlate() it's more sensible to check for args->args_count
> because this is what is actual
Hi Daniel,
Please excuse my misconfigured email client. HTML was accidentally
enabled in my previous messages, so I'll re-send it for the benefit of
mailing lists.
þri., 9. jan. 2024 kl. 22:32 skrifaði Daniel Stone :
>
> On Tue, 9 Jan 2024 at 18:12, Andri Yngvason wrote:
> > + * active color for
Hi Daniel,
þri., 9. jan. 2024 kl. 22:32 skrifaði Daniel Stone :
> On Tue, 9 Jan 2024 at 18:12, Andri Yngvason wrote:
> > + * active color format:
> > + * This read-only property tells userspace the color format
> actually used
> > + * by the hardware display engine "on the cable" on a co
Playing 4K media with 59.94 fractional rate (typically VP9) causes the screen
to lose
sync with the following error reported in the system log:
[ 89.610280] Fatal Error, invalid HDMI vclk freq 593406
Modetest shows the following:
3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407
Hi,
On Tue, 9 Jan 2024 at 18:12, Andri Yngvason wrote:
> + * active color format:
> + * This read-only property tells userspace the color format actually used
> + * by the hardware display engine "on the cable" on a connector. The
> chosen
> + * value depends on hardware capabilities
reviews.llvm.org was LLVM's Phabricator instances for code review. It
has been abandoned in favor of GitHub pull requests. While the majority
of links in the kernel sources still work because of the work Fangrui
has done turning the dynamic Phabricator instance into a static archive,
there are some
reviews.llvm.org was LLVM's Phabricator instances for code review. It
has been abandoned in favor of GitHub pull requests. While the majority
of links in the kernel sources still work because of the work Fangrui
has done turning the dynamic Phabricator instance into a static archive,
there are some
LLVM moved their issue tracker from their own Bugzilla instance to
GitHub issues. While all of the links are still valid, they may not
necessarily show the most up to date information around the issues, as
all updates will occur on GitHub, not Bugzilla.
Another complication is that the Bugzilla is
/selftests/bpf/prog_tests/xdpwall.c | 2 +-
.../selftests/bpf/progs/test_core_reloc_type_id.c | 2 +-
23 files changed, 40 insertions(+), 40 deletions(-)
---
base-commit: 0dd3ee31125508cd67f7e7172247f05b7fd1753a
change-id: 20240109-update-llvm-links-d03f9d649e1e
Best regards,
--
Nathan Chancellor
From: Werner Sembach
This commit implements the "active color format" drm property for the Intel
GPU driver.
Signed-off-by: Werner Sembach
Signed-off-by: Andri Yngvason
Tested-by: Andri Yngvason
---
drivers/gpu/drm/i915/display/intel_display.c | 33
drivers/gpu/drm/i915/
This is a subset of patches, originally submitted by Werner Sembach
titled: New uAPI drm properties for color management [1]
I've rebased against the current master branch, made modifications where
needed, and tested with both HDMI and DP on both Intel and AMD hardware,
using modified sway [2] and
From: Werner Sembach
This commit implements the "preferred color format" drm property for the
AMD GPU driver.
Signed-off-by: Werner Sembach
Signed-off-by: Andri Yngvason
Tested-by: Andri Yngvason
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 +++
.../display/amdgpu_d
From: Werner Sembach
This commit implements the "active color format" drm property for the AMD
GPU driver.
Signed-off-by: Werner Sembach
Signed-off-by: Andri Yngvason
Tested-by: Andri Yngvason
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++-
.../display/amdgpu_dm/a
From: Werner Sembach
Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check that was performed in the
drm_mode_is_420_only() case, but not in the drm_mode_is_420_also() &&
force_yuv420_output case.
Without further knowledge if YCbCr 4:2:0 is supported outside of HDMI,
there is no reason to use RGB whe
From: Werner Sembach
This commit implements the "preferred color format" drm property for the
Intel GPU driver.
Signed-off-by: Werner Sembach
Co-developed-by: Andri Yngvason
Signed-off-by: Andri Yngvason
Tested-by: Andri Yngvason
---
drivers/gpu/drm/i915/display/intel_dp.c | 16
From: Werner Sembach
Add a new general drm property "preferred color format" which can be used
by userspace to tell the graphic drivers to which color format to use.
Possible options are:
- auto (default/current behaviour)
- rgb
- ycbcr444
- ycbcr422 (not supported by both amdgpu
From: Werner Sembach
Add a new general drm property "active color format" which can be used by
graphic drivers to report the used color format back to userspace.
There was no way to check which color format got actually used on a given
monitor. To surely predict this, one must know the exact cap
Dear maintainers,
I have a Lenovo b40-30 that I have been running with nomodeset for a while.
The issue was that it needed invert_brightness. Here are the requested IDs:
0f31, 17aa, 3986 :).
N.B.: I am not subscribed, please Cc me when replying.
Best regards,
Cédric
Hello,
not a complete review, I just note that there is a duplicate space in
the Subject. You might want to fix for the next patch round.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König|
Industrial Linux Solutions | https://www.pengu
Apart from the two of_xlate implementations this member is write-only.
In the of_xlate functions of_pwm_xlate_with_flags() and
of_pwm_single_xlate() it's more sensible to check for args->args_count
because this is what is actually used in the device tree.
Signed-off-by: Uwe Kleine-König
---
driv
Hello,
the first patch is a fix for an out-of-bounds access and so should
probably go in quickly. The other changes are merge window material.
Best regards
Uwe
Uwe Kleine-König (5):
pwm: Fix out-of-bounds access in of_pwm_single_xlate()
pwm: Drop useless member .of_pwm_n_cells of struct pwm_
During the testing of Gnome on Qualcomm Robotics platform screen
corruption has been observed. Lowering GPU's highest_bank_bit from 14 to
13 seems to fix the screen corruption.
Note, the MDSS and DPU drivers use HBB=1 (which maps to the
highest_bank_bit = 14). So this change merely works around th
Dne nedelja, 31. december 2023 ob 10:10:40 CET je Frank Oltmanns napisal(a):
>
> On 2023-12-19 at 17:54:19 +0100, Jernej Škrabec
> wrote:
> > Dne ponedeljek, 18. december 2023 ob 14:35:22 CET je Frank Oltmanns
> > napisal(a):
> >> The Allwinner A64 manual lists the following constraint for the
On 09/01/2024 18:19, Andrew Davis wrote:
> The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
> multiple vendors. Describe how the SGX GPU is integrated in these SoC,
> including register space and interrupts. Clocks, reset, and power domain
> information is SoC specific.
>
> S
On 09/01/2024 18:19, Andrew Davis wrote:
> This binding will be used for GPUs starting from Series6 (Rogue)
> and later. A different binding document will describe Series5.
> With that the name "img,powervr" is too generic, rename to
> "img,powervr-rogue" to avoid confusion.
>
> Suggested-by: Maxi
On 09/01/2024 20:33, Andrew Davis wrote:
> On 1/9/24 1:17 PM, Krzysztof Kozlowski wrote:
>> On 09/01/2024 20:04, Andrew Davis wrote:
>>> On 1/9/24 12:59 PM, Krzysztof Kozlowski wrote:
On 09/01/2024 18:19, Andrew Davis wrote:
> This binding will be used for GPUs starting from Series6 (Rogue
On 1/9/24 1:17 PM, Krzysztof Kozlowski wrote:
On 09/01/2024 20:04, Andrew Davis wrote:
On 1/9/24 12:59 PM, Krzysztof Kozlowski wrote:
On 09/01/2024 18:19, Andrew Davis wrote:
This binding will be used for GPUs starting from Series6 (Rogue)
and later. A different binding document will describe
On 1/8/2024 11:07 AM, Dmitry Baryshkov wrote:
On Mon, 8 Jan 2024 at 19:57, Carl Vanderlip wrote:
On 1/5/2024 4:38 PM, Dmitry Baryshkov wrote:
On Sat, 6 Jan 2024 at 02:04, Carl Vanderlip wrote:
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/
On 09/01/2024 20:04, Andrew Davis wrote:
> On 1/9/24 12:59 PM, Krzysztof Kozlowski wrote:
>> On 09/01/2024 18:19, Andrew Davis wrote:
>>> This binding will be used for GPUs starting from Series6 (Rogue)
>>> and later. A different binding document will describe Series5.
>>> With that the name "img,p
On 1/9/24 12:59 PM, Krzysztof Kozlowski wrote:
On 09/01/2024 18:19, Andrew Davis wrote:
This binding will be used for GPUs starting from Series6 (Rogue)
and later. A different binding document will describe Series5.
With that the name "img,powervr" is too generic, rename to
"img,powervr-rogue" t
On 09/01/2024 18:19, Andrew Davis wrote:
> This binding will be used for GPUs starting from Series6 (Rogue)
> and later. A different binding document will describe Series5.
> With that the name "img,powervr" is too generic, rename to
> "img,powervr-rogue" to avoid confusion.
>
> Suggested-by: Maxi
On 09/01/2024 17:53, Andrew Davis wrote:
> On 1/9/24 5:32 AM, Krzysztof Kozlowski wrote:
>> On 08/01/2024 19:32, Andrew Davis wrote:
>>> The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
>>> multiple vendors. Describe how the SGX GPU is integrated in these SoC,
>>> including re
On 09/01/2024 17:14, Andrew Davis wrote:
> On 1/9/24 5:28 AM, Krzysztof Kozlowski wrote:
>> On 08/01/2024 19:32, Andrew Davis wrote:
>>> Signed-off-by: Andrew Davis
>>> ---
>>> .../bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} | 4 ++--
>>> MAINTAINERS
On 09/01/2024 09:23, Yoshinori Sato wrote:
> Renesas SH7751 Interrupt controller priority register define.
>
Still not a binding.
Some parts of my comments are implemented, others are just ignored
(dropping the file, fixing full stop in commit msg). This is confusing.
I don't know. Shall I just
On 1/8/2024 11:09 PM, Shengyang Chen wrote:
The waveshare 7" 800x480 panel is a clone of Raspberry Pi 7" 800x480 panel
It also uses a Toshiba TC358762 DSI to DPI bridge chip but it needs different
timing from Raspberry Pi panel. Add new timing for it.
Hi Shengyang,
The patch itself LGTM, bu
From: Rob Clark
This reverts commit abe2023b4cea192ab266b351fd38dc9dbd846df0.
Changing the locking order means that scheduler/msm_job_run() can race
with the recovery kthread worker, with the result that the GPU gets an
extra runpm get when we are trying to power it off. Leaving the GPU in
an u
On Tue, Jan 09, 2024 at 06:07:19PM +, Conor Dooley wrote:
> On Tue, Jan 09, 2024 at 05:23:24PM +0900, Yoshinori Sato wrote:
> > Added new ata-generic target.
> > - iodata,usl-5p-ata
> > - renesas,rts7751r2d-ata
> >
> > Each boards have simple IDE Interface. Use ATA generic driver.
> >
> > Sig
On Tue, Jan 09, 2024 at 05:23:24PM +0900, Yoshinori Sato wrote:
> Added new ata-generic target.
> - iodata,usl-5p-ata
> - renesas,rts7751r2d-ata
>
> Each boards have simple IDE Interface. Use ATA generic driver.
>
> Signed-off-by: Yoshinori Sato
Acked-by: Conor Dooley
Cheers,
Conor.
> ---
>
On Tue, Jan 09, 2024 at 05:23:23PM +0900, Yoshinori Sato wrote:
> Add Silicon Mortion Technology Corporation
> https://www.siliconmotion.com/
>
> Signed-off-by: Yoshinori Sato
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
On Tue, Jan 09, 2024 at 05:23:22PM +0900, Yoshinori Sato wrote:
> Add IO DATA DEVICE INC.
> https://www.iodata.com/
>
> Signed-off-by: Yoshinori Sato
I think you are missing an r-b tag here from Geert:
https://lore.kernel.org/all/camuhmduvnt1tdtoq4ppqn69cocaeveaxrsol2vq2efbq+hv...@mail.gmail.com
Yo,
On Tue, Jan 09, 2024 at 05:23:21PM +0900, Yoshinori Sato wrote:
> Renesas SH series and compatible ISA CPUs.
>
> Signed-off-by: Yoshinori Sato
> ---
> .../devicetree/bindings/sh/cpus.yaml | 74 +++
> 1 file changed, 74 insertions(+)
> create mode 100644 Documentati
On Tue, Jan 09, 2024 at 01:42:53PM +0100, Linus Walleij wrote:
> Hi Yoshinori,
>
> thanks for your patch!
>
> On Tue, Jan 9, 2024 at 9:24 AM Yoshinori Sato
> wrote:
>
> > Renesas SH7751 PCI Controller json-schema.
> >
> > Signed-off-by: Yoshinori Sato
> (...)
> > + renesas,bus-arbit-round-rob
On 1/9/24 09:07, Iago Toral wrote:
Thanks Maíra!
Reviewed-by: Iago Toral Quiroga
Applied to drm-misc/drm-misc-next-fixes!
Best Regards,
- Maíra
El mar, 09-01-2024 a las 08:30 -0300, Maíra Canal escribió:
RPi 4 uses V3D 4.2, which is currently not supported by the register
definition stat
On Tue, Jan 9, 2024 at 2:47 AM Christian König
wrote:
>
> From: Somalapuram Amaranath
>
> Instead of a list of separate busy placement add flags which indicate
> that a placement should only be used when there is room or if we need to
> evict.
>
> v2: add missing TTM_PL_FLAG_IDLE for i915
> v3: f
Hi
On Tue, 9 Jan 2024 at 11:19, wrote:
>
> Hi,
>
> On 09/01/2024 08:09, Shengyang Chen wrote:
> > This patchset adds waveshare 7inch touchscreen panel support
> > for the StarFive JH7110 SoC.
>
> Could you precise which SKU you're referring to ? is it 19885 =>
> https://www.waveshare.com/7inch-d
Hi Neil,
Am 09.01.24 um 12:19 schrieb neil.armstr...@linaro.org:
Hi,
On 09/01/2024 08:09, Shengyang Chen wrote:
This patchset adds waveshare 7inch touchscreen panel support
for the StarFive JH7110 SoC.
Could you precise which SKU you're referring to ? is it 19885 =>
https://www.waveshare.com
The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
multiple vendors. Describe how the SGX GPU is integrated in these SoC,
including register space and interrupts. Clocks, reset, and power domain
information is SoC specific.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Marti
Add SGX GPU device entry to base jz4780 dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/j
Add SGX GPU device entry to base AM654 dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-
for Series6+, but otherwise most
is the same as we have been using in our vendor tree for many years.
Thanks,
Andrew
Based on next-20240109.
[0]: https://lkml.org/lkml/2020/4/24/1222
[1]: https://github.com/openpvrsgx-devgroup
Changes for v1:
- Added commit message to patch #1
- Reworked Rogue
This binding will be used for GPUs starting from Series6 (Rogue)
and later. A different binding document will describe Series5.
With that the name "img,powervr" is too generic, rename to
"img,powervr-rogue" to avoid confusion.
Suggested-by: Maxime Ripard
Signed-off-by: Andrew Davis
Reviewed-by:
Add SGX GPU device entry to base OMAP5 dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/ti/omap/omap5.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/omap5.dtsi
b/arch/arm/boot/dts/ti/
Add SGX GPU device entry to base DRA7x dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/ti/omap/dra7.dtsi | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi
b/arch/arm/boot/dts/ti/oma
Add SGX GPU device entry to base OMAP4 dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/ti/omap/omap4.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/omap4.dtsi
b/arch/arm/boot/dts/ti/
Add SGX GPU device entry to base sun6i-a31 dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/allwinner/sun6i-a31.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi
b/arch/arm/boot/dts/all
Add SGX GPU device entries to base OMAP3 dtsi files.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/ti/omap/am3517.dtsi | 11 ++-
arch/arm/boot/dts/ti/omap/omap34xx.dtsi | 11 ++-
arch/arm/boot/dts/ti/omap/omap36xx.dtsi | 9 +
Add SGX GPU device entry to base AM33xx dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/ti/omap/am33xx.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi
b/arch/arm/boot/dts/
Add SGX GPU device entry to base AM437x dtsi file.
Signed-off-by: Andrew Davis
Reviewed-by: Javier Martinez Canillas
---
arch/arm/boot/dts/ti/omap/am4372.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi
b/arch/arm/boot/dts/ti/omap/am4372.dtsi
On Tue, Jan 09, 2024 at 05:23:16PM +0900, Yoshinori Sato wrote:
> Renesas SH7751 external interrupt encoder json-schema.
>
> Signed-off-by: Yoshinori Sato
> ---
> .../renesas,sh7751-irl-ext.yaml | 72 +++
> 1 file changed, 72 insertions(+)
> create mode 100644
> D
On Thu, 21 Dec 2023 17:30:57 +0800, xiazhengqiao wrote:
> To have better compatibility for DP sink, there is a retry mechanism
> for the link training process to switch between different training process.
> The original driver code doesn't reset the retry counter when training
> state is pass. If t
On 1/9/2024 7:31 AM, Rob Clark wrote:
On Mon, Jan 8, 2024 at 6:13 PM Rob Clark wrote:
On Mon, Jan 8, 2024 at 2:58 PM Abhinav Kumar wrote:
On 1/8/2024 11:50 AM, Rob Clark wrote:
From: Rob Clark
The msm tests should skip on non-msm hw, so I think it should be safe to
enable everywhere
On 1/9/24 10:59, Jani Nikula wrote:
On Mon, 08 Jan 2024, Danilo Krummrich wrote:
On 1/4/24 21:16, Jani Nikula wrote:
Including drm_edid.h from nouveau_connector.h causes the rebuild of 15
files when drm_edid.h is modified, while there are only a few files that
actually need to include drm_edid
On 1/9/24 5:32 AM, Krzysztof Kozlowski wrote:
On 08/01/2024 19:32, Andrew Davis wrote:
The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
multiple vendors. Describe how the SGX GPU is integrated in these SoC,
including register space and interrupts. Clocks, reset, and power d
Hi,
On Tue, Jan 9, 2024 at 4:05 AM Pin-yen Lin wrote:
>
> The ps8640 bridge seems to expect everything to be power cycled at the
> disable process, but sometimes ps8640_aux_transfer() holds the runtime
> PM reference and prevents the bridge from suspend.
>
> Prevent that by introducing a mutex lo
On 08.01.2024 22:24, Lucas De Marchi wrote:
> On Mon, Jan 08, 2024 at 09:46:47PM +0100, Michal Wajdeczko wrote:
>>
>>
>> On 08.01.2024 15:07, Lucas De Marchi wrote:
>>> On Mon, Jan 08, 2024 at 12:05:57PM +0300, Dan Carpenter wrote:
The GUC_HXG_MSG_0_ORIGIN definition should be unsigned. Cu
On Tue, Jan 09, 2024 at 03:09:48PM +0800, Shengyang Chen wrote:
> The waveshare 7" 800x480 panel is a clone of Raspberry Pi 7" 800x480 panel
> It can be drived by Raspberry Pi panel's process but it needs different
> timing from Raspberry Pi panel. Add compatible property for it.
>
> Signed-off-by
On Tue, 09 Jan 2024 17:23:16 +0900, Yoshinori Sato wrote:
> Renesas SH7751 external interrupt encoder json-schema.
>
> Signed-off-by: Yoshinori Sato
> ---
> .../renesas,sh7751-irl-ext.yaml | 72 +++
> 1 file changed, 72 insertions(+)
> create mode 100644
> Docum
On 1/9/24 5:28 AM, Krzysztof Kozlowski wrote:
On 08/01/2024 19:32, Andrew Davis wrote:
Signed-off-by: Andrew Davis
---
.../bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} | 4 ++--
MAINTAINERS | 2 +-
2 files changed, 3 insertions(
Hi,
KWin does use DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT. Tying the check to
DRM_CLIENT_CAP_ATOMIC instead would IMO make more sense though (even if it's
still weird) and would work with older versions of KWin and other compositors.
Greetings,
Xaver Hugl
On Tue, 9 Jan 2024 at 16:29, Randy Dunlap wrote:
>
>
>
> On 1/9/24 07:25, Daniel Vetter wrote:
> > On Tue, 9 Jan 2024 at 16:23, Randy Dunlap wrote:
> >>
> >>
> >>
> >> On 1/9/24 05:42, Daniel Vetter wrote:
> >>> On Tue, 9 Jan 2024 at 13:59, Daniel Vetter wrote:
>
> On Mon, Jan 08, 2024
On Mon, Jan 8, 2024 at 6:13 PM Rob Clark wrote:
>
> On Mon, Jan 8, 2024 at 2:58 PM Abhinav Kumar
> wrote:
> >
> >
> >
> > On 1/8/2024 11:50 AM, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > The msm tests should skip on non-msm hw, so I think it should be safe to
> > > enable everywhere.
>
On 1/9/24 07:25, Daniel Vetter wrote:
> On Tue, 9 Jan 2024 at 16:23, Randy Dunlap wrote:
>>
>>
>>
>> On 1/9/24 05:42, Daniel Vetter wrote:
>>> On Tue, 9 Jan 2024 at 13:59, Daniel Vetter wrote:
On Mon, Jan 08, 2024 at 01:10:12PM -0800, Randy Dunlap wrote:
> Hi Thomas,
>
>
On Tue, Jan 09, 2024 at 04:00:15PM +0100, Thomas Hellström wrote:
Select the https URL by default for xe since users may not have
registered a gitlab ssh key yet, and may get confused by
the corresponding error message.
Suggested-by: Daniel Vetter
Cc: intel...@lists.freedesktop.org
Cc: Lucas De
On Tue, 9 Jan 2024 at 16:23, Randy Dunlap wrote:
>
>
>
> On 1/9/24 05:42, Daniel Vetter wrote:
> > On Tue, 9 Jan 2024 at 13:59, Daniel Vetter wrote:
> >>
> >> On Mon, Jan 08, 2024 at 01:10:12PM -0800, Randy Dunlap wrote:
> >>> Hi Thomas,
> >>>
> >>> On 1/8/24 00:57, Thomas Zimmermann wrote:
> >>>
On 1/9/24 05:42, Daniel Vetter wrote:
> On Tue, 9 Jan 2024 at 13:59, Daniel Vetter wrote:
>>
>> On Mon, Jan 08, 2024 at 01:10:12PM -0800, Randy Dunlap wrote:
>>> Hi Thomas,
>>>
>>> On 1/8/24 00:57, Thomas Zimmermann wrote:
Hi,
thanks for the fix.
Am 06.01.24 um 04:29 sc
Daniel Vetter writes:
> On Tue, Jan 09, 2024 at 02:48:42PM +0100, Javier Martinez Canillas wrote:
>> Daniel Vetter writes:
>>
>> Hello Sima,
>>
>> Thanks for your feedback.
>>
>> > On Tue, Jan 09, 2024 at 01:05:59PM +0100, Javier Martinez Canillas wrote:
>> >> The device is initialized in the
On 09/01/2024 14:57, Christian König wrote:
Am 09.01.24 um 15:26 schrieb Daniel Vetter:
On Tue, 9 Jan 2024 at 14:25, Tvrtko Ursulin
wrote:
On 09/01/2024 12:54, Daniel Vetter wrote:
On Tue, Jan 09, 2024 at 09:30:15AM +, Tvrtko Ursulin wrote:
On 09/01/2024 07:56, Christian König wrote:
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