On 2023-12-20 at 16:12:42 +0100, Jernej Škrabec
wrote:
> Dne sreda, 20. december 2023 ob 08:09:28 CET je Frank Oltmanns napisal(a):
>>
>> On 2023-12-19 at 17:54:19 +0100, Jernej Škrabec
>> wrote:
>> > Dne ponedeljek, 18. december 2023 ob 14:35:22 CET je Frank Oltmanns
>> > napisal(a):
>> >>
On 11/22/23 14:13, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc prints a warning about a possible array overflow for a couple of
> callers of dp_decide_lane_settings() after commit 1b56c90018f0 ("Makefile:
> Enable -Wstringop-overflow globally"):
>
> drivers/gpu/drm/amd/amdgpu/../displa
Hi Linus,
Pretty quiet for this week, just i915 and amdgpu fixes, I think the
misc tree got lost this week, but didn't seem to have too much in it,
so it can wait. I've also got a bunch of nouveau GSP fixes sailing
around that'll probably land next time as well.
Dave.
drm-fixes-2023-12-22:
drm f
Fixes a memory leak seen with kmemleak.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
index e2810
It looks like for some messages the upper layers need to get access to the
results of the message so we can interpret it.
Rework the ctrl push interface to not free things and cleanup properly
whereever it errors out.
Requested-by: Lyude
Signed-off-by: Dave Airlie
---
.../gpu/drm/nouveau/includ
From: Lyude Paul
Turns out that one of the ways that Nvidia's driver handles the pre-LT
timeout for eDP panels is by providing a retry timeout in their link
training callbacks that we're expected to wait for. Up until now we didn't
pay any attention to this parameter.
So, start honoring the time
This should let the upper layers retry as needed on EAGAIN.
There may be other values we will care about in the future, but
this covers our present needs.
Signed-off-by: Dave Airlie
---
.../gpu/drm/nouveau/nvkm/subdev/gsp/r535.c| 26 +++
1 file changed, 21 insertions(+), 5 d
From: Lyude Paul
Currently we get an error from ACPI because both of these arguments expect
a single argument, and we don't provide one. I'm not totally clear on what
that argument does, but we're able to find the missing value from
_acpiCacheMethodData() in src/kernel/platform/acpi_common.c in n
There is a deadlock between the irq and fctx locks,
the irq handling takes irq then fctx lock
the fence signalling takes fctx then irq lock
This splits the fence signalling path so the code that hits
the irq lock is done in a separate work queue.
This seems to fix crashes/hangs when using nouveau
This was being leaked.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
index d088e636edc3..b903785056b5 100644
---
This fixes a memory leak for the acpi dod object.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
index 365dda6c002a.
This func ptr here is normally static allocation, but gsp r535
uses a dynamic pointer, so we need to handle that better.
This fixes a crash with GSP when you use config=disp=0 to avoid
disp problems.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c | 6 --
1 fi
These were leftover debug, if we need to bring them back do so
for debugging later.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c | 7 ---
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 9 -
2 files changed, 16 deletions(-)
diff --git a/drivers/gp
Add NULL callbacks for some things GSP calls that we don't handle, but know
about
so we avoid the logging.
v2: Timur suggested allowing null fn.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --gi
This is a collection of nouveau debug prints, memory leak, a very
annoying race condition causing system hangs with prime scenarios,
and a fix from Lyude to get the panel on my laptop working.
I'd like to get these into 6.7,
Dave.
build-kdl.sh was doing a `clone --depth 1` of the default branch,
then checking out a commit that might not be the latest of that
branch, resulting in container build error.
https://gitlab.freedesktop.org/mesa/mesa/-/commit/5efa4d56 fixes
kdl commit fetch issue. Uprev mesa in drm-ci to fix this.
On Thu, Dec 21, 2023 at 02:28:04PM -0800, Lucas De Marchi wrote:
> Add a dependency on CONFIG_64BIT since currently the xe driver doesn't
> build on 32bits. It may be enabled again after all the issues are fixed.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu
Title typo: SC8108X -> SC8180X :)
On 2023-12-03 03:32:01, Dmitry Baryshkov wrote:
> Enable WB2 hardware block, enabling writeback support on this platform.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++
> 1 file changed, 18 in
On Thu, Dec 21, 2023 at 10:28:52AM +0100, Krzysztof Kozlowski wrote:
> On 20/12/2023 11:08, Moudy Ho wrote:
> > To simplify maintenance and avoid branches, the identical component
> > should be merged and placed in the path belonging to the MDP
> > (from display/* to media/*).
>
> Combining bindin
readq() is not available in 32bits. iosys-map already has the logic in
place to use read u64 in all cases, so simply add a helper variable for
using that.
Fixes: 44e694958b95 ("drm/xe/display: Implement display support")
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/xe/compat-i915-headers/gem/i
Cast the pointer to unsigned long and let it be implicitly extended to
u64. This fixes the build on 32bits arch.
Cc: Matthew Brost
Cc: Niranjana Vishwanathapura
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/xe/xe_trace.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Now that all the issues with 32bits are fixed, enable it again.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/xe/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index a53b0fdc15a7..5b3da06e7ba3 100644
--- a/
A few fixes when building xe with ARCH=i386. If getting the whole lot,
we can simply skip the first and last patches. However they probably
need to got through CI and be reviewed to avoid regressions. For the
current pull request, simply disabling 32bits build is an alternative,
so we'd apply patch
Add a dependency on CONFIG_64BIT since currently the xe driver doesn't
build on 32bits. It may be enabled again after all the issues are fixed.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/xe/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/Kco
resource_size_t uses %pa format in printk since the size varies
depending on build options. However to keep the io_size/physical_size
addition in the same call we can't pass the address without adding yet
another variable in these function. Simply cast it to u64 and keep using
%llx.
Fixes: 286089c
Use DIV_ROUND_UP_ULL() so it also works on 32bit build.
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/xe/xe_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b
On Tue, 19 Dec 2023 21:34:08 +0100, Javier Martinez Canillas wrote:
> Add a Device Tree binding schema for the OLED panels based on the
> Solomon SSD133x family of controllers.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> Changes in v3:
> - Move solomon,ssd-common.yaml ref before the
On Tue, 19 Dec 2023 21:34:07 +0100, Javier Martinez Canillas wrote:
> Commit 2d23e7d6bacb ("dt-bindings: display: Add SSD132x OLED controllers")
> used the wrong properties for width and height, instead of the correct
> "solomon,width" and "solomon,height" properties.
>
> Fix this by adding the
On Tue, 19 Dec 2023 21:34:06 +0100, Javier Martinez Canillas wrote:
> The commit 591825fba8a2 ("dt-bindings: display: ssd1307fb: Remove default
> width and height values") used the wrong properties for width and height,
> instead of the correct "solomon,width" and "solomon,height" properties.
>
Unlike what is claimed in commit f5aa7d46b0ee ("drm/bridge:
parade-ps8640: Provide wait_hpd_asserted() in struct drm_dp_aux"), if
someone manually tries to do an AUX transfer (like via `i2cdump ${bus}
0x50 i`) while the panel is off we don't just get a simple transfer
error. Instead, the whole ps86
Hi Dave and Sima,
Here goes a v4 of our first pull request.
This fix the sign-off and 'Fixes:' tag issues of the top commit
that was added during v3. Sorry about that, but I'm sure that
after we become a drm-tip branch using dim to manage it, things
like this won't happen again.
v3: https://lore
On Thu, 21 Dec 2023 13:43:32 +0100, Raphael Gallais-Pou wrote:
> List EDT ETML0700Z9NDHA in the LVDS panel enumeration.
>
> Signed-off-by: Raphael Gallais-Pou
> ---
> Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Her
On Thu, 21 Dec 2023 12:25:06 +0200, Dmitry Baryshkov wrote:
> Rename the Qualcomm MSM Display schemas to follow the main compatible
> string instead of just using the block type. This follows the
> established practice for YAML file names.
>
> Cc: Aiqun Yu (Maria)
> Signed-off-by: Dmitry Barysh
On Thu, 21 Dec 2023 12:25:05 +0200, Dmitry Baryshkov wrote:
> While the DSI PHY schema files describe the display-related hardware,
> they still describe a PHY. Move all DSI PHY schema files to the phy/
> subdir.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../msm/dsi-phy-10nm.yaml => phy/qcom
On 21/12/2023 13:43, Raphael Gallais-Pou wrote:
> Add dt-binding file for "st,stm32-lvds" compatible.
>
> Signed-off-by: Raphael Gallais-Pou
> ---
I don't know why this was resend, nothing explains it, but I already
commented on other version.
Please respond to comments there.
In the future, u
Hi Dave and Sima,
Here goes a v3 of our first pull request.
It is basically the same, but with 2 fixed Author 'Signed-off-by:' tags
plus a fix for the clang build that would fail with our W=1.
v2: https://lore.kernel.org/all/zyizv1pk6oljq...@intel.com/
v1: https://lore.kernel.org/all/zxzta75g5vh
Hi Jonathan,
Le jeudi 21 décembre 2023 à 16:30 +, Jonathan Cameron a écrit :
> On Tue, 19 Dec 2023 18:50:01 +0100
> Paul Cercueil wrote:
>
> > [V4 was: "iio: Add buffer write() support"][1]
> >
> > Hi Jonathan,
> >
> Hi Paul,
>
> > This is a respin of the V3 of my patchset that introduced
Hi Jonathan,
Le jeudi 21 décembre 2023 à 16:12 +, Jonathan Cameron a écrit :
> On Tue, 19 Dec 2023 18:50:08 +0100
> Paul Cercueil wrote:
>
> > Use the functions provided by the buffer-dma core to implement the
> > DMABUF userspace API in the buffer-dmaengine IIO buffer
> > implementation.
>
On 21/12/2023 13:28, Raphael Gallais-Pou wrote:
> Add dt-binding file for "st,stm32-lvds" compatible.
>
A nit, subject: drop second/last, redundant "dt-bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
> Signed-off-by: Raphael Gallais-Pou
> ---
> .../bindings/
Hi Jonathan,
Le jeudi 21 décembre 2023 à 12:06 +, Jonathan Cameron a écrit :
> On Tue, 19 Dec 2023 18:50:06 +0100
> Paul Cercueil wrote:
>
> > Add the necessary infrastructure to the IIO core to support a new
> > optional DMABUF based interface.
> >
> > With this new interface, DMABUF objec
The hardware is not able to dynamically balance the load between
CCS engines. Wa_16016805146 suggests disabling it for all
platforms.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Niranjana Vishwanathapura
Cc: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h
Now that the CCS mode is configurable, an interface has been
exposed in the GT's sysfs set of files, allowing users to set the
mode.
Additionally, another interface has been added to display the
number of available slices, named 'num_slices.'
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joona
The CCS mode involves assigning CCS engines to slices depending
on the number of slices and the number of engines the user wishes
to set.
In this patch, the default CCS setting is established during the
initial GT settings. It involves assigning only one CCS to all
the slices.
Based on a patch by
Hi,
This series aims to disable the CCS hardware load balancing, as recommended by
hardware directives in Wa_16016805146.
In the meantime, we need to define and support a fixed CCS mode of balancing
that can be configured by the user.
Thanks,
Andi
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Nira
On Tue, 19 Dec 2023 18:50:01 +0100
Paul Cercueil wrote:
> [V4 was: "iio: Add buffer write() support"][1]
>
> Hi Jonathan,
>
Hi Paul,
> This is a respin of the V3 of my patchset that introduced a new
> interface based on DMABUF objects [2].
Great to see this moving forwards.
>
> The V4 was a
On Tue, 19 Dec 2023 18:50:09 +0100
Paul Cercueil wrote:
> Document the new DMABUF based API.
>
> Signed-off-by: Paul Cercueil
One minor comment inline.
>
> ---
> v2: - Explicitly state that the new interface is optional and is
> not implemented by all drivers.
> - The IOCTLs can now
On Tue, 19 Dec 2023 18:50:08 +0100
Paul Cercueil wrote:
> Use the functions provided by the buffer-dma core to implement the
> DMABUF userspace API in the buffer-dmaengine IIO buffer implementation.
>
> Since we want to be able to transfer an arbitrary number of bytes and
> not necesarily the fu
On Tue, 19 Dec 2023 18:50:07 +0100
Paul Cercueil wrote:
> Implement iio_dma_buffer_attach_dmabuf(), iio_dma_buffer_detach_dmabuf()
> and iio_dma_buffer_transfer_dmabuf(), which can then be used by the IIO
> DMA buffer implementations.
>
> Signed-off-by: Paul Cercueil
>
Hi Paul,
A few comments
> Am 21.12.2023 um 09:58 schrieb Maxime Ripard :
>
> Cool, so what you're saying is that your plan is to support those GPUs
> upstream in the imagination driver?
Yes, I would like to see PowerVR Series 5 SGX supported upstream since there
are still so many devices in the wild which could use it
Hi Vinod,
Le jeudi 21 décembre 2023 à 20:44 +0530, Vinod Koul a écrit :
> On 19-12-23, 18:50, Paul Cercueil wrote:
> > This function can be used to initiate a scatter-gather DMA
> > transfer,
> > where the address and size of each segment is located in one entry
> > of
> > the dma_vec array.
> >
On 19-12-23, 18:50, Paul Cercueil wrote:
> This function can be used to initiate a scatter-gather DMA transfer,
> where the address and size of each segment is located in one entry of
> the dma_vec array.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
> specifying the
Hi,
On 2023/12/7 23:50, Maxime Ripard wrote:
atomic_check and mode_valid do not check for the same things which can
lead to surprising result if the userspace commits a mode that didn't go
through mode_valid. Let's merge the two implementations into a function
called by both.
Signed-off-by: Ma
On Thu, 21 Dec 2023 13:43:33 +0100, Raphael Gallais-Pou wrote:
> Add dt-binding file for "st,stm32-lvds" compatible.
>
> Signed-off-by: Raphael Gallais-Pou
> ---
> .../bindings/display/st,stm32-lvds.yaml | 114 ++
> 1 file changed, 114 insertions(+)
> create mode 100644
Hi,
On 2023/12/7 23:50, Maxime Ripard wrote:
We're not doing anything special in atomic_mode_set so we can simply
merge it into atomic_enable.
Signed-off-by: Maxime Ripard
Acked-by: Sui Jingfeng
Hi,
LGTM,
On 2023/12/7 23:50, Maxime Ripard wrote:
The sun4i_hdmi driver still uses the non-atomic variants of the encoder
hooks, so let's convert to their atomic equivalents.
Signed-off-by: Maxime Ripard
Acked-by: Sui Jingfeng
Hi,
On 14/12/23 17:50, Helen Koike wrote:
On 14/12/2023 05:00, Dmitry Baryshkov wrote:
On Tue, 12 Dec 2023 at 18:04, Vignesh Raman
wrote:
build-kdl.sh was doing a `clone --depth 1` of the default branch,
then checking out a commit that might not be the latest of that
branch, resulting in c
When compiling with gcc version 14.0.0 20231220 (experimental)
and W=1, I've noticed the following warning:
drivers/gpu/drm/nouveau/nouveau_svm.c: In function
'nouveau_svm_fault_buffer_ctor':
drivers/gpu/drm/nouveau/nouveau_svm.c:1014:40: warning: 'kvcalloc' sizes
specified with
'sizeof' in the
On Thu, 21 Dec 2023 at 14:45, Raphael Gallais-Pou
wrote:
>
> From: Yannick Fertre
>
> The latest hardware version of the LTDC presents the addition of a bus
> clock, which contains the global configuration registers and the interrupt
> register.
>
> Signed-off-by: Yannick Fertre
> ---
> drivers
Hi Oak, Christian
On 11/2/23 05:32, Oak Zeng wrote:
We plan to implement xe driver's shared virtual memory
manager (aka SVM) without buffer object concept. This
means we won't build our shared virtual memory manager
upon TTM infrastructure like amdgpu does.
Even though this approach is more eff
Hi Dave & Sima -
A bit more than I'd like at this stage, but next week will be quiet.
drm-intel-fixes-2023-12-21:
drm/i915 fixes for v6.7-rc7:
- Fix state readout and check for DSC and bigjoiner combo
- Fix a potential integer overflow
- Reject async flips with bigjoiner
- Fix MTL HDMI/DP PLL c
This patch enables the following IPs on stm32mp257f-ev :
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel backlight
* Ilitek touchescreen
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++
1 file changed, 79 insertions(+)
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the c
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation. It provides a parallel digital RGB flow to be used
by display interfaces.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 12
1 file changed, 12 insertions(+)
di
This patch adds LVDS support on stm32mp253. The LVDS is used on
STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC
input clock.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp253.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git
From: Yannick Fertre
The latest hardware version of the LTDC presents the addition of a bus
clock, which contains the global configuration registers and the interrupt
register.
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 8
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files
The Low-Voltage Differential Signaling (LVDS) Display Interface
Transmitter handles the LVDS protocol: it maps the pixels received from
the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS
PHY.
It regroups three sub blocks:
* LVDS host: handles the LVDS protocol (FPD / Op
This serie introduces a new DRM bridge driver for STM32MP257 platforms
based on Arm Cortex-35. It also adds an instance in the device-tree and
handle the inclusion of the driver within the DRM framework. First patch
adds a new panel compatible in the panel-lvds driver, which is used by
default on t
Add dt-binding file for "st,stm32-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
.../bindings/display/st,stm32-lvds.yaml | 114 ++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
diff --git a/Docu
List EDT ETML0700Z9NDHA in the LVDS panel enumeration.
Signed-off-by: Raphael Gallais-Pou
---
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
b/Documentation/dev
This patch enables the following IPs on stm32mp257f-ev :
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel backlight
* Ilitek touchescreen
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++
1 file changed, 79 insertions(+)
This patch adds LVDS support on stm32mp253. The LVDS is used on
STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC
input clock.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp253.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation. It provides a parallel digital RGB flow to be used
by display interfaces.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 12
1 file changed, 12 insertions(+)
di
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the c
The Low-Voltage Differential Signaling (LVDS) Display Interface
Transmitter handles the LVDS protocol: it maps the pixels received from
the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS
PHY.
It regroups three sub blocks:
* LVDS host: handles the LVDS protocol (FPD / Op
Add dt-binding file for "st,stm32-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
.../bindings/display/st,stm32-lvds.yaml | 114 ++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
diff --git a/Docu
From: Yannick Fertre
The latest hardware version of the LTDC presents the addition of a bus
clock, which contains the global configuration registers and the interrupt
register.
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 8
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files
List EDT ETML0700Z9NDHA in the LVDS panel enumeration.
Signed-off-by: Raphael Gallais-Pou
---
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
b/Documentation/dev
This serie introduces a new DRM bridge driver for STM32MP257 platforms
based on Arm Cortex-35. It also adds an instance in the device-tree and
handle the inclusion of the driver within the DRM framework. First patch
adds a new panel compatible in the panel-lvds driver, which is used by
default on t
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the ce using the ce_to_guc() helper.
Just a leftover from previous cleanups.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+),
New libdrm has been released.
Marek Olšák (2):
amdgpu: add amdgpu_va_get_start_addr
meson: bump libdrm version to 2.4.119
git tag: libdrm-2.4.119
https://dri.freedesktop.org/libdrm/libdrm-2.4.119.tar.xz
SHA256: 0a49f12f09b5b6e68eaaaff3f02ca7cff9aa926939b212d343161d3e8ac56291
libdrm-
On Tue, 19 Dec 2023 18:50:06 +0100
Paul Cercueil wrote:
> Add the necessary infrastructure to the IIO core to support a new
> optional DMABUF based interface.
>
> With this new interface, DMABUF objects (externally created) can be
> attached to a IIO buffer, and subsequently used for data transf
On Tue, 19 Dec 2023 18:50:04 +0100
Paul Cercueil wrote:
> This function can be used to initiate a scatter-gather DMA transfer,
> where the address and size of each segment is located in one entry of
> the dma_vec array.
>
> The major difference with dmaengine_prep_slave_sg() is that it supports
On Tue, 19 Dec 2023 18:50:03 +0100
Paul Cercueil wrote:
> From: Alexandru Ardelean
>
> This change splits the logic into a separate function, which will be
> re-used later.
>
> Signed-off-by: Alexandru Ardelean
> Cc: Alexandru Ardelean
> Signed-off-by: Paul Cercueil
Harmless refactor so I'm
On Tue, 19 Dec 2023 18:50:02 +0100
Paul Cercueil wrote:
> The buffer-dma code was using two queues, incoming and outgoing, to
> manage the state of the blocks in use.
>
> While this totally works, it adds some complexity to the code,
> especially since the code only manages 2 blocks. It is much
Hi Zack,
thank you for the patch!
On Thu, 2023-09-28 at 00:13 -0400, Zack Rusin wrote:
> From: Zack Rusin
>
> Surfaces can be backed (i.e. stored in) memory objects (mob's) which
> are created and managed by the userspace as GEM buffers. Surfaces
> grab only a ttm reference which means that the
Hi Matthew,
On 12/21/2023 12:51 AM, Matthew Auld wrote:
Hi,
On 14/12/2023 13:42, Arunpravin Paneer Selvam wrote:
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks
Rename the Qualcomm MSM Display schemas to follow the main compatible
string instead of just using the block type. This follows the
established practice for YAML file names.
Cc: Aiqun Yu (Maria)
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/{gmu.yaml => qcom,adreno-gmu.yaml}
While the DSI PHY schema files describe the display-related hardware,
they still describe a PHY. Move all DSI PHY schema files to the phy/
subdir.
Signed-off-by: Dmitry Baryshkov
---
.../msm/dsi-phy-10nm.yaml => phy/qcom,dsi-phy-10nm.yaml} | 4 ++--
.../msm/dsi-phy-14nm.yaml => phy/qcom,dsi
During the email discussion Aiqun Yu (Maria) pointed out that the file
names for some of the MSM display schema files might not be obvious.
Indeed they do not fully follow the established practice of matching the
file name and one of compat strings.
Move DSI PHY schemas to the PHY subdir (renaming
From: Daniel Stone
Add a new ioctl to allow the guest VM to discover how the guest
actually allocated the underlying buffer, which allows buffers to
be used for GL<->Vulkan interop and through standard window systems.
It's also a step towards properly supporting modifiers in the guest.
Signed-of
Hi all,
Sorry to late reply. This is v2 of the implementation of
resource_query_layout. This adds a new ioctl to let guest query information
of host resource, which is originally from Daniel Stone. We add some
changes to support query the correct stride of host resource before it's
created, which
On Thu, Dec 21, 2023 at 11:35:42AM +0200, Jani Nikula wrote:
> On Tue, 19 Dec 2023, Jani Nikula wrote:
> > hdmi-codec.h does not appear to directly need drm/drm_edid.h for
> > anything. Remove it.
> >
> > There are some files that get drm/edid.h by proxy; include it where
> > needed.
> >
> > v2-v4
On Tue, 19 Dec 2023, Jani Nikula wrote:
> hdmi-codec.h does not appear to directly need drm/drm_edid.h for
> anything. Remove it.
>
> There are some files that get drm/edid.h by proxy; include it where
> needed.
>
> v2-v4: Fix build (kernel test robot )
>
> Signed-off-by: Jani Nikula
>
> ---
>
>
To have better compatibility for DP sink, there is a retry mechanism
for the link training process to switch between different training process.
The original driver code doesn't reset the retry counter when training
state is pass. If the system triggers link training over 3 times,
there will be a c
On 20/12/2023 11:08, Moudy Ho wrote:
> To simplify maintenance and avoid branches, the identical component
> should be merged and placed in the path belonging to the MDP
> (from display/* to media/*).
Combining bindings into one bigger meta-binding makes it usually more
difficult to maintain and r
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_debugfs_params.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c | 4 ++-
On 12/6/2023 9:46 PM, Andi Shyti wrote:
Get the guc reference from the gt using the gt_to_guc() helper.
Signed-off-by: Andi Shyti
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 4 +--
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 3 +-
drivers/gpu/drm/i
On 12/6/2023 9:46 PM, Andi Shyti wrote:
We already have guc_to_gt() and getting to guc from the GT it
requires some mental effort. Add the gt_to_guc().
Given the reference to the "gt", the gt_to_guc() will return the
pinter to the "guc".
Update all the files under the gt/ directory.
Signed-o
On Tue, Dec 19, 2023 at 04:40:12PM +0100, Johan Jonker wrote:
>
>
> On 12/19/23 13:55, Maxime Ripard wrote:
> > Hi,
> >
> > On Mon, Dec 18, 2023 at 04:49:06PM +0100, Johan Jonker wrote:
> >> CRTC size validation for the display controller has been added with
> >> Commit 8e140cb60270 ("drm/rockch
On Tue, Dec 19, 2023 at 11:19:49AM -0600, Andrew Davis wrote:
> On 12/18/23 4:54 AM, H. Nikolaus Schaller wrote:
> >
> >
> > > Am 18.12.2023 um 11:14 schrieb Maxime Ripard :
> > >
> > > On Mon, Dec 18, 2023 at 10:28:09AM +0100, H. Nikolaus Schaller wrote:
> > > > Hi Maxime,
> > > >
> > > > > Am
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