Hi Alexandra,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.6-rc3 next-20230929]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
https://bugzilla.kernel.org/show_bug.cgi?id=217958
Bug ID: 217958
Summary: Crashes if I boot the computer with the second display
connected to HDMI output
Product: Drivers
Version: 2.5
Hardware: All
OS: Linu
Hi Mitul,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Mitul-Golani/drm-display-dp-Add-helper-function-to-get-DSC-bpp-precision/20230929-162949
base: git://anongit.freedesktop.org/drm
Hi Uwe,
kernel test robot noticed the following build errors:
[auto build test ERROR on 8fff9184d1b5810dca5dd1a02726d4f844af88fc]
url:
https://github.com/intel-lab-lkp/linux/commits/Uwe-Kleine-K-nig/backlight-pwm_bl-Disable-PWM-on-shutdown-and-suspend/20230926-230323
base: 8fff9184d1b5810d
On 9/23/2023 12:31 AM, Mario Limonciello wrote:
> On 9/22/2023 12:50, Shyam Sundar S K wrote:
>> Sometimes policy binary retrieved from the BIOS maybe incorrect that
>> can
>> end up in failing to enable the Smart PC solution feature.
>>
>> Use print_hex_dump_debug() to dump the policy binary in
On 9/23/2023 12:21 AM, Mario Limonciello wrote:
> On 9/22/2023 12:50, Shyam Sundar S K wrote:
>> PMF Policy binary is a encrypted and signed binary that will be part
>> of the BIOS. PMF driver via the ACPI interface checks the existence
>> of Smart PC bit. If the advertised bit is found, PMF dri
Hi,
On Fri, Sep 29, 2023 at 2:50 PM Laurent Pinchart
wrote:
>
> Hi Doug,
>
> CC'ing the dri-devel mailing list and Douglas Anderson.
>
> On Fri, Sep 29, 2023 at 03:36:52PM -0400, Douglas Cooper wrote:
> > Hello,
> >
> > I've been trying to get the ti-sn65dsi86 to work with the dsi bus as the clk
On 2023-09-19 01:01, Matthew Brost wrote:
> Add helper to queue TDR immediately for current and future jobs. This
> will be used in XE, new Intel GPU driver, to trigger the TDR to cleanup
Please use present tense, "is", in code, comments, commits, etc.
Is it "XE" or is it "Xe"? I always thought i
Hi,
On 2023-09-19 01:01, Matthew Brost wrote:
> If the TDR is set to a value, it can fire before a job is submitted in
> drm_sched_main. The job should be always be submitted before the TDR
> fires, fix this ordering.
>
> v2:
> - Add to pending list before run_job, start TDR after (Luben, Boris
Hi,
On 2023-09-19 01:01, Matthew Brost wrote:
> If the TDR is set to a very small value it can fire before the
> submission is started in the function drm_sched_start. The submission is
> expected to running when the TDR fires, fix this ordering so this
> expectation is always met.
>
> Signed-off
Hi Doug,
CC'ing the dri-devel mailing list and Douglas Anderson.
On Fri, Sep 29, 2023 at 03:36:52PM -0400, Douglas Cooper wrote:
> Hello,
>
> I've been trying to get the ti-sn65dsi86 to work with the dsi bus as the clk
> source (refclk grounded) and have concluded that the pll is not getting
>
+ .cache_type = REGCACHE_MAPLE,
> .volatile_reg = adv7511_cec_register_volatile,
> };
>
>
> ---
> base-commit: 6465e260f48790807eef06b583b38ca9789b6072
> change-id: 20230929-drm-adv7511-2d592921f8a2
--
Regards,
Laurent Pinchart
On Fri, 29 Sept 2023 at 23:53, Luca Weiss wrote:
>
> On Samstag, 23. September 2023 23:49:10 CEST Dmitry Baryshkov wrote:
> > Experimental support for MSM8953, which has MDP5 v1.16. It looks like
> > trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
> > etc.
> >
>
> Hi Dmitry,
Hi,
On 2023-09-19 01:01, Matthew Brost wrote:
> Also add a lockdep assert to drm_sched_start_timeout.
>
> Signed-off-by: Matthew Brost
Reviewed-by: Luben Tuikov
Thanks for this patch!
> ---
> drivers/gpu/drm/scheduler/sched_main.c | 23 +--
> 1 file changed, 13 insertion
On Samstag, 23. September 2023 23:49:10 CEST Dmitry Baryshkov wrote:
> Experimental support for MSM8953, which has MDP5 v1.16. It looks like
> trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
> etc.
>
Hi Dmitry,
As written on IRC, on sdm632-fairphone-fp3 with this DPU patche
From: Ivan Lipski
This reverts commit 45e1ade04b4d60fe5df859076005779f27c4c9be.
Since, it causes the following IGT tests to fail:
kms_cursor_legacy@cursor-vs-flip.*
kms_cursor_legacy@flip-vs-cursor.*
Signed-off-by: Ivan Lipski
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdg
Reviewed-by: Lyude Paul
On Sat, 2023-09-16 at 03:14 +0200, Danilo Krummrich wrote:
> Fix the following warning.
>
> drivers/gpu/drm/nouveau/nouveau_fence.c:210:45: sparse: sparse:
> incorrect type in initializer (different address spaces)
> @@ expected struct nouveau_channel *chan
>
Hi,
The $Subject could be improved, e.g.:
[PATCH] drm/amd/display: add kernel docs for dc_dmub_caps
On 9/29/23 03:00, Sagar Vashnav wrote:
> Add kernel documentation for the dc_dmub_caps structure.
>
> Signed-off-by: Sagar Vashnav
Reviewed-by: Randy Dunlap
Thanks.
> ---
> drivers/gpu/drm
On Fri, 22 Sep 2023 10:32:05 -0700, Kees Cook wrote:
> This is a batch of patches touching drm for preparing for the coming
> implementation by GCC and Clang of the __counted_by attribute. Flexible
> array members annotated with __counted_by can have their accesses
> bounds-checked at run-time chec
On Fri, 15 Sep 2023 12:43:20 -0600, Gustavo A. R. Silva wrote:
> If, for any reason, the open-coded arithmetic causes a wraparound, the
> protection that `struct_size()` adds against potential integer overflows
> is defeated. Fix this by hardening call to `struct_size()` with `size_add()`.
>
>
A
The pull request you sent on Fri, 29 Sep 2023 11:46:12 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-09-29
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/6edc84bc3f8aceae74eb63684d53c17553382ec0
Thank you!
--
Deet-doot-dot, I am a bot.
https://k
On Wed, 16 Aug 2023 12:03:06 -0600, Gustavo A. R. Silva wrote:
> This small series aims to replace a one-element array with a
> flexible-array member in struct nouveau_svm. And, while at it,
> fix a checkpatch.pl error.
>
> Gustavo A. R. Silva (2):
> nouveau/svm: Replace one-element array with f
A new DRM GEM object function is added so that drm_show_memory_stats can
provide more accurate memory usage numbers.
Ideally, in panfrost_gem_status, the BO's purgeable flag would be checked
after locking the driver's shrinker mutex, but drm_show_memory_stats takes
over the drm file's object handl
BO's RSS is updated every time new pages are allocated on demand and mapped
for the object at GPU page fault's IRQ handler, but only for heap buffers.
The reason this is unnecessary for non-heap buffers is that they are mapped
onto the GPU's VA space and backed by physical memory in their entirety
Some BO's might be mapped onto physical memory chunkwise and on demand,
like Panfrost's tiler heap. In this case, even though the
drm_gem_shmem_object page array might already be allocated, only a very
small fraction of the BO is currently backed by system memory, but
drm_show_memory_stats will the
These GPU registers will be used when programming the cycle counter, which
we need for providing accurate fdinfo drm-cycles values to user space.
Signed-off-by: Adrián Larumbe
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/p
The drm-stats fdinfo tags made available to user space are drm-engine,
drm-cycles, drm-max-freq and drm-curfreq, one per job slot.
This deviates from standard practice in other DRM drivers, where a single
set of key:value pairs is provided for the whole render engine. However,
Panfrost has separat
This patch series adds fdinfo support to the Panfrost DRM driver. It will
display a series of key:value pairs under /proc/pid/fdinfo/fd for render
processes that open the Panfrost DRM file.
The pairs contain basic drm gpu engine and memory region information that
can either be cat by a privileged
Hi Luca,
Am Freitag, dem 29.09.2023 um 18:48 +0200 schrieb Luca Ceresoli:
> Hi Lucas,
>
> On Thu, 28 Sep 2023 14:55:35 +0200
> Lucas Stach wrote:
>
> > Add binding for the i.MX8MP HDMI parallel video interface block.
> >
> > Signed-off-by: Lucas Stach
> > Reviewed-by: Laurent Pinchart
> > --
On 29/09/2023 4:45 pm, Will Deacon wrote:
On Mon, Sep 25, 2023 at 06:54:42PM +0100, Robin Murphy wrote:
On 2023-04-10 19:52, Dmitry Baryshkov wrote:
If the Adreno SMMU is dma-coherent, allocation will fail unless we
disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
cohere
Hi Lucas,
On Thu, 28 Sep 2023 14:55:35 +0200
Lucas Stach wrote:
> Add binding for the i.MX8MP HDMI parallel video interface block.
>
> Signed-off-by: Lucas Stach
> Reviewed-by: Laurent Pinchart
> ---
> .../display/imx/fsl,imx8mp-hdmi-pvi.yaml | 83 +++
> 1 file changed,
Hi Lucas,
On Thu, 28 Sep 2023 14:55:36 +0200
Lucas Stach wrote:
> This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a
> full timing generator and can switch between different video sources. On
> the i.MX8MP however the only supported source is the LCDIF. The block
> just ne
https://bugzilla.kernel.org/show_bug.cgi?id=216806
--- Comment #5 from Balazs Vinarz (viniba...@gmail.com) ---
The latest 6.5.5-arch1-1 kernel just turned the display into a full white
screen with high brightness.
--
You may reply to this email to add a comment.
You are receiving this mail beca
On Mon, Sep 25, 2023 at 06:54:42PM +0100, Robin Murphy wrote:
> On 2023-04-10 19:52, Dmitry Baryshkov wrote:
> > If the Adreno SMMU is dma-coherent, allocation will fail unless we
> > disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
> > coherent SMMUs (like we have on sm8350
The 'top_pipe_to_program pointer' can be NULL and it is checked
at the first dereference, but not at the second.
Add a check before using it.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Igor Artemiev
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1
Hi
Am 29.09.23 um 14:11 schrieb Maxime Ripard:
On Wed, Sep 20, 2023 at 04:24:26PM +0200, Thomas Zimmermann wrote:
DRM's format-conversion helpers require temporary memory. Pass the
buffer from the caller and keep it allocated over several calls. Allow
the caller to preallocate the buffer memory
On Thu, Sep 28, 2023 at 02:55:35PM +0200, Lucas Stach wrote:
> Add binding for the i.MX8MP HDMI parallel video interface block.
>
> Signed-off-by: Lucas Stach
> Reviewed-by: Laurent Pinchart
> ---
> .../display/imx/fsl,imx8mp-hdmi-pvi.yaml | 83 +++
> 1 file changed, 83 ins
Hi,
On Thu, Sep 28, 2023 at 2:42 PM Linus Walleij wrote:
>
> On Tue, Sep 26, 2023 at 11:49 PM Doug Anderson wrote:
>
> > > I'm curious what the latest on this patch series is. Is it abandoned,
> > > or is it still on your list to move forward with it? If it's
> > > abandoned, does that mean we'v
On Thu, Sep 28, 2023 at 03:26:16PM +, Wei Liu wrote:
> Please change the prefix to "Drivers: hv:" in the subject line in the
> two patches.
I'll change the commit message for the 14/15 patch from "hyper-v/azure"
to "Drivers: hv:". But I only see one patch that needs this. Which is
the other one
On Fri, Sep 29, 2023 at 10:42:58AM +0200, AngeloGioacchino Del Regno wrote:
> Il 28/09/23 18:49, Conor Dooley ha scritto:
> > On Thu, Sep 28, 2023 at 02:52:23AM +, Moudy Ho (何宗原) wrote:
> > > On Wed, 2023-09-27 at 10:47 +0100, Conor Dooley wrote:
> > > > On Wed, Sep 27, 2023 at 07:19:28AM +
On Tue, Sep 05, 2023 at 03:44:23AM +, Ying Liu wrote:
> On Thursday, August 24, 2023 5:48 PM, Maxime Ripard
> wrote:
> > On Wed, Aug 23, 2023 at 08:47:51AM +, Ying Liu wrote:
> > > > > This dt-binding just follows generic dt-binding rule to describe the
> > > > > DPU
> > IP
> > > > > ha
On 19.09.23 16:08, Bagas Sanjaya wrote:
> On Sat, Sep 02, 2023 at 06:14:12PM +0200, Oleksandr Natalenko wrote:
>>
>> Since v6.5 kernel the following HW:
>>
>> * Lenovo T460s laptop with Skylake GT2 [HD Graphics 520] (rev 07)
>> * Lenovo T490s laptop with WhiskeyLake-U GT2 [UHD Graphics 620] (rev 02
On Fri, Sep 29, 2023 at 3:29 PM syzbot
wrote:
>
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:9ed22ae6be81 Merge tag 'spi-fix-v6.6-rc3' of git://git.ker..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=14b37a7c68
> kernel confi
On 2023-09-29 03:35, Pekka Paalanen wrote:
> On Thu, 28 Sep 2023 16:16:57 -0400
> Harry Wentland wrote:
>
>> On 2023-09-25 15:49, Melissa Wen wrote:
>>> Brief documentation about pre-defined transfer function usage on AMD
>>> display driver and standardized EOTFs and inverse EOTFs.
>>>
>>> v3:
= adv7511_cec_register_volatile,
};
---
base-commit: 6465e260f48790807eef06b583b38ca9789b6072
change-id: 20230929-drm-adv7511-2d592921f8a2
Best regards,
--
Mark Brown
Add support for the 2700x1224 AMOLED BOE panel bundled with a RM692E5
driver IC, as found on the Fairphone 5 smartphone.
Co-developed-by: Luca Weiss
Signed-off-by: Luca Weiss
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile
Raydium RM692E5 is a display driver IC used to drive AMOLED DSI panels.
Describe it.
Reviewed-by: Conor Dooley
Signed-off-by: Konrad Dybcio
---
.../bindings/display/panel/raydium,rm692e5.yaml| 73 ++
1 file changed, 73 insertions(+)
diff --git
a/Documentation/devicetre
The Fairphone 5 smartphone ships with a BOE AMOLED panel in conjunction
with a Raydium RM692E5 driver IC. This series adds the bindings and driver
for that.
Signed-off-by: Konrad Dybcio
---
Changes in v2:
DRIVER:
- Remove 1ms sleeps after each DCS command submission
- Remove WARN_ON from probe()
Some panels support multiple LVDS data mapping formats, which can be
used e.g. run displays on jeida-18 format when only 3 LVDS lanes are
available.
Add parsing of an optional data-mapping devicetree property, which also
touches up the bits per color to match the bus format.
Signed-off-by: Johann
Some Displays support more than just a single default LVDS data mapping,
which can be used to run displays on only 3 LVDS lanes in the jeida-18
data-mapping mode.
Add an optional data-mapping property to allow overriding the default
data mapping. As it does not generally apply to any display and b
As the LVDS data-mapping property is required in multiple bindings: move
it to separate file and include instead of duplicating it.
Reviewed-by: Conor Dooley
Reviewed-by: Laurent Pinchart
Signed-off-by: Johannes Zink
---
Changes:
v4 -> v5: none, but are-dded the reviewed-bys from v2, that wer
Some LVDS panels, such as the innolux,g101ice-l01 support multiple LVDS
data mapping modes, which can be configured by strapping a dataformat
pin on the display to a specific voltage.
This can be particularly useful for using the jeida-18 format, which
requires only 3 instead of 4 LVDS lanes.
Thi
On Thu, Sep 28, 2023 at 03:36:55PM +0200, Greg Kroah-Hartman wrote:
> On Thu, Sep 28, 2023 at 03:21:26PM +0200, Joel Granados via B4 Relay wrote:
> > From: Joel Granados
> >
> > This commit comes at the tail end of a greater effort to remove the
> > empty elements at the end of the ctl_table arra
On Thu, Sep 28, 2023 at 03:26:16PM +, Wei Liu wrote:
> Please change the prefix to "Drivers: hv:" in the subject line in the
> two patches.
>
> On Thu, Sep 28, 2023 at 03:21:39PM +0200, Joel Granados via B4 Relay wrote:
> > From: Joel Granados
> >
> > This commit comes at the tail end of a g
On Thu, Sep 28, 2023 at 12:51:15PM -0500, Steve Wahl wrote:
> On Thu, Sep 28, 2023 at 03:21:36PM +0200, Joel Granados via B4 Relay wrote:
> > From: Joel Granados
> >
> > This commit comes at the tail end of a greater effort to remove the
> > empty elements at the end of the ctl_table arrays (sent
On Wed, Sep 20, 2023 at 04:24:26PM +0200, Thomas Zimmermann wrote:
> DRM's format-conversion helpers require temporary memory. Pass the
> buffer from the caller and keep it allocated over several calls. Allow
> the caller to preallocate the buffer memory.
>
> The motivation for this patchset is th
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is als
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is als
On Thu, 28 Sep 2023, Laurent Pinchart wrote:
> On Wed, Sep 27, 2023 at 05:09:23PM +0300, Jani Nikula wrote:
>> On Wed, 27 Sep 2023, Laurent Pinchart wrote:
>> > On Thu, Sep 14, 2023 at 04:14:50PM +0300, Jani Nikula wrote:
>> >> Make drm_bridge_get_edid() the one place to call the hook.
>> >>
>> >
On Thu, 14 Sep 2023, Rodrigo Vivi wrote:
> On Tue, Sep 12, 2023 at 02:06:27PM +0300, Jani Nikula wrote:
>> The upcoming drm/xe driver [1][2] will reuse the drm/i915 display code,
>> initially by compiling the relevant compilation units separately as part
>> of the xe driver. This series prepares f
el tags/drm-intel-next-2023-09-29
for you to fetch changes up to 3570bd989acc66add5726785058cceffa06b1f54:
drm/i915: Update DRIVER_DATE to 20230929 (2023-09-29 12:43:23 +0300)
drm/i915 feature pull for v6.7:
Features and functi
When a fence signals there is a very small race window where the timestamp
isn't updated yet. sync_file solves this by busy waiting for the
timestamp to appear, but on other ocassions didn't handled this
correctly.
Provide a dma_fence_timestamp() helper function for this and use it in
all appropri
Am 29.09.23 um 11:25 schrieb André Almeida:
Create a section that specifies how to deal with DRM device resets for
kernel and userspace drivers.
Acked-by: Pekka Paalanen
Acked-by: Sebastian Wick
Signed-off-by: André Almeida
Reviewed-by: Christian König
I think that is now ready to be push
: 2dde18cd1d8fac735875f2e4987f11817cc0bc2c
patch link:
https://lore.kernel.org/r/20230927172849.193996-3-jfalempe%40redhat.com
patch subject: [PATCH v3 2/3] drm/panic: Add a drm panic handler
config: arc-randconfig-002-20230929
(https://download.01.org/0day-ci/archive/20230929/202309291753.8xaivqn0
Create a section that specifies how to deal with DRM device resets for
kernel and userspace drivers.
Acked-by: Pekka Paalanen
Acked-by: Sebastian Wick
Signed-off-by: André Almeida
---
v8 changes:
- Add acked-by tags
v7:
https://lore.kernel.org/dri-devel/20230818200642.276735-1-andrealm...@iga
Thomas Zimmermann writes:
> Store and instance of struct drm_xfrm_buf in struct ssd130x_device and
> keep the allocated memory allocated across display updates. Avoid
> possibly reallocating temporary memory on each display update. Instead
> preallocate temporary memory during initialization. Rel
Thomas Zimmermann writes:
Hello Thomas,
> Pass an instance of struct drm_xfrm_buf to DRM's format conversion
> helpers. Update all callers. Drivers will later be able to keep this
> cache across display updates.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Noralf Trønnes
> Cc: Javier Martinez Ca
Il 28/09/23 18:49, Conor Dooley ha scritto:
On Thu, Sep 28, 2023 at 02:52:23AM +, Moudy Ho (何宗原) wrote:
On Wed, 2023-09-27 at 10:47 +0100, Conor Dooley wrote:
On Wed, Sep 27, 2023 at 07:19:28AM +, Moudy Ho (何宗原) wrote:
On Fri, 2023-09-22 at 16:51 +0100, Conor Dooley wrote:
On Fri, Sep
On 9/28/2023 11:42 PM, Andrzej Hajda wrote:
On 28.09.2023 15:00, Nirmoy Das wrote:
Implement intel_gt_mcr_lock_sanitize() to provide a mechanism
for cleaning the steer semaphore when absolutely necessary.
v2: remove unnecessary lock(Andi, Matt)
improve the kernel doc(Matt)
s/intel_g
On 28/09/2023 20:53, Felix Kuehling wrote:
On 2023-09-28 11:38, Shashank Sharma wrote:
Hello Felix, Mukul,
On 28/09/2023 17:30, Felix Kuehling wrote:
On 2023-09-28 10:30, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: Yadav, Arvind
Sent: Thursday,
Thanks reviewing this series. Merged it in gt-next so hopefully we have
bit greener CI for MTL now.
Regards,
Nirmoy
On 9/28/2023 3:00 PM, Nirmoy Das wrote:
Implement intel_gt_mcr_lock_sanitize() to provide a mechanism
for cleaning the steer semaphore when absolutely necessary.
v2: remove u
Thomas Zimmermann writes:
> Hold temporary memory for format conversion in an instance of struct
> drm_xfrm_buf. Update internal helpers of DRM's format-conversion code
> accordingly. Drivers will later be able to keep this cache across
> display updates.
>
> Signed-off-by: Thomas Zimmermann
> -
On Fri, 29 Sep 2023, Ramya SR wrote:
> Hi All ,
>
> Please review the reply comment.
Please read the responses you do get [1]. Please stop
top-posting. Please fix your mail client.
BR,
Jani.
[1] https://lore.kernel.org/r/877coak8o3@intel.com
>
> Regards,
> Ramya SR
>
> -Original Messa
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4 f
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
---
.../gpu/drm/i915/d
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Signed-off-by: S
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if
From: Ankit Nautiyal
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
---
driv
From: Ankit Nautiyal
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractiona
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchw
From: Ankit Nautiyal
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
Acked-by: Maxime Ripard
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +
include/drm/display
Hi
Am 29.09.23 um 09:33 schrieb Geert Uytterhoeven:
Hi Thomas,
On Fri, Sep 29, 2023 at 9:11 AM Thomas Zimmermann wrote:
Am 28.09.23 um 17:32 schrieb Geert Uytterhoeven:
On Thu, Sep 28, 2023 at 3:59 PM Thomas Zimmermann wrote:
Am 28.09.23 um 14:16 schrieb Geert Uytterhoeven:
is the second
On Thu, 28 Sep 2023 16:16:57 -0400
Harry Wentland wrote:
> On 2023-09-25 15:49, Melissa Wen wrote:
> > Brief documentation about pre-defined transfer function usage on AMD
> > display driver and standardized EOTFs and inverse EOTFs.
> >
> > v3:
> > - Document BT709 OETF (Pekka)
> > - Fix descrip
Hi Thomas,
On Fri, Sep 29, 2023 at 9:11 AM Thomas Zimmermann wrote:
> Am 28.09.23 um 17:32 schrieb Geert Uytterhoeven:
> > On Thu, Sep 28, 2023 at 3:59 PM Thomas Zimmermann
> > wrote:
> >> Am 28.09.23 um 14:16 schrieb Geert Uytterhoeven:
> >>> is the second largest header file in
> >>> the DRM
Am 28.09.23 um 14:16 schrieb Geert Uytterhoeven:
Fix misspellings of "preceding".
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_atomic_helper.c | 4 ++--
include/drm/drm_modeset_helper_vtables.h | 2 +-
2 files changed, 3 insertions(+),
Am 28.09.23 um 14:16 schrieb Geert Uytterhoeven:
Fix misspellings of "hardware".
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Thomas Zimmermann
---
include/drm/drm_bridge.h | 2 +-
include/drm/drm_modeset_helper_vtables.h | 4 ++--
2 files changed, 3 insertions(+),
Hi
Am 28.09.23 um 17:32 schrieb Geert Uytterhoeven:
Hi Thomas,
On Thu, Sep 28, 2023 at 3:59 PM Thomas Zimmermann wrote:
Am 28.09.23 um 14:16 schrieb Geert Uytterhoeven:
is the second largest header file in
the DRM subsystem, and declares helpers vtables for various DRM
components. Several
Hi Iago,
additional to Maria's comments:
Please keep the order of the compatible strings.
Also you need to update the device tree binding before this patch:
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
Also make sure that the series is send to the maintainers, not just
dri-devel by
The One Mix 2S is a mini laptop with a 1200x1920 portrait screen
mounted in a landscape oriented clamshell case. Because of the too
generic DMI strings this entry is also doing bios-date matching.
Signed-off-by: Kai Uwe Broulik
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 16
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