On Mon, Sep 25, 2023 at 03:49:29PM -0700, Douglas Anderson wrote:
> As per the discussion on the lists [1], changes to this driver
> generally flow through drm-misc. Add a tag in MAINTAINERS to document
> this
>
> [1]
> https://lore.kernel.org/r/20230925054710.r3guqn5jzdl4g...@fsr-ub1664-121.ea.f
This patch fixes a smatch warning:
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.c:2868
smu_v13_0_0_check_ecc_table_support() warn: missing error code? 'ret'
This warning is caused by the fact that this function returns the value of
the variable ret. However, the value of ret is no
This patch fixes a null pointer dereference in the error message that is
printed when the Display Core (DC) fails to initialize. The original
message includes the DC version number, which is undefined if the DC is
not initialized.
Fixes: 9788d087caff ("drm/amd/display: improve the message printed
Use local variable for debugfs root, just to make further changes
easier.
Signed-off-by: Stanislaw Gruszka
---
I'll squash that patch into patch 1
drivers/accel/ivpu/ivpu_debugfs.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/accel/ivpu/ivpu_debugf
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced this warning:
Error: Cannot open file /home/sfr/next/next/drivers/gpu/drm/drm_gpuva_mgr.c
Error: Cannot open file /home/sfr/next/next/include/drm/drm_gpuva_mgr.h
Introduced by commit
f72c2db47080 ("drm/gpuvm
Hello,
kernel test robot noticed
"WARNING:at_drivers/gpu/drm/drm_fbdev_generic.c:#drm_fbdev_generic_helper_fb_dirty"
on:
commit: e5f31d1a2da5d43187a0e1fc4d1882982ab0d9b8 ("[PATCH v17 10/18]
drm/shmem-helper: Use refcount_t for vmap_use_count")
url:
https://github.com/intel-lab-lkp/linux/co
From: Zack Rusin
Some drivers require the mapped tt pages to be decrypted. In an ideal
world this would have been handled by the dma layer, but the TTM page
fault handling would have to be rewritten to able to do that.
A side-effect of the TTM page fault handling is using a dma allocation
per or
On Tuesday, September 5, 2023 4:37 PM, Maxime Ripard wrote:
> On Tue, Sep 05, 2023 at 03:32:47AM +, Ying Liu wrote:
> > > On Tue, Aug 22, 2023 at 04:59:48PM +0800, Liu Ying wrote:
> > > > +int dpu_cf_init(struct dpu_soc *dpu, unsigned int index,
> > > > + unsigned int id, enum dp
Hi Nirmoy,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-tip/drm-tip
drm/drm-next drm-exynos/exynos-drm-next drm-misc/drm-misc-next linus/master
v6.6-rc3 next-20230925]
[If
Hello,
kernel test robot noticed a -3.2% regression of
phoronix-test-suite.paraview.WaveletContour.1024x768.mipolys___sec on:
commit: 54fef7ea35dadd66193b98805b0bc42ef2b279db ("[PATCH] drm/i915/gem: Allow
users to disable waitboost")
url:
https://github.com/intel-lab-lkp/linux/commits/Vina
Since I will continue to work on Nouveau consistently, also beyond my
former and still ongoing VM_BIND/EXEC work, add myself to the list of
Nouveau maintainers.
Signed-off-by: Danilo Krummrich
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b19
On Mon, 25 Sep 2023 19:26:30 -0400, Richard Acayan wrote:
> Add documentation for the SDM670 display subsystem, adapted from the
> SDM845 and SM6125 documentation.
>
> Signed-off-by: Richard Acayan
> ---
> .../display/msm/qcom,sdm670-mdss.yaml | 280 ++
> 1 file changed
On 9/15/23 11:46, Boris Brezillon wrote:
>> -static int drm_gem_shmem_get_pages_locked(struct drm_gem_shmem_object
>> *shmem)
>> +static int
>> +drm_gem_shmem_acquire_pages(struct drm_gem_shmem_object *shmem, bool init)
>> {
>> struct drm_gem_object *obj = &shmem->base;
>> struct page *
On 9/15/23 11:46, Boris Brezillon wrote:
> The naming becomes quite confusing, with drm_gem_shmem_unpin_locked()
> and drm_gem_shmem_unpin_pages_locked(). By the look of it, it seems to
> do exactly the opposite of drm_gem_shmem_swapin_locked(), except for
> the missing ->evicted = true, which we c
Add support for the MDSS block on the SDM670 platform.
Signed-off-by: Richard Acayan
---
drivers/gpu/drm/msm/msm_mdss.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 2e87dd6cb17b..2afb843271aa 100644
--- a/drivers
The Snapdragon 670 uses similar clocks (with one frequency added) to the
Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
with configuration from the Pixel 3a downstream kernel.
Since revision 4.0 is SDM845, reuse some configuration from its catalog
entry.
Link:
https://andr
The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.
Signed-off-by: Richard Acayan
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 +++
1 file changed, 294 insertions(+)
diff --git a/arch/arm64/bo
The SDM670 display controller has the same requirements as the SDM845
display controller, despite having distinct properties as described in
the catalog. Add the compatible for SDM670 to the SDM845 controller.
Signed-off-by: Richard Acayan
---
.../devicetree/bindings/display/msm/qcom,sdm845-dpu.
Add documentation for the SDM670 display subsystem, adapted from the
SDM845 and SM6125 documentation.
Signed-off-by: Richard Acayan
---
.../display/msm/qcom,sdm670-mdss.yaml | 280 ++
1 file changed, 280 insertions(+)
create mode 100644
Documentation/devicetree/bindings
The SDM670 has DSI ports. Add the compatible for the controller.
Signed-off-by: Richard Acayan
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b/Docum
This series adds support for the display subsystem on the Snapdragon
670. It is based on an earlier patch a few versions back, which had
missing device tree bindings and device tree changes.
There is a separate IOMMU patch which adds the MDSS compatible to a
workaround.
Richard Acayan (6):
dt-b
Hi,
On Sun, Sep 24, 2023 at 10:47 PM Laurentiu Palcu
wrote:
>
> Hi Doug,
>
> On Fri, Sep 22, 2023 at 08:44:16AM -0700, Doug Anderson wrote:
> > Hi,
> >
> > On Fri, Sep 22, 2023 at 12:56 AM Laurentiu Palcu
> > wrote:
> > >
> > > Hi,
> > >
> > > On Thu, Sep 21, 2023 at 12:26:44PM -0700, Douglas An
As per the discussion on the lists [1], changes to this driver
generally flow through drm-misc. Add a tag in MAINTAINERS to document
this
[1]
https://lore.kernel.org/r/20230925054710.r3guqn5jzdl4g...@fsr-ub1664-121.ea.freescale.net
Signed-off-by: Douglas Anderson
---
MAINTAINERS | 1 +
1 file
On 9/25/23 17:59, Arnd Bergmann wrote:
From: Arnd Bergmann
After a recent change, two variables are only used in an #ifdef:
drivers/gpu/drm/nouveau/dispnv50/disp.c: In function 'nv50_sor_atomic_disable':
drivers/gpu/drm/nouveau/dispnv50/disp.c:1569:13: error: unused variable 'ret'
[-Werror=un
In commit 5f04e7ce392d ("drm/panel-edp: Split eDP panels out of
panel-simple") I moved a pile of panels out of panel-simple driver
into the newly created panel-edp driver. One of those panels, however,
shouldn't have been moved.
As is clear from commit e35e305eff0f ("drm/panel: simple: Add AUO
B11
On 9/19/23 13:44, Danilo Krummrich wrote:
Hi Matt,
On 9/19/23 07:01, Matthew Brost wrote:
As a prerequisite to merging the new Intel Xe DRM driver [1] [2], we
have been asked to merge our common DRM scheduler patches first.
This a continuation of a RFC [3] with all comments addressed, ready fo
Hi Shyam,
kernel test robot noticed the following build warnings:
[auto build test WARNING on hid/for-next]
[also build test WARNING on linus/master v6.6-rc3 next-20230925]
[cannot apply to drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
Make it explicit that child nodes have additional properties and the
child node schema is not complete. The complete schemas are applied
separately based the compatible strings.
Signed-off-by: Rob Herring
---
.../bindings/display/msm/qcom,msm8998-mdss.yaml| 6 ++
.../bindings/displa
Just as unevaluatedProperties or additionalProperties are required at
the top level of schemas, they should (and will) also be required for
child node schemas. That ensures only documented properties are
present for any node.
Signed-off-by: Rob Herring
---
Documentation/devicetree/bindings/displ
Add helper script that given a gitlab pipeline url, analise which are
the failures and flakes and update the xfails folder accordingly.
Example:
Trigger a pipeline in gitlab infrastructure, than re-try a few jobs more
than once (so we can have data if failues are consistent across jobs
with the sa
Map the plane CTM driver-specific property to DC plane, instead of DC
stream. The remaining steps to program DPP block are already implemented
on DC shared-code.
v3:
- fix comment about plane and CRTC CTMs priorities (Harry)
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgp
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Reviewed-by: Harry Wentland
Enable usage of predefined transfer func in addition to shaper 1D LUT.
That means we can save some complexity by just setting a predefined
curve, instead of programming a custom curve when preparing color space
for applying 3D LUT.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_
From: Joshua Ashton
We should reset a plane state if at least one of the color management
properties differs from old and new state.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amd
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
drivers/gpu/drm/amd/display/i
From: Joshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority. That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We retu
DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.
Reviewed-by: Harry Wentland
From: Joshua Ashton
Create drm_color_ctm_3x4 to support 3x4-dimension plane CTM matrix and
convert DRM CTM to DC CSC float matrix.
v3:
- rename ctm2 to ctm_3x4 (Harry)
Signed-off-by: Joshua Ashton
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 28 +--
.../amd/display/amdg
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgp
From: Joshua Ashton
Map plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
modu
Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD
display HW, 3D LUT comes after a shaper curve and we always have to
program a shaper curve to delinearize or normalize the color space
before applying a 3D LUT (since we have a reduced number of LUT
entries).
In this version, th
From: Joshua Ashton
Add predefined transfer function programming. There is no pre-blending
out gamma ROM, but we can use AMD color modules to program LUT
parameters from a pre-defined TF and an empty regamma LUT (or bump up
LUT parameters with pre-defined TF setup).
v2:
- update crtc color mgmt
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
conflits with DRM CRTC CTM property.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
-
Map DC shaper LUT to DM plane color management. Shaper LUT can be used
to delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. If a plane degamma is
apply to linearize the color space, a custom shaper 1D LUT can be used
just before applying
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
v2:
- remove redundant color caps assignment on plane degamma map (Harry)
- pass color caps to degamma params
v3:
- remove unused color_caps parameter from set_color_proper
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinat
Add AMD pre-defined transfer function property to default DRM CRTC
gamma to convert to wire encoding with or without a user gamma LUT.
There is no post-blending regamma ROM for pre-defined TF. When setting
blend TF (!= Identity) and LUT at the same time, the color module will
combine the pre-define
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D LUT
From: Joshua Ashton
Blend 1D LUT or a pre-defined transfer function (TF) can be set to
linearize content before blending, so that it's positioned just before
blending planes in the AMD color mgmt pipeline, and after 3D LUT
(non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D
LUT
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR content,
Describe some expected behavior of the AMD DM color mgmt programming.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdg
On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT. Add pre-defined transfer function to enable delinearizing content
with or without shaper LUT, where AMD color module calculates the
resulted shaper curve. W
From: Joshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgp
Add 3D LUT property for plane color transformations using a 3D lookup
table. 3D LUT allows for highly accurate and complex color
transformations and is suitable to adjust the balance between color
channels. It's also more complex to manage and require more
computational resources. Since a 3D LUT ha
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Reviewed-by: Harry
Instead of relying on color block names to get the transfer function
intention regarding encoding pixel's luminance, define supported
Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that
includes pure gamma or standardized transfer functions.
v3:
- squash linear and unity TFs to iden
Brief documentation about pre-defined transfer function usage on AMD
display driver and standardized EOTFs and inverse EOTFs.
v3:
- Document BT709 OETF (Pekka)
- Fix description of sRGB and pure power funcs (Pekka)
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Mel
Hook up driver-specific atomic operations for managing AMD color
properties. Create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`.
First add plane degamma LUT properties that means user-blob and its
size. We will add
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to delinearize
content with or without LUT.
v2:
- rename TF enum prefix from DRM_ to AMDGPU_ (Harry)
- remove HLG TF
Reviewed-by: Harry Wentland
Signed-o
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Reviewed-by: Harry Wentland
Reviewed-by: Liviu Dudau
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
driv
Hi,
This series extends the current KMS color management API with AMD
driver-specific properties to enhance the color management support on
AMD Steam Deck. The key additions to the color pipeline include:
- plane degamma LUT and pre-defined TF;
- plane HDR multiplier;
- plane CTM 3x4;
- plane sha
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
-
On Mon, Sep 25, 2023 at 1:52 PM Kees Cook wrote:
>
> On Mon, Sep 25, 2023 at 08:30:30AM +0200, Christian König wrote:
> > Am 22.09.23 um 19:41 schrieb Alex Deucher:
> > > On Fri, Sep 22, 2023 at 1:32 PM Kees Cook wrote:
> > > > Prepare for the coming implementation by GCC and Clang of the
> > >
Am 25.09.23 um 14:55 schrieb Boris Brezillon:
+The imagination team, who's probably interested too.
On Mon, 25 Sep 2023 00:43:06 +0200
Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the amount
of jobs in flight. Therefore, a scheduler is initialized w
On 2023-04-10 19:52, Dmitry Baryshkov wrote:
If the Adreno SMMU is dma-coherent, allocation will fail unless we
disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
coherent SMMUs (like we have on sm8350 platform).
Hmm, but is it right that it should fail in the first place?
On Mon, Sep 25, 2023 at 08:30:30AM +0200, Christian König wrote:
> Am 22.09.23 um 19:41 schrieb Alex Deucher:
> > On Fri, Sep 22, 2023 at 1:32 PM Kees Cook wrote:
> > > Prepare for the coming implementation by GCC and Clang of the __counted_by
> > > attribute. Flexible array members annotated with
On Mon, Sep 25, 2023 at 12:08:36PM +0200, Andrzej Hajda wrote:
>
>
> On 22.09.2023 19:32, Kees Cook wrote:
> > Prepare for the coming implementation by GCC and Clang of the __counted_by
> > attribute. Flexible array members annotated with __counted_by can have
> > their accesses bounds-checked at
Hi Jani,
added comments in-line.
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, September 7, 2023 2:58 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org; Nikula, Jani ;
> Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 4/6] drm/edid: use a temp v
On Fri, 22 Sep 2023 10:54:17 -0700, Kees Cook wrote:
> Prepare for the coming implementation by GCC and Clang of the __counted_by
> attribute. Flexible array members annotated with __counted_by can have
> their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
> (for array indexi
From: Jonathan Cavitt
Where applicable, use for_each_gt instead of to_gt in the
i915_gem_shrinker functions to make them apply to more than just the
primary GT. Specifically, this ensure i915_gem_shrink_all retires all
requests across all GTs, and this makes i915_gem_shrinker_vmap unmap
VMAs fro
Hi,
On Mon, Sep 25, 2023 at 8:57 AM Deucher, Alexander
wrote:
>
> [Public]
>
> > -Original Message-
> > From: Douglas Anderson
> > Sent: Thursday, September 21, 2023 3:27 PM
> > To: dri-devel@lists.freedesktop.org; Maxime Ripard
> > Cc: Douglas Anderson ; Zhang, Bokun
> > ; Zhang, Hawki
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, September 7, 2023 2:58 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org; Nikula, Jani ;
> Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 3/6] drm/edid: include drm_eld.h only where required
>
> Redu
On Mon, 25 Sep 2023 16:38:46 +0800, xiazhengqiao wrote:
> Add compatible string "mediatek,mt8188-rt5682" to support new board
> with rt5682s codec.
> ---
> .../devicetree/bindings/sound/mediatek,mt8188-mt6359.yaml| 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring
Hi Jernej,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.6-rc3 next-20230925]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, September 7, 2023 2:58 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org; Nikula, Jani ;
> Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 2/6] drm/eld: replace uint8_t with u8
>
> Unify on kernel
On 9/25/2023 11:27, Deucher, Alexander wrote:
[Public]
-Original Message-
From: amd-gfx On Behalf Of
Shyam Sundar S K
Sent: Friday, September 22, 2023 1:51 PM
To: hdego...@redhat.com; markgr...@kernel.org; Natikar, Basavaraj
; ji...@kernel.org;
benjamin.tissoi...@redhat.com; Deucher, A
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Shyam Sundar S K
> Sent: Friday, September 22, 2023 1:51 PM
> To: hdego...@redhat.com; markgr...@kernel.org; Natikar, Basavaraj
> ; ji...@kernel.org;
> benjamin.tissoi...@redhat.com; Deucher, Alexander
> ; Koenig, Christian
> ;
Hi,
On Mon, Sep 25, 2023 at 8:49 AM Deucher, Alexander
wrote:
>
> [Public]
>
> > -Original Message-
> > From: Douglas Anderson
> > Sent: Thursday, September 21, 2023 3:27 PM
> > To: dri-devel@lists.freedesktop.org; Maxime Ripard
> > Cc: Douglas Anderson ; Pan, Xinhui
> > ; airl...@gmail
On Fri, Sep 22, 2023 at 03:21:09PM +0800, Moudy Ho wrote:
> Add the fundamental hardware configuration of component STITCH,
STITCH? You mean TCC?
> which is controlled by MDP3 on MT8195.
>
> Signed-off-by: Moudy Ho
> ---
> .../bindings/media/mediatek,mdp3-tcc.yaml | 60 +++
On 9/22/2023 6:35 PM, Abhinav Kumar wrote:
Hi Stephen
On 9/22/2023 2:54 PM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2023-09-19 02:50:12)
On Mon, 18 Sept 2023 at 20:48, Kuogee Hsieh
wrote:
On 9/15/2023 6:21 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh
wr
On 2023-09-13 12:43, Melissa Wen wrote:
> Color caps changed between HW versions which caused DCN10 color state
> sections on DTN log no longer fit DCN3.0 versions. Create a
> DCN3.0-specific color state logging and hook it to drivers of DCN3.0
> family.
>
> rfc-v2:
> - detail RAM mode for gamc
On 2023-09-13 12:43, Melissa Wen wrote:
> Hi,
>
> This is an update of previous RFC [0] improving the data collection of
> Gamma Correction and Blend Gamma color blocks.
>
> As I mentioned in the last version, I'm updating the color state part of
> DTN log to match DCN3.0 HW better. Currently,
On 2023-09-13 12:43, Melissa Wen wrote:
> Logging DCN3 MPC state was following DCN1 implementation that doesn't
> consider new DCN3 MPC color blocks. Create new elements according to
> DCN3 MPC color caps and a new DCN3-specific function for reading MPC
> data.
>
> Signed-off-by: Melissa Wen
>
From: Arnd Bergmann
After a recent change, two variables are only used in an #ifdef:
drivers/gpu/drm/nouveau/dispnv50/disp.c: In function 'nv50_sor_atomic_disable':
drivers/gpu/drm/nouveau/dispnv50/disp.c:1569:13: error: unused variable 'ret'
[-Werror=unused-variable]
1569 | int ret;
[Public]
> -Original Message-
> From: Douglas Anderson
> Sent: Thursday, September 21, 2023 3:27 PM
> To: dri-devel@lists.freedesktop.org; Maxime Ripard
> Cc: Douglas Anderson ; Zhang, Bokun
> ; Zhang, Hawking ;
> Zhu, James ; Zhao, Victor ;
> Pan, Xinhui ; airl...@gmail.com; Deucher, Al
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, September 7, 2023 2:58 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org; Nikula, Jani ;
> Golani, Mitulkumar Ajitkumar
> Subject: [PATCH 1/6] drm/edid: split out drm_eld.h from drm_edid.h
>
> The dr
[Public]
> -Original Message-
> From: Douglas Anderson
> Sent: Thursday, September 21, 2023 3:27 PM
> To: dri-devel@lists.freedesktop.org; Maxime Ripard
> Cc: Douglas Anderson ; Pan, Xinhui
> ; airl...@gmail.com; Deucher, Alexander
> ; amd-...@lists.freedesktop.org; Koenig,
> Christian ;
Dne ponedeljek, 25. september 2023 ob 09:57:22 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sun, Sep 24, 2023 at 09:26:00PM +0200, Jernej Skrabec wrote:
> > Since ddc-en property handling was moved from sun8i dw-hdmi driver to
> > display connector driver, probe order of drivers determines if ED
Hi Jani,
> >>struct i915_vma *vma, *next;
> >>unsigned long freed_pages = 0;
> >>intel_wakeref_t wakeref;
> >> + struct intel_gt *gt;
> >> + int i;
> >
> > the trend is to use 'unsigned int' here and I've seen it
> > reviewed. Personally, if I really have to express a preference, I
>
On Mon, 25 Sep 2023, Andi Shyti wrote:
> Hi Nirmoy,
>
> you forgot the v2 here.
>
> On Mon, Sep 25, 2023 at 03:49:38PM +0200, Nirmoy Das wrote:
>> From: Jonathan Cavitt
>>
>> Where applicable, use for_each_gt instead of to_gt in the
>> i915_gem_shrinker functions to make them apply to more than
Dne ponedeljek, 25. september 2023 ob 09:47:15 CEST je Maxime Ripard napisal(a):
> On Sun, Sep 24, 2023 at 09:26:02PM +0200, Jernej Skrabec wrote:
> > There is no reason to register two drivers in same place. Using macro
> > lowers amount of boilerplate code.
>
> There's one actually: you can't ha
Hi Tvrtko,
On Mon, Sep 25, 2023 at 03:28:27PM +0100, Tvrtko Ursulin wrote:
>
> On 25/09/2023 15:14, Andi Shyti wrote:
> > Hi Tvrtko,
> >
> > On Wed, Sep 20, 2023 at 09:57:15AM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > >
> > > Recent refactoring left an unsightly block of empt
On Fri, Sep 22, 2023 at 3:22 PM Imre Deak wrote:
>
> On Fri, Sep 22, 2023 at 03:02:23PM -0400, Lyude Paul wrote:
> >
> > Oh! wow thank you for catching this:
> >
> > Reviewed-by: Lyude Paul
> >
> > I will go and push this to drm-misc-next in just a moment
> >
> > On Fri, 2023-09-15 at 10:24 +0530
On 2023-07-21 09:24, Melissa Wen wrote:
> dc->caps.color.mpc.gamut_remap says there is a post-blending color block
> for gamut remap matrix for DCN3 HW family and newer versions. However,
> those drivers still follow DCN10 programming that remap stream
> gamut_remap_matrix to DPP (pre-blending).
Some GPUs - particularly A7xx ones - are really really stubborn and
sometimes take a longer-than-expected time to finish unhalting GBIF.
Note that this is not caused by the request a few lines above.
Poll for the unhalt ack to make sure we're not trying to write bits to
an essentially dead GPU th
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/
A740 builds upon the A730 IP, shuffling some values and registers
around. More differences will appear when things like BCL are
implemented.
adreno_is_a740_family is added in preparation for more A7xx GPUs,
the logic checks will be valid resulting in smaller diffs.
Tested-by: Neil Armstrong # on
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