-tip next-20230915]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Ku
https://bugzilla.kernel.org/show_bug.cgi?id=217916
Bug ID: 217916
Summary: amdgpu: ring gfx_low timeout (Google Maps zooming)
Product: Drivers
Version: 2.5
Hardware: All
OS: Linux
Status: NEW
Severity: nor
Hi Alan,
kernel test robot noticed the following build errors:
[auto build test ERROR on cf1e91e884bb1113c653e654e9de1754fc1d4488]
url:
https://github.com/intel-lab-lkp/linux/commits/Alan-Previn/drm-i915-pxp-mtl-Update-pxp-firmware-response-timeout/20230916-023150
base: cf1e91e884bb1113c65
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
>
> The is_connected flag is set to true after DP mainlink successfully
> finish link training. Replace the is_connected flag with link_ready
finishes.
Also this is not a replace, this patch renames the flag.
> flag to avoid confusing.
confusin
On Sat, 16 Sept 2023 at 00:39, Kuogee Hsieh wrote:
>
> Currently eDP population is done at msm_dp_modeset_init() which happen
> at binding time. Move eDP population to be done at display probe time
> so that probe deferral cases can be handled effectively.
> wait_for_hpd_asserted callback is added
Hello,
syzbot found the following issue on:
HEAD commit:0bb80ecc33a8 Linux 6.6-rc1
git tree: upstream
console+strace: https://syzkaller.appspot.com/x/log.txt?x=1002530c68
kernel config: https://syzkaller.appspot.com/x/.config?x=f4894cf58531f
dashboard link: https://syzkaller.appspo
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
>
> Add pm_runtime_force_suspend()/resume() to complete incorporating pm
> runtime framework into DP driver. Both dp_pm_prepare() and dp_pm_complete()
> are added to set hpd_state to correct state. After resume, DP driver will
> re training its ma
Fix the following warning.
drivers/gpu/drm/nouveau/nouveau_fence.c:210:45: sparse: sparse:
incorrect type in initializer (different address spaces)
@@ expected struct nouveau_channel *chan
@@ got struct nouveau_channel [noderef] __rcu *channel
We're just about to emit the fence, t
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
>
> EV_HPD_INIT_SETUP flag is used to trigger the initialization of external
> DP host controller. Since external DP host controller initialization had
> been incorporated into pm_runtime_resume(), this flag become obsolete.
became
> Lets get ri
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
>
> Currently DP driver is executed independent of PM runtime framework.
> This lead DP driver incompatible with others. Incorporating pm runtime
Why is it incompatible? Which others are mentioned here?
> framework into DP driver so that both po
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
>
> Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
> framework, to report HPD status changes to user space frame work.
> Replace it with drm_bridge_hpd_notify() since DP driver is part of drm
> bridge.
>
> Signed-off-by:
On Fri, 15 Sept 2023 at 23:45, Abhinav Kumar wrote:
>
> dsi_wait4video_done() API waits for the DSI video mode engine to
> become idle so that we can transmit the DCS commands in the
> beginning of BLLP. However, with the current sequence, the MDP
> timing engine is turned on after the panel's pre
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
>
> Currently the dp_display_irq_handler() is executed at msm_dp_modeset_init()
> which ties irq registration to the DPU device's life cycle, while depending on
> resources that are released as the DP device is torn down. Move register DP
> driver
On Sat, 16 Sept 2023 at 02:01, Abhinav Kumar wrote:
>
>
>
> On 9/11/2023 2:45 PM, Dmitry Baryshkov wrote:
> > Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
> > are all related to different versions of the same HW scaling block.
> > Corresponding driver parts use scaler_bl
On Thu, Sep 14, 2023 at 02:03:00PM +0700, Bagas Sanjaya wrote:
> #regzbot introduced: v6.5..v6.6
> https://bugzilla.kernel.org/show_bug.cgi?id=217905
> #regzbot title: shutdown/reboot hang on Ryzen 5825U (stuck on amdgpu
> initialization)
>
Fixing up commit range:
#regzbot introduced: v6.5..v6
Hi Dan,
On 9/15/23 14:59, Dan Carpenter wrote:
The u_memcpya() function is supposed to return error pointers on
error. Returning NULL will lead to an Oops.
Fixes: 68132cc6d1bc ("nouveau/u_memcpya: use vmemdup_user")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/nouveau/nouveau_drv.h | 2
On 9/11/2023 2:45 PM, Dmitry Baryshkov wrote:
Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block.
Corresponding driver parts use scaler_blk.version to identify the
correct way to program the hardware. In or
[WHY]
edid_override and drm_edid_override_connector_update, according to drm
documentation, should not be referred outside drm_edid.
[HOW]
Remove and replace them accordingly. This can tested by IGT's
kms_hdmi_inject test.
Signed-off-by: Alex Hung
---
V2 - add comments for drm_get_edid and chec
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 3 +
drivers/gpu/drm
From: John Harrison
Use the new w/a KLV support to enable a MTL w/a. Note, this w/a is a
super-set of Wa_16019325821, so requires turning that one as well as
setting the new flag for Wa_14019159160 itself.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 +++
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 19 +++
drivers/gpu/drm/i915/gt/
From: John Harrison
The latest GuC has new features and new workarounds that we wish to
enable. So let the universe know that it is useful to update their
firmware.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletion
From: John Harrison
Enable Wa_14019159160 and Wa_16019325821 for MTL
RCS/CCS workarounds for MTL.
Signed-off-by: John Harrison
John Harrison (4):
drm/i915/guc: Update 'recommended' version to 70.11.0 for
DG2/ADL-P/MTL
drm/i915: Enable Wa_16019325821
drm/i915/guc: Add support for w
On 9/11/2023 2:45 PM, Dmitry Baryshkov wrote:
As the subblock info is now mostly gone, inline and drop the macro
DPU_HW_SUBBLK_INFO.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 40 ++-
1 file changed, 21 insertions(+), 19 deletions(-
On 9/11/2023 2:02 AM, John Watts wrote:
SPI drivers needs their own list of compatible device IDs in order
for automatic module loading to work. Add those for this driver.
Hi John,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
Signed-off-by: John Watts
---
drivers/gpu/drm/panel/
On 9/11/2023 2:45 PM, Dmitry Baryshkov wrote:
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +--
.../msm/disp/dpu1/catalog/dpu_4_0_s
EV_HPD_INIT_SETUP flag is used to trigger the initialization of external
DP host controller. Since external DP host controller initialization had
been incorporated into pm_runtime_resume(), this flag become obsolete.
Lets get rid of it.
Changes in v3:
-- drop EV_HPD_INIT_SETUP and msm_dp_irq_posti
Currently eDP population is done at msm_dp_modeset_init() which happen
at binding time. Move eDP population to be done at display probe time
so that probe deferral cases can be handled effectively.
wait_for_hpd_asserted callback is added during drm_dp_aux_init()
to ensure eDP's HPD is up before pro
Incorporate pm runtime framework into DP driver and clean up eDP
by moving of_dp_aux_populate_bus() to probe().
-- add v3 changes log
Kuogee Hsieh (7):
drm/msm/dp: tie dp_display_irq_handler() with dp driver
drm/msm/dp: replace is_connected with link_ready
drm/msm/dp: use drm_bridge_hpd_not
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report HPD status changes to user space frame work.
Replace it with drm_bridge_hpd_notify() since DP driver is part of drm
bridge.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display.c | 20 ++---
Add pm_runtime_force_suspend()/resume() to complete incorporating pm
runtime framework into DP driver. Both dp_pm_prepare() and dp_pm_complete()
are added to set hpd_state to correct state. After resume, DP driver will
re training its main link after .hpd_enable() callback enabled HPD
interrupts an
Currently DP driver is executed independent of PM runtime framework.
This lead DP driver incompatible with others. Incorporating pm runtime
framework into DP driver so that both power and clocks to enable/disable
host controller fits with PM runtime mechanism. Once pm runtime framework
is incorpora
The is_connected flag is set to true after DP mainlink successfully
finish link training. Replace the is_connected flag with link_ready
flag to avoid confusing.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display.c | 19 +--
drivers/gpu/drm/msm/dp/dp_display.h | 2
Currently the dp_display_irq_handler() is executed at msm_dp_modeset_init()
which ties irq registration to the DPU device's life cycle, while depending on
resources that are released as the DP device is torn down. Move register DP
driver irq handler at dp_display_probe() to have dp_display_irq_hand
On 9/11/2023 2:02 AM, John Watts wrote:
Panel initialization registers are per-display and not tied to the
controller itself. Different panels will specify their own registers.
Attach the sequences to the panel info struct so future panels
can specify their own sequences.
Signed-off-by: John
Currently eDP population is done at msm_dp_modeset_init() which happen
at binding time. Move eDP population to be done at display probe time
so that probe deferral cases can be handled effectively.
wait_for_hpd_asserted callback is added during drm_dp_aux_init()
to ensure eDP's HPD is up before pro
Add pm_runtime_force_suspend()/resume() to complete incorporating pm
runtime framework into DP driver. Both dp_pm_prepare() and dp_pm_complete()
are added to set hpd_state to correct state. After resume, DP driver will
re training its main link after .hpd_enable() callback enabled HPD
interrupts an
Currently DP driver use drm_helper_hpd_irq_event(), bypassing drm bridge
framework, to report HPD status changes to user space frame work.
Replace it with drm_bridge_hpd_notify() since DP driver is part of drm
bridge.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display.c | 20 ++---
EV_HPD_INIT_SETUP flag is used to trigger the initialization of external
DP host controller. Since external DP host controller initialization had
been incorporated into pm_runtime_resume(), this flag become obsolete.
Lets get rid of it.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dp
Currently the dp_display_irq_handler() is executed at msm_dp_modeset_init()
which ties irq registration to the DPU device's life cycle, while depending on
resources that are released as the DP device is torn down. Move register DP
driver irq handler at dp_display_probe() to have dp_display_irq_hand
Currently DP driver is executed independent of PM runtime framework.
This lead DP driver incompatible with others. Incorporating pm runtime
framework into DP driver so that both power and clocks to enable/disable
host controller fits with PM runtime mechanism. Once pm runtime framework
is incorpora
The is_connected flag is set to true after DP mainlink successfully
finish link training. Replace the is_connected flag with link_ready
flag to avoid confusing.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display.c | 19 +--
drivers/gpu/drm/msm/dp/dp_display.h | 2
Incorporate pm runtime framework into DP driver and clean up eDP
by moving of_dp_aux_populate_bus() to probe()
Kuogee Hsieh (7):
drm/msm/dp: tie dp_display_irq_handler() with dp driver
drm/msm/dp: replace is_connected with link_ready
drm/msm/dp: use drm_bridge_hpd_notify() to report HPD stat
dsi_wait4video_done() API waits for the DSI video mode engine to
become idle so that we can transmit the DCS commands in the
beginning of BLLP. However, with the current sequence, the MDP
timing engine is turned on after the panel's pre_enable() callback
which can send out the DCS commands needed t
The pull request you sent on Fri, 15 Sep 2023 12:57:50 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2023-09-15
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/9608c7b729e29c177525006711966ae0fd399b11
Thank you!
--
Deet-doot-dot, I am a bot.
https://k
On Fri, 2023-09-15 at 13:15 -0700, Teres Alexis, Alan Previn wrote:
> Debugging PXP issues can't even begin without understanding precedding
> sequence of important events. Add drm_dbg into the most important PXP events.
>
> v3 : - move gt_dbg to after mutex block in function
> i915_gsc_p
Debugging PXP issues can't even begin without understanding precedding
sequence of important events. Add drm_dbg into the most important PXP events.
v3 : - move gt_dbg to after mutex block in function
i915_gsc_proxy_component_bind. (Vivaik)
v2 : - remove __func__ since drm_dbg covers tha
Thanks for catching all of this! for the whole series:
Reviewed-by: Lyude Paul
On Thu, 2023-09-14 at 01:32 +0300, Imre Deak wrote:
> Fix the NULL dereference leading to the following stack trace:
>
> [ 129.687181] i915 :00:02.0: [drm:drm_dp_add_payload_part1
> [drm_display_helper]] VCPI
On Fri, 15 Sept 2023 at 21:30, Abhinav Kumar wrote:
>
> dsi_wait4video_done() API wait for the DSI video mode engine to
> become idle so that we can transmit the DCS commands in the
> beginning of BLLP. However, with the current sequence, the MDP
> timing engine is turned on after the panel's pre_
On 9/15/23 12:52, Kees Cook wrote:
On Fri, Sep 15, 2023 at 12:43:20PM -0600, Gustavo A. R. Silva wrote:
If, for any reason, the open-coded arithmetic causes a wraparound, the
protection that `struct_size()` adds against potential integer overflows
is defeated. Fix this by hardening call to `s
On Fri, Sep 15, 2023 at 12:43:20PM -0600, Gustavo A. R. Silva wrote:
> If, for any reason, the open-coded arithmetic causes a wraparound, the
> protection that `struct_size()` adds against potential integer overflows
> is defeated. Fix this by hardening call to `struct_size()` with `size_add()`.
>
If, for any reason, the open-coded arithmetic causes a wraparound, the
protection that `struct_size()` adds against potential integer overflows
is defeated. Fix this by hardening call to `struct_size()` with `size_add()`.
Fixes: 40e1a70b4aed ("drm: Add GUD USB Display driver")
Signed-off-by: Gusta
Hi,
On 9/8/23 10:44, Joonas Lahtinen wrote:
Quoting Thomas Hellström (2023-08-22 19:21:32)
This series adds a flag at VM_BIND time to pin the memory backing a VMA.
Initially this is needed for long-running workloads on hardware that
neither support mid-thread preemption nor pagefaults, since wi
dsi_wait4video_done() API wait for the DSI video mode engine to
become idle so that we can transmit the DCS commands in the
beginning of BLLP. However, with the current sequence, the MDP
timing engine is turned on after the panel's pre_enable() callback
which can send out the DCS commands needed to
Update the GSC-fw input/output HECI packet size to match
updated internal fw specs.
Signed-off-by: Alan Previn
Reviewed-by: Vivaik Balasubrawmanian
---
drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
For MTL, update the GSC-HECI packet size and the max firmware
response timeout to match internal fw specs. Enforce setting
run-alone bit in LRC for protected contexts.
Changes from prio revs:
v5: - PAGE_ALIGN typo fix (Alan).
- Use macro for runalone bit (Vivaik)
- Spec alignment
On Meteorlake onwards, HW specs require that all user contexts that
run on render or compute engines and require PXP must enforce
run-alone bit in lrc. Add this enforcement for protected contexts.
Signed-off-by: Alan Previn
Reviewed-by: Vivaik Balasubrawmanian
---
drivers/gpu/drm/i915/gt/intel_
Update the max GSC-fw response time to match updated internal
fw specs. Because this response time is an SLA on the firmware,
not inclusive of i915->GuC->HW handoff latency, when submitting
requests to the GSC fw via intel_gsc_uc_heci_cmd_submit helpers,
start the count after the request hits the G
For MTL, update the GSC-HECI packet size and the max firmware
response timeout to match internal fw specs. Enforce setting
run-alone bit in LRC for protected contexts.
Changes from prio revs:
v5: - PAGE_ALIGN typo fix (Alan).
- Use macro for runalone bit (Vivaik)
- Spec alignment
syzbot has bisected this issue to:
commit 5c074eeabbd332b11559f7fc1e89d456f94801fb
Author: Gerd Hoffmann
Date: Wed Nov 14 12:20:29 2018 +
udmabuf: set read/write flag when exporting
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=12b21bbfa8
start commit: db906f0ca6b
On 9/12/2023 3:59 AM, Ruihai Zhou wrote:
The sta_himax83102 panel sometimes shows abnormally flickering
horizontal lines. The front gate output will precharge the X point of
the next pole circuit before TP(TouchPanel Enable) term starts, and wait
until the end of the TP term to resume the CLK.
On 2023-09-14 17:12, Hamza Mahfooz wrote:
>
> On 9/14/23 17:04, Hamza Mahfooz wrote:
>>
>> On 9/14/23 16:40, Harry Wentland wrote:
>>> On 2023-09-14 13:53, Hamza Mahfooz wrote:
On eDP we can receive invalid modes from dm_update_crtc_state() for
entirely new streams for which drm_mode_
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> On Meteorlake onwards, HW specs require that all user contexts that
> run on render or compute engines and require PXP must enforce
> run-alone bit in lrc. Add this enforcement for protected contexts.
alan:snip
>
> Signed-off-by
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the GSC-fw input/output HECI packet size to match
> updated internal fw specs.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
> 1 file changed, 2 insertions(+), 2
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the max GSC-fw response time to match updated internal
> fw specs. Because this response time is an SLA on the firmware,
> not inclusive of i915->GuC->HW handoff latency, when submitting
> requests to the GSC fw via intel_
Reviewed-by: Lyude Paul
Will push this and your other patches in just a moment
On Thu, 2023-09-14 at 21:30 +, Justin Stitt wrote:
> `strncpy` is deprecated and as such we should prefer more robust and
> less ambiguous string interfaces.
>
> A suitable replacement is `strscpy_pad` due to the
...oops, responded to the wrong email :P
Reviewed-by: Lyude Paul
On Thu, 2023-09-14 at 22:17 +, Justin Stitt wrote:
> `strncpy` is deprecated for use on NUL-terminated destination strings [1].
>
> We should prefer more robust and less ambiguous string interfaces.
>
> A suitable replacemen
Eek, I didn't realize how many instances of this we had. Thanks for doing this
:)
Reviewed-by: Lyude Paul
On Thu, 2023-09-14 at 21:40 +, Justin Stitt wrote:
> `strncpy` is deprecated for use on NUL-terminated destination strings [1].
>
> We should prefer more robust and less ambiguous strin
Nice catch!
Reviewed-by: Lyude Paul
Will push in just a moment
On Thu, 2023-09-14 at 21:59 -0700, Kees Cook wrote:
> On Thu, Sep 14, 2023 at 10:17:08PM +, Justin Stitt wrote:
> > `strncpy` is deprecated for use on NUL-terminated destination strings [1].
> >
> > We should prefer more robust
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the max GSC-fw response time to match updated internal
> fw specs. Because this response time is an SLA on the firmware,
> not inclusive of i915->GuC->HW handoff latency, when submitting
> requests to the GSC fw via intel_
On Sat, 2023-09-09 at 15:38 -0700, Teres Alexis, Alan Previn wrote:
> Update the GSC-fw input/output HECI packet size to match
> updated internal fw specs.
>
> Signed-off-by: Alan Previn
>
alan:snip
> -/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
> -#define PXP43_MAX_HECI_INOUT_SIZE
[AMD Official Use Only - General]
Pushed the rest of the patches in the series to amd-staging-drm-next.
Regards
Shashank
-Original Message-
From: Koenig, Christian
Sent: Monday, September 11, 2023 1:15 PM
To: André Almeida ; dri-devel@lists.freedesktop.org;
amd-...@lists.freedesktop.org
On Fri, Sep 15, 2023 at 04:05:15PM +0200, Flavio Suligoi wrote:
> The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
> programmable switching frequency to optimize efficiency.
> The brightness can be controlled either by I2C commands (called "analog"
> mode) or by a PWM inp
Yo,
On Fri, Sep 15, 2023 at 04:05:15PM +0200, Flavio Suligoi wrote:
> The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
> programmable switching frequency to optimize efficiency.
> The brightness can be controlled either by I2C commands (called "analog"
> mode) or by a PW
On Fri, 15 Sep 2023, Robert Foss wrote:
> On Fri, Sep 15, 2023 at 12:31 PM Neil Armstrong
> wrote:
>>
>> On 14/09/2023 15:19, Jani Nikula wrote:
>> > Clearly this should be under bridge chips.
>> >
>> > Cc: Andrzej Hajda
>> > Cc: Neil Armstrong
>> > Cc: Robert Foss
>> > Signed-off-by: Jani Nik
On 9/1/2023 10:12 AM, Jeffrey Hugo wrote:
From: Pranjal Ramajor Asha Kanojiya
Since drm_dev_alloc() is deprecated it is recommended to use
devm_drm_dev_alloc() instead. Update the driver to start using
devm_drm_dev_alloc().
Signed-off-by: Pranjal Ramajor Asha Kanojiya
Reviewed-by: Carl Vander
On 9/4/2023 3:28 AM, Stanislaw Gruszka wrote:
On Fri, Sep 01, 2023 at 10:12:36AM -0600, Jeffrey Hugo wrote:
From: Pranjal Ramajor Asha Kanojiya
Since drm_dev_alloc() is deprecated it is recommended to use
devm_drm_dev_alloc() instead. Update the driver to start using
devm_drm_dev_alloc().
Sig
On Fri, 15 Sep 2023 16:05:15 +0200, Flavio Suligoi wrote:
> The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
> programmable switching frequency to optimize efficiency.
> The brightness can be controlled either by I2C commands (called "analog"
> mode) or by a PWM input s
On 9/1/2023 10:10 AM, Jeffrey Hugo wrote:
From: Pranjal Ramajor Asha Kanojiya
As qaic drivers base device is connected to host via PCI framework, it
makes sense to register in PCI framework at the beginning of module
init.
Signed-off-by: Pranjal Ramajor Asha Kanojiya
Reviewed-by: Carl Vanderl
On Fri, 15 Sep 2023, Harry Wentland wrote:
> On 2023-09-05 13:13, Alex Hung wrote:
>> [WHY]
>> edid_override and drm_edid_override_connector_update, according to drm
>> documentation, should not be referred outside drm_edid.
>>
>> [HOW]
>> Remove and replace them accordingly.
>>
>> Signed-off-by
Hey,
On Thu, 14 Sept 2023 at 10:54, Maxime Ripard wrote:
> On Tue, Sep 12, 2023 at 02:16:41PM +0100, Daniel Stone wrote:
> > Hopefully less mangled formatting this time: turns out Thunderbird +
> > plain text is utterly unreadable, so that's one less MUA that is
> > actually usable to send email
On 9/15/23 11:17, Janusz Krzysztofik wrote:
Hi Maíra,
Thanks for review.
On Friday, 15 September 2023 16:01:31 CEST Maira Canal wrote:
Hi,
On 9/11/23 10:03, Janusz Krzysztofik wrote:
While drm_mm test was converted form igt selftest to kunit, unexpected
value of "end" argument equal "start"
Hi Maíra,
Thanks for review.
On Friday, 15 September 2023 16:01:31 CEST Maira Canal wrote:
> Hi,
>
> On 9/11/23 10:03, Janusz Krzysztofik wrote:
> > While drm_mm test was converted form igt selftest to kunit, unexpected
> > value of "end" argument equal "start" was introduced to one of calls to
Hi,
On 2023/9/15 21:44, Doug Anderson wrote:
Hi,
On Fri, Sep 15, 2023 at 2:11 AM suijingfeng wrote:
Hi,
On 2023/9/2 07:39, Douglas Anderson wrote:
Based on grepping through the source code these drivers appear to be
missing a call to drm_atomic_helper_shutdown() at system shutdown
time. A
Hi,
On 9/11/23 10:03, Janusz Krzysztofik wrote:
While drm_mm test was converted form igt selftest to kunit, unexpected
value of "end" argument equal "start" was introduced to one of calls to a
function that executes the drm_test_mm_insert_range for specific start/end
pair of arguments. As a con
On 2023-09-05 13:13, Alex Hung wrote:
> [WHY]
> edid_override and drm_edid_override_connector_update, according to drm
> documentation, should not be referred outside drm_edid.
>
> [HOW]
> Remove and replace them accordingly.
>
> Signed-off-by: Alex Hung
> ---
> .../gpu/drm/amd/display/amdgp
Hi,
On Fri, Sep 15, 2023 at 2:11 AM suijingfeng wrote:
>
> Hi,
>
>
> On 2023/9/2 07:39, Douglas Anderson wrote:
> > Based on grepping through the source code these drivers appear to be
> > missing a call to drm_atomic_helper_shutdown() at system shutdown
> > time. Among other things, this means t
On 15.09.2023 14:59, Dan Carpenter wrote:
> The irq_of_parse_and_map() function returns zero on error. It
> never returns negative error codes. Fix the check.
>
> Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
> Signed-off-by: Dan Carpenter
> ---
Reviewed-by: Konrad Dybcio
The irq_of_parse_and_map() function returns zero on error. It
never returns negative error codes. Fix the check.
Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +++
1 file changed, 3 insertions(+),
The u_memcpya() function is supposed to return error pointers on
error. Returning NULL will lead to an Oops.
Fixes: 68132cc6d1bc ("nouveau/u_memcpya: use vmemdup_user")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Dmitry,
On Mon, Sep 04, 2023 at 12:41:50AM +0300, Dmitry Baryshkov wrote:
> In order to notify the userspace about the DRM connector's USB-C port,
> export the corresponding port's name as the bridge's path field.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/usb/typec/tcpm/qcom/qcom_p
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is als
Don't assume that only the driver would be accessing LNKCTL2. In the
case of upstream (parent), the driver does not even own the device it's
changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value. This change is als
On Fri, Sep 15, 2023 at 12:31 PM Neil Armstrong
wrote:
>
> On 14/09/2023 15:19, Jani Nikula wrote:
> > Clearly this should be under bridge chips.
> >
> > Cc: Andrzej Hajda
> > Cc: Neil Armstrong
> > Cc: Robert Foss
> > Signed-off-by: Jani Nikula
> > ---
> > MAINTAINERS | 2 ++
> > 1 file ch
Hi Jani,
Le jeudi 14 septembre 2023 à 16:11 +0300, Jani Nikula a écrit :
> The drm stack does not expect error valued pointers for EDID
> anywhere.
>
> Fixes: e66856508746 ("drm: bridge: it66121: Set DDC preamble only
> once before reading EDID")
> Cc: Paul Cercueil
> Cc: Robert Foss
> Cc: Phon
This definition is used fro qemu, and qemu imports this marco in the
headers to enable venus for virtio gpu. So it should add it even kernel
doesn't use this.
Signed-off-by: Huang Rui
---
Hi all,
We would like to add a new definition for venus capset, it will be used for
qemu. Please see detail
Update the LCDC_HEOCFG30 and LCDC_HEOCFG31 registers of XLCDC IP which
supports vertical and horizontal scaling with Bilinear and Bicubic
co-efficients taps for Chroma and Luma componenets of the Pixel.
Signed-off-by: Manikandan Muralidharan
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2
Add support for the following DPI mode if the encoder type
is DSI as per the XLCDC IP datasheet:
- 16BPPCFG1
- 16BPPCFG2
- 16BPPCFG3
- 18BPPCFG1
- 18BPPCFG2
- 24BPP
Signed-off-by: Manikandan Muralidharan
[durai.manicka...@microchip.com: update output format using is_xlcdc flag]
Signed-off-by: Dur
Add support for Display Pixel Interface (DPI) Compatible Mode
support in atmel-hlcdc driver for XLCDC IP along with legacy
pixel mapping.DPI mode BIT is configured in LCDC_CFG5 register.
Signed-off-by: Manikandan Muralidharan
[durai.manicka...@microchip.com: update DPI mode bit using is_xlcdc fla
From: Durai Manickam KR
The register address of the XLCDC IP used in SAM9X7 SoC family
are different from the previous HLCDC.Defining those address
space with valid macros.
Signed-off-by: Durai Manickam KR
[manikanda...@microchip.com: Remove unused macro definitions]
Signed-off-by: Manikandan M
1 - 100 of 167 matches
Mail list logo
