On 27-07-2023 15:43, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In order to show per client memory usage lets add some infrastructure
> which enables tracking buffer objects owned by clients.
>
> We add a per client list protected by a new per client lock and to support
> delayed destru
On 27-07-2023 15:43, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Use the newly added drm_print_memory_stats helper to show memory
> utilisation of our objects in drm/driver specific fdinfo output.
>
> To collect the stats we walk the per memory regions object lists
> and accumulate objec
It is not possible for platform_get_irq() to return 0. Use the
return value from platform_get_irq().
Signed-off-by: Ruan Jinjie
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/med
Since commit a85a6c86c25b ("driver core: platform: Clarify that
IRQ 0 is invalid"), there is no possible both for platform_get_irq()
and platform_get_irq_byname() to return 0.
And the return value of platform_get_irq() or platform_get_irq_byname()
is more sensible to show the error reason.
Chan
It is not possible for platform_get_irq_byname() to return 0.
Use the return value from platform_get_irq_byname().
Signed-off-by: Ruan Jinjie
---
drivers/gpu/drm/panfrost/panfrost_gpu.c | 4 ++--
drivers/gpu/drm/panfrost/panfrost_job.c | 4 ++--
drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++--
It is not possible for platform_get_irq_byname() to return 0.
Use the return value from platform_get_irq_byname().
Signed-off-by: Ruan Jinjie
---
drivers/gpu/drm/panfrost/panfrost_gpu.c | 4 ++--
drivers/gpu/drm/panfrost/panfrost_job.c | 4 ++--
drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++--
It is not possible for platform_get_irq() to return 0. Use the
return value from platform_get_irq().
Signed-off-by: Ruan Jinjie
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/med
Since commit a85a6c86c25be ("driver core: platform: Clarify that
IRQ 0 is invalid)", there is no possible both for platform_get_irq()
and platform_get_irq_byname() to return 0,
And the return value of platform_get_irq() or platform_get_irq_byname()
is more sensible to show the error reason.
Rua
On Wed, 2023-08-02 at 16:34 -0700, Teres Alexis, Alan Previn wrote:
> This series is the result of debugging issues root caused to
> races between the GuC's destroyed_worker_func being triggered vs
> repeating suspend-resume cycles with concurrent delayed
> fence signals for engine-freeing.
>
> Th
When suspending, add a timeout when calling
intel_gt_pm_wait_for_idle else if we have a lost
G2H event that holds a wakeref (which would be
indicating of a bug elsewhere in the driver), we
get to complete the suspend-resume cycle, albeit
without all the lower power hw counters hitting
its targets,
If we are at the end of suspend or very early in resume
its possible an async fence signal could lead us to the
execution of the context destruction worker (after the
prior worker flush).
Even if checking that the CT is enabled before calling
destroyed_worker_func, guc_lrc_desc_unpin may still fai
Suspend is not like reset, it can unroll, so we have to properly
flush pending context-guc-id deregistrations to complete before
we return from suspend calls.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submiss
This series is the result of debugging issues root caused to
races between the GuC's destroyed_worker_func being triggered vs
repeating suspend-resume cycles with concurrent delayed
fence signals for engine-freeing.
The reproduction steps require that an app is created right before
the start of th
From: Rob Clark
This was not strictly necessary, as page unpinning (ie. shrinker) only
cares about the resv. It did give us some extra sanity checking for
userspace controlled iova, and was useful to catch issues on kernel and
userspace side when enabling userspace iova. But if userspace screws
From: Rob Clark
Split out pin_count incrementing and lru updating into a separate loop
so we can take the lru lock only once for all objs. Since we are still
holding the obj lock, it is safe to split this up.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 45 +
From: Rob Clark
Basically everywhere wants the base ptr type. So store that instead of
msm_gem_object.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++--
drivers/gpu/drm/msm/msm_gem.h | 2 +-
drivers/gpu/drm/msm/msm_gem_submit.c | 42 +-
From: Rob Clark
I recently wrote myself a submitoverhead igt test[1] and spent a bit of
time profiling. The end result ranges from 1.6x faster for
NO_IMPLICIT_SYNC commits with 100 BOs to 2.5x faster for 1000 BOs.
[1] https://patchwork.freedesktop.org/series/121909/
Rob Clark (4):
drm/msm: T
From: Rob Clark
Rather than acquiring it and dropping it for each individual obj.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 3 ---
drivers/gpu/drm/msm/msm_ringbuffer.c | 5 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_ge
From: Rob Clark
Mesa stopped using these pretty early in a6xx bringup. Take advantage
of this to disallow some legacy UABI.
Signed-off-by: Rob Clark
---
So, it was late 2018 when mesa stopped using relocs. At that point a6xx
support was still in a pretty early state. I guess you _could_ use
On Wed, Aug 2, 2023 at 1:44 AM Boris Brezillon
wrote:
>
> On Tue, 1 Aug 2023 13:35:13 -0700
> Nick Desaulniers wrote:
>
> > On Mon, Jul 31, 2023 at 5:36 AM Christian König
> > wrote:
> > >
> > > GCC forbids to jump to labels in loop conditions and a new clang
> > > check stumbled over this.
> >
On 8/2/2023 12:46 PM, Marijn Suijten wrote:
On 2023-08-02 21:36:55, Dmitry Baryshkov wrote:
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
0x100, while the actual length is 0x9c (last register having offset 0x98).
Reduce subblock length to remove the empty register s
Thomas, Jocelyn,
I just thought I'd let you know that it occurred to me that, now I
understood the workings of the mgag200 module better, I might be
able to get an even higher screen resolution than before.
So I relaxed the limits of this chip that returns unique_rev_id=1 to be
those that would
On 2023-08-02 21:36:54, Dmitry Baryshkov wrote:
> All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
> This includes the common block itself, enc subblocks and some empty
> space around. Change that to pass 0x4 instead, the length of common
> register block itself.
>
> Fixes:
On 2023-08-02 21:36:55, Dmitry Baryshkov wrote:
> Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
> 0x100, while the actual length is 0x9c (last register having offset 0x98).
> Reduce subblock length to remove the empty register space from being
> dumped.
>
> Fixes: 0d1b10
On 2023-08-02 11:08:49, Jessica Zhang wrote:
> DPU supports a data-bus widen mode for DSI INTF.
>
> Enable this mode for all supported chipsets if widebus is enabled for DSI.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
> driver
I find this title very undescriptive, it doesn't really explain from/to
where this move is happening nor why.
On 2023-08-02 11:08:48, Jessica Zhang wrote:
> Move the setting of dpu_enc.wide_bus_en to
> dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
> dpu_enc.dsc.
mirroring "th
2 августа 2023 г. 22:13:51 GMT+03:00, Laurent Pinchart
пишет:
>On Wed, Aug 02, 2023 at 10:01:19PM +0300, Dmitry Baryshkov wrote:
>> On 02/08/2023 21:55, Laurent Pinchart wrote:
>> > Hi Dmitry,
>> >
>> > Thank you for the patch.
>> >
>> > On Sat, Jul 29, 2023 at 03:49:12AM +0300, Dmitry Baryshko
On Wed, Aug 02, 2023 at 10:01:19PM +0300, Dmitry Baryshkov wrote:
> On 02/08/2023 21:55, Laurent Pinchart wrote:
> > Hi Dmitry,
> >
> > Thank you for the patch.
> >
> > On Sat, Jul 29, 2023 at 03:49:12AM +0300, Dmitry Baryshkov wrote:
> >> To properly define the USB-C DP altmode connectors, add t
ies
> >>>> since 5.10, breaking them doesn't seem more acceptable than breaking the
> >>>> new out-of-tree iMX8m hardware.
> >>>
> >>> The MX8M is also in-tree, so this does not apply.
> >>
> >> v6.5-rc4:
> >>
> &
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when calling intel_pxp_init_hw
from within intel_
On 02/08/2023 21:54, Laurent Pinchart wrote:
Hi Dmitry,
Thank you for the patch.
On Sat, Jul 29, 2023 at 03:49:10AM +0300, Dmitry Baryshkov wrote:
In the embedded usecases the default subtype depends on the bridge
chain, so it is easier to specify the subtype at the proprety attachment
s/pro
On 02/08/2023 21:55, Laurent Pinchart wrote:
Hi Dmitry,
Thank you for the patch.
On Sat, Jul 29, 2023 at 03:49:12AM +0300, Dmitry Baryshkov wrote:
To properly define the USB-C DP altmode connectors, add the USB
subconnector type.
Suggested-by: Simon Ser
Signed-off-by: Dmitry Baryshkov
---
Hi Dmitry,
Thank you for the patch.
On Sat, Jul 29, 2023 at 03:49:12AM +0300, Dmitry Baryshkov wrote:
> To properly define the USB-C DP altmode connectors, add the USB
> subconnector type.
>
> Suggested-by: Simon Ser
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/drm_connector.c |
Hi Dmitry,
Thank you for the patch.
On Sat, Jul 29, 2023 at 03:49:10AM +0300, Dmitry Baryshkov wrote:
> In the embedded usecases the default subtype depends on the bridge
> chain, so it is easier to specify the subtype at the proprety attachment
s/proprety/property/
> type rather than specifyin
On 02/08/2023 21:46, Laurent Pinchart wrote:
On Wed, Aug 02, 2023 at 12:05:50PM +0300, Dmitry Baryshkov wrote:
On Wed, 2 Aug 2023 at 11:35, Neil Armstrong wrote:
On 29/07/2023 02:49, Dmitry Baryshkov wrote:
If the created connector type supports subconnector type property,
create and attach co
b845c.dts: compatible =
"lontium,lt9611";
drivers/gpu/drm/bridge/lontium-lt9611.c: { "lontium,lt9611", 0 },
drivers/gpu/drm/bridge/lontium-lt9611.c: { .compatible =
"lontium,lt9611" },
next-20230802:
$ git grep lontium,lt9611 | grep -v 9611uxc
Documentation/devicetree/
lt9611.yaml:$id:
> http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
> Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml:
> - lontium,lt9611
> Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml:
> compatible = "lonti
From: John Harrison
It was noticed that if the very first 'stealing' request failed to
create for some reason then the 'steal all ids' loop would immediately
exit with 'last' still being NULL. The test would attempt to continue
but using a null pointer. Fix that by aborting the test if it fails t
On 8/2/23 19:49, Abhinav Kumar wrote:
Hi Marek
On 8/2/2023 10:25 AM, Marek Vasut wrote:
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wr
On Wed, Aug 02, 2023 at 12:05:50PM +0300, Dmitry Baryshkov wrote:
> On Wed, 2 Aug 2023 at 11:35, Neil Armstrong wrote:
> > On 29/07/2023 02:49, Dmitry Baryshkov wrote:
> > > If the created connector type supports subconnector type property,
> > > create and attach corresponding it. The default subt
rivers/gpu/drm/bridge/lontium-lt9611.c: { "lontium,lt9611", 0 },
drivers/gpu/drm/bridge/lontium-lt9611.c: { .compatible = "lontium,lt9611" },
next-20230802:
$ git grep lontium,lt9611 | grep -v 9611uxc
Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml
On Wed, 2 Aug 2023 at 21:36, Dmitry Baryshkov
wrote:
>
> All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
> This includes the common block itself, enc subblocks and some empty
> space around. Change that to pass 0x4 instead, the length of common
> register block itself.
>
>
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
0x100, while the actual length is 0x9c (last register having offset 0x98).
Reduce subblock length to remove the empty register space from being
dumped.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chi
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relev
> >
> >
alan:snip
Thanks Vinay and Daniele - i'll respin with below fix.
> > @@ -48,7 +50,8 @@ void intel_pxp_resume_complete()
> > if (!HAS_ENGINE(pxp->ctrl_gt, GSC0) && !pxp->pxp_component)
> > return;
> >
> > - intel_pxp_init_hw(pxp);
> > + with_intel_runtime_pm(&pxp-
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable
> databus widen mode.
Reviewed-by: Dmitry Baryshkov
(The patch will probably be replaced by Rob syncing up msm headers).
>
> Signed-off-by: Jessica Zhang
> ---
> dri
After recent discussions with Mesa folks, it was requested
that we optimize i915's GET_PARAM for the PXP_STATUS without
changing the UAPI spec.
Add these additional optimizations:
- If any PXP initializatoin flow failed, then ensure that
we catch it so that we can change the returned PXP_S
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data instead of 24.
>
> Enable this mode whenever DSC is enabled for supported chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/ms
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> Move the setting of dpu_enc.wide_bus_en to
> dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
> dpu_enc.dsc.
because ... ?
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++--
On Wed, 2 Aug 2023 at 21:09, Jessica Zhang wrote:
>
> DPU supports a data-bus widen mode for DSI INTF.
>
> Enable this mode for all supported chipsets if widebus is enabled for DSI.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
>
splay/bridge/lontium,lt9611.yaml:$id:
http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml:
- lontium,lt9611
Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml:
compatible = "lontium,lt9
On Wed, 2 Aug 2023 at 20:34, Marek Vasut wrote:
>
> On 8/2/23 14:37, Neil Armstrong wrote:
> > On 02/08/2023 14:28, Marek Vasut wrote:
> >> On 8/2/23 14:07, Marek Vasut wrote:
> >>> On 8/2/23 10:52, Neil Armstrong wrote:
> This reverts commit [1] to fix display regression on the Dragonboard
>
Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable
databus widen mode.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index a4a1546
DSI 6G v2.5.x+ and DPU support a data-bus widen mode that allows DSI
to send 48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommended by the hardware programming guide.
Only enable this for command mode as we are
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data instead of 24.
Enable this mode whenever DSC is enabled for supported chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi.c | 5 +
drivers/gpu/drm/msm/dsi/dsi.h |
Move the setting of dpu_enc.wide_bus_en to
dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
dpu_enc.dsc.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/
DPU supports a data-bus widen mode for DSI INTF.
Enable this mode for all supported chipsets if widebus is enabled for DSI.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +++-
dri
On Wed, 2 Aug 2023 at 18:26, Chris Morgan wrote:
>
> * Spam *
> On Mon, Jul 31, 2023 at 07:03:07PM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Mon, Jul 31, 2023 at 11:33:22AM -0500, Chris Morgan wrote:
> > > In my case a few different panel drivers disable the regulators in the
> > > unprepare/
Hi Marek
On 8/2/2023 10:25 AM, Marek Vasut wrote:
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP me
In the bug reported by Syzbot, the variable `den == (1 << 22)` and
`mode->vscan == (1 << 10)`, causing the multiplication to overflow and
accidentally make `den == 0`. To prevent any chance of overflow, we
replace `num` and `den` with 64-bit unsigned integers, and explicitly
check if the divisor `d
On 8/2/23 14:37, Neil Armstrong wrote:
On 02/08/2023 14:28, Marek Vasut wrote:
On 8/2/23 14:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard
845c
(SDM845) devboard.
There's a mismatch on the real action of the
On 8/2/23 15:38, Dmitry Baryshkov wrote:
On 02/08/2023 11:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard 845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags:
- MIPI_DSI_MODE_VIDEO_NO_HSA
- MIPI_DSI_MODE_VIDEO_NO_HF
On 8/2/23 15:16, Dmitry Baryshkov wrote:
On 02/08/2023 15:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard
845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags:
- MIPI_DSI_MODE_VI
On 8/2/23 14:38, Dmitry Baryshkov wrote:
On 02/08/2023 15:07, Marek Vasut wrote:
On 8/2/23 10:52, Neil Armstrong wrote:
This reverts commit [1] to fix display regression on the Dragonboard
845c
(SDM845) devboard.
There's a mismatch on the real action of the following flags:
- MIPI_DSI_MODE_VI
On Mon, Jul 31, 2023 at 07:03:07PM +0200, Maxime Ripard wrote:
> Hi,
>
> On Mon, Jul 31, 2023 at 11:33:22AM -0500, Chris Morgan wrote:
> > In my case a few different panel drivers disable the regulators in the
> > unprepare/disable routines.
>
> And that's totally fine.
>
> > For at least the Ro
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP means the HBP period is just skipped by
DSIM.
Maybe
On 7/31/2023 10:12 AM, Stanislaw Gruszka wrote:
Add DRM_IVPU_PARAM_CAPABILITIES ioctl to query driver capabilities.
For now use it for identify metric streamer and new dma memory range
features. Currently upstream version of intel_vpu does not have those,
they will be added it the future.
Hmm.
Drop vsync_event and vsync_event_work handlers as they are unnecessary.
In addition drop the dpu_enc_ktime_template event class as it will be
unused after the vsync_event handlers are dropped.
Signed-off-by: Jessica Zhang
---
Changes in v2:
- Dropped dpu_enc_early_kickoff event and dpu_enc_ktime_
On 7/31/2023 10:12 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
Use VPU IP generation for naming FW instead of the platform name.
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 7/31/2023 10:12 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
Given that VPU generation can be used by multiple platforms, driver should
use VPU IP generation names instead of a platform names.
Change naming for functions and registries.
Use 37XX format, where:
3 - major VPU IP g
On 7/31/2023 10:12 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
Given that VPU generation can be used by multiple platforms, driver should
use VPU IP generation in names instead of a platform names.
I think just "platform." instead of "platform names" reads better.
Change naming fo
On Wed, Aug 02, 2023 at 02:52:57PM +, Jiaxin Yu (俞家鑫) wrote:
> On Mon, 2023-07-31 at 12:50 +0100, Mark Brown wrote:
> > On Mon, Jul 31, 2023 at 02:08:02AM +0800, Jiaxin Yu wrote:
> > > Use SND_SOC_DAPM_LINE instead of SND_SOC_DAPM_OUTPUT to trigger
> > > DAPM events to hdmi-codec when userspac
On 7/13/23 2:27 PM, Greg Kroah-Hartman wrote:
On Thu, Jul 13, 2023 at 02:13:16PM -0500, Andrew Davis wrote:
+int sram_add_dma_heap(struct sram_dev *sram,
+ struct sram_reserve *block,
+ phys_addr_t start,
+ struct sram_partition *part)
Hi Ran,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on linus/master v6.5-rc4 next-20230802]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
Thanks. Change is merged to amd-staging-drm-next.
Harry
On 2023-08-01 00:07, Alex Hung wrote:
> Tested-by: Alex Hung
>
> On 2023-07-31 02:35, Melissa Wen wrote:
>> Don't set predefined degamma curve to cursor plane if the cursor
>> attribute flag is not set. Applying a degamma curve to the curs
On 8/1/2023 8:05 AM, Pranjal Ramajor Asha Kanojiya wrote:
On 7/26/2023 7:36 PM, Colin Ian King wrote:
Pointer pexec is being assigned a value however it is never read. The
assignment is redundant and can be removed. Replace sizeof(*pexec)
with sizeof the type and remove the declaration of poin
On Wed, Aug 02, 2023 at 08:07:55PM +0530, Jagan Teki wrote:
> On Wed, 2 Aug 2023 at 02:37, Conor Dooley wrote:
> >
> > On Mon, Jul 31, 2023 at 04:30:03PM +0530, Jagan Teki wrote:
> > > Document the VOP for Rockchip RV1126.
> > >
> > > Signed-off-by: Jagan Teki
> >
> > There's no commentary here a
Hi all,
In order to avoid spamming the list, I sparked a discussion in
#dri-devel. FTR the log can be found here:
https://oftc.irclog.whitequark.org/dri-devel/2023-08-02#32360491;
On 8/2/23 14:47, Maxime Ripard wrote:
> Hi,
>
> On Wed, Aug 02, 2023 at 02:34:28PM +0200, Michael Riesch wrote:
>> O
From: Pranjal Ramajor Asha Kanojiya
The temporary buffer storing slicing configuration data from user is only
freed on error. This is a memory leak. Free the buffer unconditionally.
Fixes: ff13be830333 ("accel/qaic: Add datapath")
Signed-off-by: Pranjal Ramajor Asha Kanojiya
Reviewed-by: Carl
Hi,
Le mardi 04 juillet 2023 à 09:51 +0800, Xiaoyong Lu a écrit :
> Fix av1 decode fail when iova is 36bit.
I'd change the subject to "media: mediatek: vcodec: fix AV1 decoding on MT8188"
And rephrase this one to:
Fix AV1 decoding failure when the iova is 36bit.
>
> Decoder hardware will acc
On Mon, 31 Jul 2023 at 04:01, André Almeida wrote:
>
> Em 13/07/2023 04:51, Pekka Paalanen escreveu:
> > On Tue, 11 Jul 2023 10:57:57 +0200
> > Daniel Vetter wrote:
> >
> >> On Fri, Jul 07, 2023 at 07:40:59PM -0300, André Almeida wrote:
> >>> From: Pekka Paalanen
> >>>
> >>> Specify how the atom
Hi,
On Tue, Aug 1, 2023 at 9:21 PM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (htmldocs)
> produced this warning:
>
> include/drm/drm_panel.h:270: warning: Function parameter or member
> 'follower_lock' not described in 'drm_panel'
>
> Intro
Hi,
On Tue, Aug 1, 2023 at 9:17 PM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (htmldocs)
> produced this warning:
>
> Documentation/gpu/todo.rst:469: ERROR: Unexpected indentation.
>
> Introduced by commit
>
> d2aacaf07395 ("drm/panel: Chec
1. Add encoder_index function to mtk_ddp_comp_funcs to support dynamic
connector selection for some ddp_comp who has encoder_index.
2. Add mtk_ddp_comp_encoder_index_set function to set encoder_index to
each comp.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 ++
Add mtk_drm_crtc_path enum for eatch display path.
Instead of using array index of all_drm_priv in mtk_drm_kms_init(),
mtk_drm_crtc_path enum can make more readable.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +++---
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 +++
Add DSI as a main display output selection on MT8188 VDOSYS0.
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/
Add implementation of mtk_dpi_encoder_index to mtk_ddp_comp_func
to make mtk_dpi support dynamic connector selection.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +
drivers/gpu/drm/mediatek/mtk_drm_ddp
To support DSI and eDP as main display connector without modifying
mtk-drm driver, we add the dynamic connector selection mechanism.
Change in v8:
1. add mtk_drm_crtc_path enum to replace array index of all_drm_priv.
2. separate add encoder_index function to another patch.
3. separate add dpi and
Add missing mmsys_dev_num to mt8188 vdosys0 driver data.
Fixes: 54b48080278a ("drm/mediatek: Add mediatek-drm of vdosys0 support for
mt8188")
Signed-off-by: Jason-JH.Lin
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
1 file change
In mtk_drm_kms_init(), each element in all_drm_priv should has one
display path private data only, such as:
all_drm_priv[CRTC_MAIN] should has main_path data only
all_drm_priv[CRTC_EXT] should has ext_path data only
all_drm_priv[CRTC_THIRD] should has third_path data only
So we need to add the len
Add implementation of mtk_dsi_encoder_index to mtk_ddp_comp_func
to make mtk_dsi support dynamic connector selection.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_dsi.c
1. Move output drm connector from each ddp_path array to connector array.
2. Add dynamic select available connector flow in crtc create and enable.
Signed-off-by: Nancy Lin
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 81 +++
In commit d2aacaf07395 ("drm/panel: Check for already prepared/enabled
in drm_panel") the formatting for a code block was not quite
right. This caused an error when building htmldocs:
Documentation/gpu/todo.rst:469: ERROR: Unexpected indentation.
Fix the error by using the proper syntax for a c
In the kernel doc for the `follower_lock` member of `struct drm_panel`
there was a typo where it was called `followers_lock`. This resulted
in a warning when making "htmldocs":
./include/drm/drm_panel.h:270: warning:
Function parameter or member 'follower_lock' not described in 'drm_panel'
Fi
Laurent Pinchart writes:
> I haven't seen anything either. I tried moving the documentation inline,
> and the scripts/kernel-doc script ignores the comment blocks for the
> inner fields.
>
> Mauro, Jon, is this a known issue ? If so, are there plans to fix it ?
> What's the recommended way to pro
On Wed, 2 Aug 2023 at 02:37, Conor Dooley wrote:
>
> On Mon, Jul 31, 2023 at 04:30:03PM +0530, Jagan Teki wrote:
> > Document the VOP for Rockchip RV1126.
> >
> > Signed-off-by: Jagan Teki
>
> There's no commentary here about compatibility with other, existing,
> devices nor did you CC me on the
On Tue, Jul 18, 2023 at 05:31:49PM +0200, Michael Riesch wrote:
> Hi all,
>
> This series adds support for the partial display mode to the Sitronix
> ST7789V panel driver. This is useful for panels that are partially
> occluded by design, such as the Jasonic JT240MHQS-HWT-EK-E3. Support
> for this
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