tree: git://anongit.freedesktop.org/drm-intel drm-intel-next
head: 0c4f52bac4401dfd6f82984040bc0e163b0ccb9c
commit: f6757dfcfde722fdeaee371b66f63d7eb61dd7e4 [1/2] drm/doc: fix duplicate
declaration warning
reproduce:
(https://download.01.org/0day-ci/archive/20230701/202307011340.vny1abul-...@
https://bugzilla.kernel.org/show_bug.cgi?id=213145
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--- Comment #54 from MasterCATZ (masterc...@hotmail.com) ---
Still getting this using kodi playing back video files
VGA: Advanced Micro Devices, Inc. [AMD/ATI] Navi 21 [Radeon RX 6800/6800 XT /
6900 XT] (rev c1)
OpenGL driver: radeonsi
Kernel dr
Specify how the atomic state is maintained between userspace and
kernel, plus the special case for async flips.
Signed-off-by: André Almeida
---
v4: new patch
---
Documentation/gpu/drm-uapi.rst | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/gpu/drm-uapi.rs
Given that prop changes may lead to modesetting, which would defeat the
fast path of the async flip, refuse any atomic prop change for async
flips in atomic API. The only exceptions are the framebuffer ID to flip
to and the mode ID, that could be referring to an identical mode.
Signed-off-by: Andr
From: Simon Ser
amdgpu_dm_commit_planes() already sets the flip_immediate flag for
async page-flips. This flag is used to set the UNP_FLIP_CONTROL
register. Thus, no additional change is required to handle async
page-flips with the atomic uAPI.
Signed-off-by: Simon Ser
Reviewed-by: André Almeid
From: Simon Ser
This new field indicates whether the driver has the necessary logic
to support async page-flips via the atomic uAPI. This is leveraged by
the next commit to allow user-space to use this functionality.
All atomic drivers setting drm_mode_config.async_page_flip are updated
to also
From: Simon Ser
This new kernel capability indicates whether async page-flips are
supported via the atomic uAPI. DRM clients can use it to check
for support before feeding DRM_MODE_PAGE_FLIP_ASYNC to the kernel.
Make it clear that DRM_CAP_ASYNC_PAGE_FLIP is for legacy uAPI only.
Signed-off-by:
From: Simon Ser
If the driver supports it, allow user-space to supply the
DRM_MODE_PAGE_FLIP_ASYNC flag to request an async page-flip.
Set drm_crtc_state.async_flip accordingly.
Document that drivers will reject atomic commits if an async
flip isn't possible. This allows user-space to fall back
Hi,
This work from me and Simon adds support for DRM_MODE_PAGE_FLIP_ASYNC through
the atomic API. This feature is already available via the legacy API. The use
case is to be able to present a new frame immediately (or as soon as
possible), even if after missing a vblank. This might result in teari
On 6/29/2023 5:59 PM, Dmitry Baryshkov wrote:
On 30/06/2023 03:25, Jessica Zhang wrote:
Drop DPU_PLANE_COLOR_FILL_FLAG and check the DRM solid_fill property to
determine if the plane is solid fill. In addition drop the DPU plane
color_fill field as we can now use drm_plane_state.solid_fill in
On 6/30/2023 1:21 AM, Pekka Paalanen wrote:
On Fri, 30 Jun 2023 03:52:37 +0300
Dmitry Baryshkov wrote:
On 30/06/2023 03:25, Jessica Zhang wrote:
Since solid fill planes allow for a NULL framebuffer in a valid commit,
add NULL framebuffer checks to atomic commit calls within DPU.
Signed-of
> +static void get_chan_freq_boundary(u32 center_freq,
> +u32 bandwidth,
> +u64 *start,
> +u64 *end)
> +{
> + bandwidth = MHZ_TO_KHZ(bandwidth);
> + center_freq = MHZ_TO_KHZ(center_freq);
> +
> +
> + argv4 = kzalloc(sizeof(*argv4) * (2 * num_of_ranges + 2 + 1),
> GFP_KERNEL);
> + if (!argv4)
> + return -ENOMEM;
> +
> + argv4[arg_idx].package.type = ACPI_TYPE_PACKAGE;
> + argv4[arg_idx].package.count = 2 + 2 * num_of_ranges;
> + argv4[arg_idx++].package.eleme
On Sat, 1 Jul 2023 at 02:12, Konrad Dybcio wrote:
>
> Recently, a WARN_ON() was introduced to ensure that revn is filled before
> adreno_is_aXYZ is called. This however doesn't work very well when revn is
> 0 by design (such as for A635). Fill it in as a stopgap solution for
> -fixes.
>
> Fixes: c
On Friday, June 30, 2023 1:35:02 PM PDT Lucas De Marchi wrote:
> v3 of https://patchwork.freedesktop.org/series/119766/
>
> Changes from v2:
>
> - Do not rmw if (clr | set) covers all bits
> - Add patch to make sure the set bits are also checked on
> wa_*_clr_set() when clr is
> Right now there are stubs for non CONFIG_WBRF as well as other patches are
> using #ifdef CONFIG_WBRF or having their own stubs. Like mac80211 patch
> looks for #ifdef CONFIG_WBRF.
>
> I think we should pick one or the other.
>
> Having other subsystems #ifdef CONFIG_WBRF will make the series
> Drivers/subsystems contributing frequencies:
>
> 1) During probe, check `wbrf_supported_producer` to see if WBRF supported
>for the device.
What is the purpose of this stage? Why would it not be supported for
this device?
> +#ifdef CONFIG_WBRF
> +bool wbrf_supported_producer(struct device
On 6/29/2023 5:49 PM, Dmitry Baryshkov wrote:
On 30/06/2023 03:25, Jessica Zhang wrote:
Add solid_fill and pixel_source properties to DPU plane
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 ++
1 file changed, 2 insertions(+)
This should be the last com
On 6/29/2023 5:48 PM, Dmitry Baryshkov wrote:
On 30/06/2023 03:25, Jessica Zhang wrote:
Loosen the requirements for atomic and legacy commit so that, in cases
where solid fill planes is enabled but no FB is set, the commit can
still go through.
This includes adding framebuffer NULL checks in
On 6/23/2023 12:10 AM, Marijn Suijten wrote:
It is nice if cover letters also include the subsystem:
drm/msm: Add support to print DPU sub-block registers
On 2023-06-22 16:48:52, Ryan McCann wrote:
The purpose of this patch series is to add support to print the registers
of sub blocks in th
Recently, a WARN_ON() was introduced to ensure that revn is filled before
adreno_is_aXYZ is called. This however doesn't work very well when revn is
0 by design (such as for A635). Fill it in as a stopgap solution for
-fixes.
Fixes: cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified befo
On Thu, Jun 22, 2023 at 02:12:32PM -0700, Randy Dunlap wrote:
> Is this going anywhere? It was posted about 2 months ago.
Last I heard Dave was still working with Lucas on this?
Luis
On 6/30/2023 7:43 AM, Sebastian Wick wrote:
On Fri, Jun 30, 2023 at 2:26 AM Jessica Zhang wrote:
Add support for pixel_source property to drm_plane and related
documentation.
This enum property will allow user to specify a pixel source for the
plane. Possible pixel sources will be defined
The HDMI block needs to be enabled to properly generate HPD events. Make
sure it is not turned off in the disable paths if HPD delivery is enabled.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h| 2 ++
drivers/gpu/drm/msm
The HDMI driver already has msm_hdmi_hpd_enable() and
msm_hdmi_hpd_disable() functions. Wire them into the
msm_hdmi_bridge_funcs, so that HPD can be enabled and disabled
dynamically rather than always having HPD events generation enabled.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/
Supporting simultaneous check of native HPD and the external GPIO proved
to be less stable than just native HPD. Drop the hpd-gpios support,
leaving just the native HPD support. In case the native HPD doesn't work
the user is urged to switch to specifying the HPD property to the
hdmi-connector devi
It is completely not obvious, but the so-called 'hpd' clocks and
regulators are required for the HDMI host to function properly. Merge
pwr and hpd regulators. Use regulators, clocks and pinctrl to implement
proper runtime PM callbacks.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi
The pm_runtime_get_sync() function is a bad choise for runtime power
management. Switch HDMI driver to pm_runtime_resume_and_get() and add
proper error handling, while we are at it.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 +-
drivers/gpu/drm/msm/hdmi/hdmi_
Expand the HDMI_CFG() macro in HDMI config description. It has no added
value other than hiding some boilerplate declarations.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 16
drivers/gpu/drm/msm/hdmi/hdmi.h | 2 +-
2 files changed, 9 insertions(+), 9 d
The only clock which has frequency being set through hpd_freqs is the
"core" aka MDSS_HDMI_CLK clock. It always has the specified frequency,
so we can drop corresponding clk_set_rate() call together with the
hpd_freq infrastructure.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hd
We must be sure that the HDMI controller is powered on, while performing
the DDC transfer. Add corresponding runtime PM calls to
msm_hdmi_i2c_xfer().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_i2c.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
dif
The last platform using legacy clock names for HDMI block (APQ8064)
switched to new clock names in 5.16. It's time to stop caring about old
DT, drop hand-coded helpers and switch to clk_bulk_* API.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 15 ---
drivers/
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24 ---
drivers/gpu/drm/msm/hdmi/hdmi.h| 6 +
drivers/gpu/drm/msm/hdmi/hdmi_
As these clocks are now used in the runtime PM callbacks, they have no
connection to 'HPD'. Rename corresponding fields to follow clocks
purpose, to power up the HDMI controller.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 26 +-
drivers/gpu/drm/
In consequent modeset calls, the atomic_pre_enable() will be called
several times without calling atomic_post_disable() inbetween. Thus
iframes will not be updated for the next mode. Fix this by setting the
iframe outside of the !power_on check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/dr
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 62ce1455f974..fbcf4dd91cd9 100644
--- a/drivers/gpu/dr
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
The MSM HDMI driver is plagued with the long-standing bug. If HDMI cable
is disconnected, in most of the cases cable reconnection will not be
detected properly. We have been carrying the patch from [1] in our
integration tree for ages. The time has come to fix the long-standing
bug and implement pr
On Wed, Jun 28, 2023 at 12:54 PM Dmitry Baryshkov
wrote:
>
> On 28/06/2023 22:05, Konrad Dybcio wrote:
> > Recently, a WARN_ON() was introduced to ensure that revn is filled before
> > adreno_is_aXYZ is called. This however doesn't work very well when revn is
> > 0 by design (such as for A635). Fi
v3 of https://patchwork.freedesktop.org/series/119766/
Changes from v2:
- Do not rmw if (clr | set) covers all bits
- Add patch to make sure the set bits are also checked on
wa_*_clr_set() when clr is not a superset.
Tested on DG2 with intel_reg reading 0xb158 with a bu
Most of the context workarounds tweak masked registers, but not all. For
masked registers, when writing the value it's sufficient to just write
the wa->set_bits since that will take care of both the clr and set bits
as well as not overwriting other bits.
However there are some workarounds, the reg
When checking if the workarounds were applied succesfully, the read-back
mask should also contain the bits being set: it's possible that in a
call to wa_write_clr_set(), the cleared bits are not a superset of the
set bits.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarou
Contrary to GEN12_FF_MODE2, platforms using XEHP_FF_MODE2 are not
affected by Wa_1608008084, hence read back can be enabled.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
The comment on the parameter being 0 to avoid the read back doesn't
apply as this is not a call to wa_add(), but rather to
wa_write_clr_set(). So, this register is actually checked and it's
according to the Bspec that the register is RW, not RO.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm
Right now context workarounds don't do a rmw and instead only write to
the register. Since 2 separate programmings to the same register are
coalesced into a single write, this is not problematic for
GEN12_FF_MODE2 since both TDS and GS timer are going to be written
together and the other remaining
Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
1 file changed, 1 insertion(+), 4 deleti
Move helper function to get all the forcewakes required by the wa list
to the top, so it can be re-used by other functions.
Signed-off-by: Lucas De Marchi
Reviewed-by: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++---
1 file changed, 16 insertions(+), 1
That's a terrible idea. Ignoring API calls would be identical to a freeze.
You might as well disable GPU recovery because the result would be the same.
There are 2 scenarios:
- robust contexts: report the GPU reset status and skip API calls; let the
app recreate the context to recover
- non-robust
Andy Shevchenko writes:
> On Fri, Jun 30, 2023 at 07:38:01PM +0200, Javier Martinez Canillas wrote:
>> Andy Shevchenko writes:
>> > On Fri, Jun 30, 2023 at 12:51:02AM +0200, Javier Martinez Canillas wrote:
>> >> This patch series splits the fbdev core support in two different Kconfig
>> >> symbo
On Fri, Jun 30, 2023 at 9:21 AM John Stultz wrote:
>
> Laura's email address has not been valid for quite awhile now,
> so wanted to clean up the reviewer list here.
>
> I reached out to Laura who said it made sense to drop her from
> the list, so this patch does that.
>
> I do want to recognize L
On Fri, 30 Jun 2023, Bjorn Helgaas wrote:
> On Fri, Jun 30, 2023 at 10:14:11AM +0800, suijingfeng wrote:
>> On 2023/6/30 01:44, Limonciello, Mario wrote:
>> > > On 2023/6/29 23:54, Bjorn Helgaas wrote:
>> > > > On Thu, Jun 22, 2023 at 01:08:15PM +0800, Sui Jingfeng wrote:
>
>> > > > 4) Right now w
On Fri, Jun 30, 2023 at 06:29:08PM +0200, Neil Armstrong wrote:
> Add new CLK ids for the CTS_ENCL and CTS_ENCL_SEL clocks
> on G12A compatible SoCs.
>
> Signed-off-by: Neil Armstrong
Acked-by: Conor Dooley
Cheers,
Conor.
signature.asc
Description: PGP signature
On Fri, Jun 30, 2023 at 06:29:15PM +0200, Neil Armstrong wrote:
> The MNT Reform 2 CM4 adapter can be populated with any Raspberry Pi CM4
> compatible module such as a BPI-CM4 Module, document that.
>
> Signed-off-by: Neil Armstrong
Acked-by: Conor Dooley
Cheers,
Conor.
signature.asc
Descrip
On 6/29/2023 5:43 PM, Dmitry Baryshkov wrote:
On 30/06/2023 03:25, Jessica Zhang wrote:
Currently framebuffer checks happen directly in
drm_atomic_plane_check(). Move these checks into their own helper
method.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 130
++
Hi Dave, Daniel,
Fixes for 6.5. This is a bit bigger than usual since it's two weeks of fixes
and I missed a bunch of stuff for 6.4 final due to being out of the office
last week and having a late PR.
The following changes since commit dcb0775d36de28992f56455ab3967b30d380:
Merge tag 'drm-
On 6/30/2023 3:33 AM, Dmitry Baryshkov wrote:
On 30/06/2023 03:25, Jessica Zhang wrote:
Document and add support for solid_fill property to drm_plane. In
addition, add support for setting and getting the values for solid_fill.
To enable solid fill planes, userspace must assign a property blo
On Fri, Jun 30, 2023 at 08:42:21PM +0300, Andy Shevchenko wrote:
> On Fri, Jun 30, 2023 at 07:38:01PM +0200, Javier Martinez Canillas wrote:
> > Andy Shevchenko writes:
> > > On Fri, Jun 30, 2023 at 12:51:02AM +0200, Javier Martinez Canillas wrote:
...
> > >> The reason for doing this is that no
On Fri, Jun 30, 2023 at 07:38:01PM +0200, Javier Martinez Canillas wrote:
> Andy Shevchenko writes:
> > On Fri, Jun 30, 2023 at 12:51:02AM +0200, Javier Martinez Canillas wrote:
> >> This patch series splits the fbdev core support in two different Kconfig
> >> symbols: FB and FB_CORE. The motivati
On Fri, Jun 30, 2023 at 10:14:11AM +0800, suijingfeng wrote:
> On 2023/6/30 01:44, Limonciello, Mario wrote:
> > > On 2023/6/29 23:54, Bjorn Helgaas wrote:
> > > > On Thu, Jun 22, 2023 at 01:08:15PM +0800, Sui Jingfeng wrote:
> > > > 4) Right now we're in the middle of the v6.5 merge window, so ne
Andy Shevchenko writes:
Hello Andy,
> On Fri, Jun 30, 2023 at 12:51:02AM +0200, Javier Martinez Canillas wrote:
>> This patch series splits the fbdev core support in two different Kconfig
>> symbols: FB and FB_CORE. The motivation for this is to allow CONFIG_FB to
>> be disabled, while still hav
On Fri, Jun 30, 2023 at 12:51:02AM +0200, Javier Martinez Canillas wrote:
> This patch series splits the fbdev core support in two different Kconfig
> symbols: FB and FB_CORE. The motivation for this is to allow CONFIG_FB to
> be disabled, while still having the the core fbdev support needed for th
On 2023-06-30 08:00, Christian König wrote:
> Some Android CTS is testing if the signaling time keeps consistent
> during merges.
>
> v2: use the current time if the fence is still in the signaling path and
> the timestamp not yet available.
> v3: improve comment, fix one more case to use the corr
Add the first version of the VM_BIND locking document which is
intended to be part of the xe driver upstreaming agreement.
The document describes and discuss the locking used during exec-
functions, evicton and for userptr gmvas. Intention is to be using the
same nomenclature as the drm-vm-bind-as
On Thu, Jun 29, 2023 at 10:44:34PM +0200, Konrad Dybcio wrote:
> On 29.06.2023 22:35, Konrad Dybcio wrote:
> > Modern Qualcomm SoCs have a REFGEN (reference voltage generator)
> > regulator, providing reference voltage to on-chip IP, like PHYs.
> >
> > Add a driver to support toggling that regulat
On 6/30/2023 05:32, Evan Quan wrote:
Due to electrical and mechanical constraints in certain platform designs
there may be likely interference of relatively high-powered harmonics of
the (G-)DDR memory clocks with local radio module frequency bands used
by Wifi 6/6e/7.
To mitigate this, AMD has
On Thu, 29 Jun 2023 22:35:41 +0200, Konrad Dybcio wrote:
> Modern Qualcomm SoCs have a REFGEN (reference voltage generator)
> regulator, providing reference voltage to on-chip IP, like PHYs.
> It's controlled through MMIO and we can toggle it or read its state back.
>
> Describe it.
>
> Signed-
This adds a basic devicetree for the MNT Reform2 DIY laptop when using a
CM4 adapter and a BPI-CM4 module.
Co-developed-by: Lukas F. Hartmann
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../meson-g12b-bananapi-cm4-mnt-reform2.dts| 388 ++
The MNT Reform 2 CM4 adapter can be populated with any Raspberry Pi CM4
compatible module such as a BPI-CM4 Module, document that.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bin
Add the MIPI DSI Analog & Digital PHY nodes and the DSI control
nodes with proper port endpoint to the VPU.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 70 +++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic
Disable the px_clk when setting the rate to recover a fully
configured and correctly reset VCLK clock tree after the rate
is set.
Fixes: 77d9e1e6b846 ("drm/meson: add support for MIPI-DSI transceiver")
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 7 +++
1 fil
This add nodes to support the Khadas TS050 panel on the
Khadas VIM3 & VIM3L boards.
Signed-off-by: Neil Armstrong
---
.../boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 76 ++
.../boot/dts/amlogic/meson-sm1-khadas-
In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.
The nocache option is removed from following clocks:
- vclk2_sel
- vclk2_input
- vclk2_div
- vclk2
- vclk_div1
- vclk2_div2_en
- vclk2_div4_en
- vclk2_div6_en
- vclk2_div12_en
- vclk2_div2
- vclk2_div4
-
Add new CLK ids for the CTS_ENCL and CTS_ENCL_SEL clocks
on G12A compatible SoCs.
Signed-off-by: Neil Armstrong
---
include/dt-bindings/clock/g12a-clkc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/g12a-clkc.h
b/include/dt-bindings/clock/g12a-clkc.h
index 387
Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
SoCs, they are used to feed the VPU LCD Pixel encoder used for
DSI display purposes.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.c | 40
1 file changed, 40 insertions(+)
diff --g
The VCLK and VCLK_DIV clocks have supplementary bits.
The VCLK has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.
The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
(ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the
DW-HDMI
glue on the same Amlogic SoCs.
This is a follow-up of v5 now the DRM patches are applied, the clk & DT changes
remains
Laura's email address has not been valid for quite awhile now,
so wanted to clean up the reviewer list here.
I reached out to Laura who said it made sense to drop her from
the list, so this patch does that.
I do want to recognize Laura's long time contribution to this
area and her previous ION ma
From: Rob Clark
The range is actually len+1.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index eea2e60ce3b7..edf76a4b16b
Cc: Ben Skeggs
Cc: Lyude Paul
Fixes: f530bc60a30b ("drm/nouveau/disp: move HDMI config into acquire +
infoframe methods")
Signed-off-by: Karol Herbst
---
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/
On Fri, Jun 30, 2023 at 4:59 PM Alex Deucher wrote:
>
> On Fri, Jun 30, 2023 at 10:49 AM Sebastian Wick
> wrote:
> >
> > On Tue, Jun 27, 2023 at 3:23 PM André Almeida
> > wrote:
> > >
> > > Create a section that specifies how to deal with DRM device resets for
> > > kernel and userspace drivers
On 6/30/23 16:59, Alex Deucher wrote:
> On Fri, Jun 30, 2023 at 10:49 AM Sebastian Wick
> wrote:
>> On Tue, Jun 27, 2023 at 3:23 PM André Almeida wrote:
>>>
>>> +Robustness
>>> +--
>>> +
>>> +The only way to try to keep an application working after a reset is if it
>>> +complies with the
On Fri, Jun 30, 2023 at 10:49 AM Sebastian Wick
wrote:
>
> On Tue, Jun 27, 2023 at 3:23 PM André Almeida wrote:
> >
> > Create a section that specifies how to deal with DRM device resets for
> > kernel and userspace drivers.
> >
> > Acked-by: Pekka Paalanen
> > Signed-off-by: André Almeida
> >
On Tue, Jun 27, 2023 at 3:23 PM André Almeida wrote:
>
> Create a section that specifies how to deal with DRM device resets for
> kernel and userspace drivers.
>
> Acked-by: Pekka Paalanen
> Signed-off-by: André Almeida
> ---
>
> v4:
> https://lore.kernel.org/lkml/20230626183347.55118-1-andreal
On Fri, Jun 30, 2023 at 2:26 AM Jessica Zhang wrote:
>
> Add support for pixel_source property to drm_plane and related
> documentation.
>
> This enum property will allow user to specify a pixel source for the
> plane. Possible pixel sources will be defined in the
> drm_plane_pixel_source enum.
>
Hi Evan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on wireless-next/main]
[also build test WARNING on wireless/main v6.4]
[cannot apply to drm-misc/drm-misc-next linus/master next-20230630]
[If your patch is applied to the wrong git tree, kindly drop us a
Hi Evan,
kernel test robot noticed the following build errors:
[auto build test ERROR on wireless-next/main]
[also build test ERROR on wireless/main linus/master v6.4]
[cannot apply to drm-misc/drm-misc-next next-20230630]
[If your patch is applied to the wrong git tree, kindly drop us a note
On Fri, Jun 30, 2023 at 06:32:32PM +0800, Evan Quan wrote:
...
> diff --git a/include/linux/wbrf.h b/include/linux/wbrf.h
> new file mode 100644
> index ..3ca95786cef5
> --- /dev/null
> +++ b/include/linux/wbrf.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + *
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
registe
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
Currently we check if pipe_bpp is max the min DSC bpc requirements.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +
1 file changed, 24 insertions(
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 ++---
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_d
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 189
1 file changed
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++--
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 11
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