This has already been fixed with:
commit 2ce977df10c179138e2723b25c2d2c055a3e3cc6
Author: Ma Jun
Date: Wed May 31 13:30:51 2023 +0800
drm/ttm: Remove redundant code in ttm_tt_init_fields
Remove redundant assignment code for ttm->caching as it's overwritten
just a few lines later.
suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Xiaoyong-Lu/media-mediatek-vcodec-fix-AV1-decode-fail-for-36bit-iova/20230628-134327
base: next-20230627
patch link:
https://bugzilla.kernel.org/show_bug.cgi?id=217607
Bug ID: 217607
Summary: null pointer dereference with NVIDIA installer on
5.15.118 and 5.15.119
Product: Drivers
Version: 2.5
Hardware: Intel
OS: Linux
On 6/24/23 18:29, Carlos Eduardo Gallo Filho wrote:
Swap tests parameters names so they actually reflect what is being tested.
v1: https://lore.kernel.org/all/20230623152518.8603-1-gcar...@disroot.org/
v2: Simplified commit message.
Signed-off-by: Carlos Eduardo Gallo Filho
Reviewed-by: André
On Wed, Jun 28, 2023 at 11:17:18AM -0700, Alan Previn wrote:
> In the ABI header, GUC_CTB_MSG_MIN_LEN is '1' because
> GUC_CTB_HDR_LEN is 1. This aligns with H2G/G2H CTB specification
> where all command formats are defined in units of dwords so that '1'
> is a dword. Accordingly, GUC_CTB_MSG_MAX_L
: 5c875096d59010cee4e00da1f9c7bdb07a025dc2
patch link:
https://lore.kernel.org/r/20230628-topic-refgen-v1-2-126e59573eeb%40linaro.org
patch subject: [PATCH 2/4] regulator: Introduce Qualcomm REFGEN regulator driver
config: loongarch-allmodconfig
(https://download.01.org/0day-ci/archive/20230629/202306290533
We have to verify the selected mode as Userspace might request one which
we can't configure the GPU for.
X with the modesetting DDX is adding a bunch of modes, some so far outside
of hardware limits that things simply break.
Sadly we can't fix X this way as on start it sticks to one mode and
igno
Signed-off-by: Karol Herbst
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_dp.c| 3 +--
drivers/gpu/drm/nouveau/nouveau_encoder.h | 3 +--
4 files changed, 4 insertions(+), 6 deletions(-)
diff
Cc: Ben Skeggs
Cc: Lyude Paul
Fixes: f530bc60a30b ("drm/nouveau/disp: move HDMI config into acquire +
infoframe methods")
Signed-off-by: Karol Herbst
---
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau
On Wed, Jun 28, 2023 at 1:39 PM John Stultz wrote:
>
> On Wed, Jun 28, 2023 at 11:05 AM Jeffrey Hugo wrote:
> >
> > @codeaurora.org email addresses are no longer valid and will bounce.
> >
> > I reached out to Liam about updating his entry under DMA-BUF HEAPS
> > FRAMEWORK with an @codeaurora.org
On Wed, Jun 28, 2023 at 11:05 AM Jeffrey Hugo wrote:
>
> @codeaurora.org email addresses are no longer valid and will bounce.
>
> I reached out to Liam about updating his entry under DMA-BUF HEAPS
> FRAMEWORK with an @codeaurora.org address. His response:
>
> "I am not a maintainer anymore, that
Some GPUs - particularly A7xx ones - are really really stubborn and
sometimes take a longer-than-expected time to finish unhalting GBIF.
Note that this is not caused by the request a few lines above.
Poll for the unhalt ack to make sure we're not trying to write bits to
an essentially dead GPU th
A7xx GMUs can be slow as molasses at times.
Increase the timeout to 1 second to match the vendor driver.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
b/drivers/gpu
A740 builds upon the A730 IP, shuffling some values and registers
around. More differences will appear when things like BCL are
implemented.
adreno_is_a740_family is added in preparation for more A7xx GPUs,
the logic checks will be valid resulting in smaller diffs.
Signed-off-by: Konrad Dybcio
-
Move these wrappers in preparation for use in a6xx_gmu.c
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 +++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/a
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8
2 files changed, 17 insertions(+)
diff --git
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 61 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 13
The QMP mailbox expects to be notified of the ACD (Adaptive Clock
Distribution) state. Get a handle to the mailbox at probe time and
poke it at GMU resume.
Since we don't fully support ACD yet, hardcode the message to "val: 0"
(state = disabled).
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++-
drivers/gpu/drm/ms
A7xx GPUs are - from kernel's POV anyway - basically another generation
of A6xx. They build upon the A650/A660_family advancements, skipping some
writes (presumably more values are preset correctly on reset), adding
some new ones and changing others.
One notable difference is the introduction of a
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documenta
If the GMU can't guarantee the required resources are up, trying to
bring up the GPU is a lost cause. Return early if setting GPU OOB
fails.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
Add a helper that does exactly what it says on the can, it'll be
required for A7xx.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
When booting the GMU, the QMP mailbox should be pinged about some tunables
(e.g. adaptive clock distribution state). To achieve that, a reference to
it is necessary. Allow it and require it with A730.
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
The GMU on the A7xx series is pretty much the same as on the A6xx parts.
It's now "smarter", needs a bit less register writes and controls more
things (like inter-frame power collapse) mostly internally (instead of
us having to write to G[PM]U_[CG]X registers from APPS)
The only difference worth m
7c0844717d
change-id: 20230628-topic-a7xx_drmmsm-123f30d76cf7
Best regards,
--
Konrad Dybcio
On 6/26/2023 7:04 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:41, Marijn Suijten wrote:
SM6125 is identical to SM6375 except that while downstream also defines
a throttle clock, its presence results in timeouts whereas SM6375
requires it to not observe any timeouts.
I see that the vendor D
On Wed, 2023-06-28 at 10:54 +0300, Pekka Paalanen wrote:
> On Wed, 28 Jun 2023 10:41:06 +0300
> Pekka Paalanen wrote:
>
> > On Wed, 28 Jun 2023 01:21:27 -0400
> > Zack Rusin wrote:
> >
> > > From: Zack Rusin
> > >
> > > Atomic modesetting code lacked support for specifying mouse cursor
> > >
,
[ADRENO_FW_GMU] = "a660_gmu.bin",
---
base-commit: 5c875096d59010cee4e00da1f9c7bdb07a025dc2
change-id: 20230628-topic-a635-1b3c2c987417
Best regards,
--
With best wishes
Dmitry
On Wed, Jun 28, 2023 at 06:29:46PM +0200, Konrad Dybcio wrote:
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
Please use a C++ comment for the whole thing for consist
On Wed, Jun 28, 2023 at 4:20 PM Marijn Suijten
wrote:
> But for now we might already create a step-up version of that by having
> a "Samsung panel driver library" to deduplicate generic commands, which
> drivers can freely call into?
Yeah something like that is likely what we want.
> On the oth
660_sqe.fw",
[ADRENO_FW_GMU] = "a660_gmu.bin",
---
base-commit: 5c875096d59010cee4e00da1f9c7bdb07a025dc2
change-id: 20230628-topic-a635-1b3c2c987417
Best regards,
--
Konrad Dybcio
In the ABI header, GUC_CTB_MSG_MIN_LEN is '1' because
GUC_CTB_HDR_LEN is 1. This aligns with H2G/G2H CTB specification
where all command formats are defined in units of dwords so that '1'
is a dword. Accordingly, GUC_CTB_MSG_MAX_LEN is 256-1 (i.e. 255
dwords). However, h2g_write was incorrectly ass
@codeaurora.org email addresses are no longer valid and will bounce.
I reached out to Liam about updating his entry under DMA-BUF HEAPS
FRAMEWORK with an @codeaurora.org address. His response:
"I am not a maintainer anymore, that should be removed."
Liam currently does not have an email address
On 6/28/2023 12:34 AM, Pekka Paalanen wrote:
On Tue, 27 Jun 2023 15:10:19 -0700
Abhinav Kumar wrote:
On 6/27/2023 2:59 PM, Dmitry Baryshkov wrote:
On 28/06/2023 00:27, Jessica Zhang wrote:
On 6/27/2023 12:58 AM, Pekka Paalanen wrote:
On Mon, 26 Jun 2023 16:02:50 -0700
Jessica Zhang wr
Consume the refgen supply on configurations that may use it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 8a5fb6df7210..1f98ff74ceb0 100644
---
DSI host needs REFGEN to be enabled (if it's present on a given platform).
Allow consuming it.
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display
Modern Qualcomm SoCs have a REFGEN (reference voltage generator)
regulator, providing reference voltage to on-chip IP, like PHYs.
It's controlled through MMIO and we can toggle it or read its state back.
Describe it.
Signed-off-by: Konrad Dybcio
---
.../regulator/qcom,sdm845-refgen-regulator.ya
Modern Qualcomm SoCs have a REFGEN (reference voltage generator)
regulator, providing reference voltage to on-chip IP, like PHYs.
Add a driver to support toggling that regulator.
This driver is based on the driver available in the downstream msm-5.4
kernel. It's been cleaned up and partly remade
/regulator/qcom-refgen-regulator.c | 187 +
6 files changed, 260 insertions(+)
---
base-commit: 5c875096d59010cee4e00da1f9c7bdb07a025dc2
change-id: 20230628-topic-refgen-14fb0b762115
Best regards,
--
Konrad Dybcio
On Wed, 2023-06-28 at 14:15 +, Simon Ser wrote:
> I think we should drop the CRTC_X/CRTC_Y properties for hotspot-aware cursor
> planes.
> The drivers aren't going to do anything with these, and exposing them to user-
> space
> makes it sound like user-space controls the position of the plane,
On 2023-06-28 09:30:51, Rob Herring wrote:
> On Tue, Jun 27, 2023 at 10:14:22PM +0200, Marijn Suijten wrote:
> > Document the SM6125 MDSS.
> >
> > Reviewed-by: Krzysztof Kozlowski
> > Signed-off-by: Marijn Suijten
> > ---
> > .../bindings/display/msm/qcom,sm6125-mdss.yaml | 217
> > +++
From: Tvrtko Ursulin
Informal commit message for now.
I got a bit impatient and curious to see if the idea we discussed would
work so sketched something out. I think it is what I was describing back
then..
So high level idea is to teach the driver what caching modes are hidden
behind PAT indice
Hi,
Le mercredi 28 juin 2023 à 13:41 +0800, Xiaoyong Lu a écrit :
> Decoder hardware will access incorrect iova address when tile buffer is
> 36bit, leading to iommu fault when hardware access dram data.
>
> Fixes: 2f5d0aef37c6 ("media: mediatek: vcodec: support stateless AV1 decoder")
> Signed-o
On Mon, Jun 19, 2023 at 3:02 PM Dmitry Osipenko <
dmitry.osipe...@collabora.com> wrote:
> On 6/13/23 20:43, Gurchetan Singh wrote:
> > We don't want to create a fence for every command submission. It's
> > only necessary when userspace provides a waitable token for submission.
> > This could be:
We don't want to create a fence for every command submission. It's
only necessary when userspace provides a waitable token for submission.
This could be:
1) bo_handles, to be used with VIRTGPU_WAIT
2) out_fence_fd, to be used with dma_fence apis
3) a ring_idx provided with VIRTGPU_CONTEXT_PARAM_P
On Tue, Jun 27, 2023 at 10:14:22PM +0200, Marijn Suijten wrote:
> Document the SM6125 MDSS.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Marijn Suijten
> ---
> .../bindings/display/msm/qcom,sm6125-mdss.yaml | 217
> +
> 1 file changed, 217 insertions(+)
>
> di
On 2023-06-28 11:22:37, Linus Walleij wrote:
> On Sun, May 21, 2023 at 11:23 PM Marijn Suijten
> wrote:
>
> > The Sony Xperia 1 (codename kumano griffin) features an unnamed 4k OLED
> > DSI cmd mode panel produced by Samsung. It can be driven in a
> > 1644x3840@60 or 1096x2560@60 mode, and alway
I think we should drop the CRTC_X/CRTC_Y properties for hotspot-aware cursor
planes.
The drivers aren't going to do anything with these, and exposing them to
user-space
makes it sound like user-space controls the position of the plane, but it really
doesn't.
Use the new component here as well and remove the old handling.
v2: drop dupplicate handling
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 71 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 5 +-
d
Start using the new component here as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 78 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 80 -
2 files changed, 71 insertions(+), 87 deletions(-)
diff --git a/drivers/g
Start using the new component here as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 90 -
1 file changed, 43 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.
Exercise at least all driver facing functions of this new component.
v2: add array test as well
v3: some kunit cleanups
v4: more tests and cleanups
Signed-off-by: Christian König
---
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/tests/Makefile| 3 +-
drivers/gpu/drm/t
Avoids quite a bit of logic and kmalloc overhead.
v2: fix multiple problems pointed out by Felix
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/Kconfig| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 5 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 299
This adds the infrastructure for an execution context for GEM buffers
which is similar to the existing TTMs execbuf util and intended to replace
it in the long term.
The basic functionality is that we abstracts the necessary loop to lock
many different GEM buffers with automated deadlock and dupli
Hey Alex,
any objections to merge those patches through drm-misc-next? If not can you
give me an rb for them?
Thanks,
Christian.
Hi,
On 2023/4/17 20:56, Thomas Zimmermann wrote:
Replace the architecture's fbdev helpers with the generic
ones from . No functional changes.
v2:
* use default implementation for fb_pgprotect() (Arnd)
Signed-off-by: Thomas Zimmermann
Cc: Huacai Chen
Cc: WANG Xuerui
---
arch/loonga
On Sat, Jun 24, 2023, at 16:21, Arnd Bergmann wrote:
> On Sat, Jun 24, 2023, at 15:26, Guenter Roeck wrote:
>> On 6/24/23 02:27, Arnd Bergmann wrote:
>>> On Sat, Jun 24, 2023, at 03:55, Guenter Roeck wrote:
ERROR: modpost: "__xchg_called_with_bad_pointer" [lib/atomic64_test.ko]
undef
On Sun, May 21, 2023 at 11:23 PM Marijn Suijten
wrote:
> The Sony Xperia 1 (codename kumano griffin) features an unnamed 4k OLED
> DSI cmd mode panel produced by Samsung. It can be driven in a
> 1644x3840@60 or 1096x2560@60 mode, and always has Display Stream
> Compression 1.1 enabled.
>
> Signe
On Tue, 20 Jun 2023, Ralph Campbell wrote:
> The OSVR virtual reality headset HDK 2.0 uses a different EDID
> vendor and device identifier than the HDK 1.1 - 1.4 headsets.
> Add the HDK 2.0 vendor and device identifier to the quirks table so
> that window managers do not try to display the desktop
Pekka Paalanen writes:
Hello Pekka,
> On Wed, 28 Jun 2023 10:41:06 +0300
> Pekka Paalanen wrote:
>
>> On Wed, 28 Jun 2023 01:21:27 -0400
>> Zack Rusin wrote:
>>
>> > From: Zack Rusin
>> >
>> > Atomic modesetting code lacked support for specifying mouse cursor
>> > hotspots. The legacy kms D
On Tue, 27 Jun 2023, Colin Ian King wrote:
> Don't populate the const array on the stack, instead make it static.
>
> Signed-off-by: Colin Ian King
Thanks, pushed to drm-misc-next.
> ---
> drivers/gpu/drm/drm_edid.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drive
Hi David,
>
> On 27.06.23 08:37, Kasireddy, Vivek wrote:
> > Hi David,
> >
>
> Hi!
>
> sorry for taking a bit longer to reply lately.
No problem.
>
> [...]
>
> >>> Sounds right, maybe it needs to go back to the old GUP solution, though,
> as
> >>> mmu notifiers are also mm-based not fd-based
On Wed, 28 Jun 2023 10:41:06 +0300
Pekka Paalanen wrote:
> On Wed, 28 Jun 2023 01:21:27 -0400
> Zack Rusin wrote:
>
> > From: Zack Rusin
> >
> > Atomic modesetting code lacked support for specifying mouse cursor
> > hotspots. The legacy kms DRM_IOCTL_MODE_CURSOR2 had support for setting
> > t
On Wed, 28 Jun 2023 01:21:27 -0400
Zack Rusin wrote:
> From: Zack Rusin
>
> Atomic modesetting code lacked support for specifying mouse cursor
> hotspots. The legacy kms DRM_IOCTL_MODE_CURSOR2 had support for setting
> the hotspot but the functionality was not implemented in the new atomic
> pa
On Tue, 27 Jun 2023 15:10:19 -0700
Abhinav Kumar wrote:
> On 6/27/2023 2:59 PM, Dmitry Baryshkov wrote:
> > On 28/06/2023 00:27, Jessica Zhang wrote:
> >>
> >>
> >> On 6/27/2023 12:58 AM, Pekka Paalanen wrote:
> >>> On Mon, 26 Jun 2023 16:02:50 -0700
> >>> Jessica Zhang wrote:
> >>>
>
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