On 09/05/2023 11:49, Jocelyn Falempe wrote:
On 08/05/2023 10:04, Thomas Zimmermann wrote:
Hi Jocelyn
Am 05.05.23 um 14:43 schrieb Jocelyn Falempe:
[cut]
+ /* pad each line to 32bits boundaries see section 4.5.7 of G200
Specification */
+ int width_padded = round_up(width * cpp, 4);
+
On 17/05/2023 15:41, Tom Rix wrote:
smatch reports
drivers/gpu/drm/mgag200/mgag200_drv.c:23:5: warning: symbol
'mgag200_modeset' was not declared. Should it be static?
This variable is only used in its defining file, so it should be static
Signed-off-by: Tom Rix
---
drivers/gpu/drm/mgag20
On Mon, May 22, 2023 at 03:57:12PM -0400, Rodrigo Vivi wrote:
We are not using the STAGING inside drm and the uAPI needs to be
in the acceptable form before we get merged upstream.
Is this a change from i915, where the force_probe protection
is sufficient?
The email exchange with Greg KH hi
Hi Neil,
On 22-May-23 13:35, neil.armstr...@linaro.org wrote:
> On 17/05/2023 07:48, Aradhya Bhatia wrote:
>> Hi Neil,
>>
>> On 16-May-23 12:54, Neil Armstrong wrote:
>>> On 09/05/2023 11:30, Aradhya Bhatia wrote:
From: Nikhil Devshatwar
input_bus_flags are specified in drm_bridge_
Hi,
On 2023/5/22 19:29, Jani Nikula wrote:
In general, do not use unsigned types in arithmethic to avoid negative
values, because most people will be tripped over by integer promotion
rules, and you'll get negative values anyway.
Here I'm sure about this,
but there are plenty unsigned types
Hi,
On 2023/5/22 23:01, Jani Nikula wrote:
On Mon, 22 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
Hi,
On 2023/5/22 20:13, Jani Nikula wrote:
On Mon, 22 May 2023, Sui Jingfeng <15330273...@189.cn> wrote:
Hi,
On 2023/5/22 19:29, Jani Nikula wrote:
On Thu, 18 May 2023, Sui Jingfeng <15
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:374: warning: expecting prototype for
vcn_v4_0_mc_resume_dpg_mode(). Prototype was for
vcn_v4_0_3_mc_resume_dpg_mode() instead.
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:631: warning: expecting prototype for
vcn_v4_0_ena
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:426: warning: expecting prototype for
sdma_v4_4_2_gfx_stop(). Prototype was for sdma_v4_4_2_inst_gfx_stop() instead.
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:457: warning: expecting prototype for
sdma_v4_4_2_rlc_stop()
On Mon, May 22, 2023 at 8:15 PM Bjorn Andersson
wrote:
>
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
> arm
2023년 5월 19일 (금) 오후 6:21, Andi Shyti 님이 작성:
> Hi Inki,
>
> > > > @@ -469,8 +469,6 @@ static int vidi_remove(struct platform_device
> *pdev)
> > > > if (ctx->raw_edid != (struct edid *)fake_edid_info) {
> > > > kfree(ctx->raw_edid);
> > > > ctx->raw_edid = NULL;
> > > > -
> >
./drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c: amdgpu_xcp.h is included more than
once.
Reported-by: Abaci Robot
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5281
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/dri
On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
Changes since v1:
- Withdrawn two pathes for a later consideration
- Changed dpu_encoder_phys_init() to return void (Abhinav)
- Added small sim
On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
There is no need to assign a result to temp varable just to return it
after a goto. Drop the temporary variable and goto and return the result
directly.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
From: Bjorn Andersson
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Moved a690 to adreno_is_a660_family(), which simplifies hw_init() and
ensured that pdc_in_aop got set.
- Dropped dyn
From: Bjorn Andersson
Add memory reservation for the zap-shader and enable the Adreno SMMU,
GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
Lenovo ThinkPad X13s.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- None
arch/arm64/bo
From: Bjorn Andersson
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
- Added missing compatible to &adreno_sm
This series introduces support for A690 in the DRM/MSM driver and
enables it for the two SC8280XP laptops.
Bjorn Andersson (3):
drm/msm/adreno: Add Adreno A690 support
arm64: dts: qcom: sc8280xp: Add GPU related nodes
arm64: dts: qcom: sc8280xp: Enable GPU related nodes
arch/arm64/boot/dts
In DPU 7.x and later, DSC/DCE enablement registers have been moved from
PINGPONG to INTF. Thus, add a DPU_INTF_DATA_COMPRESS feature flag that will
be set if the DATA_COMPRESS register is in the INTF block.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dp
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
To fix this, use DIV_ROUND_UP to divide hdisplay.
Suggested-by: Marijn Suijten
Fixes: 08802f515c3cf ("drm/msm/dsi: Add support for DS
This is a series of changes for DSI to enable command mode support
for DSC v1.2.
This includes:
1) Rounding up `hdisplay / 3` in dsc_timing_setup()
2) Adjusting pclk_rate to account for compression
3) Fixing incorrect uses of slice_count in DSI DSC calculations
4) Setting the DATA_COMPRESS bit wh
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/d
Currently, slice_count is being used to calculate word count and
pkt_per_line. Instead, these values should be calculated using slice per
packet, which is not the same as slice_count.
Slice count represents the number of slices per interface, and its value
will not always match that of slice per p
Add a DPU INTF op to set the DCE_DATA_COMPRESS bit to enable the
DCE/DSC 1.2 datapath
Note: For now, this op is called for command mode encoders only. Changes to
set DATA_COMPRESS for video mode encoders will be posted along with DSC
v1.2 support for DP.
Reviewed-by: Marijn Suijten
Signed-off-by
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
MAINTAINERS
between commit:
80e62bc8487b ("MAINTAINERS: re-sort all entries and fields")
from Linus' tree and commit:
0dd53308f74f ("MAINTAINERS: Add entry for Samsung S6D7AA0 LCD panel
controller driver")
from t
On Sun, 21 May 2023 at 10:03, Dmitry Baryshkov
wrote:
>
> On 15/05/2023 17:30, Rob Clark wrote:
> > From: Rob Clark
> >
> > Similar motivation to other similar recent attempt[1]. But with an
> > attempt to have some shared code for this. As well as documentation.
> >
> > It is probably a bit UM
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
> A few fixes/updates are required around the GSC memory allocation and it
> is easier to do them all at the same time. The changes are as follows:
alan:snip
> @@ -109,38 +110,21 @@ static int gsc_fw_load_prepare(struct intel_gsc_
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location o
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc()
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.
changes in v4:
-- delete DPU_DSC_H
There are two tiers of pending flush control, top levle and
individual hardware block. Currently only the top level of
flush mask is reset to 0 but the individual pending flush masks
of particular hardware blocks are left at their previous values,
eventually accumulating all possible bit values and
From: Abhinav Kumar
Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.
Changes in v9:
-- add MSM8998 and SC8180x to commit title
Changes in v10:
-- fix grammar at commit text
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter with
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and dpu_hw_
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the ops
The DSC CTL_FLUSH register should be programmed with the 22th bit
(DSC_IDX) to flush the DSC hardware blocks, not the literal value of
22 (which corresponds to flushing VIG1, VIG2 and RGB1 instead).
Changes in V12:
-- split this patch out of "separate DSC flush update out of interface"
Changes in
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]: https://patchwork.fr
Hi Tvrtko,
On Mon, May 22, 2023 at 12:59:28PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> User feedback indicates significant performance gains are possible in
> specific games with non default RPS up/down thresholds.
>
> Expose these tunables via sysfs which will allow users to ach
Hi Tvrtko,
On Mon, May 22, 2023 at 12:59:27PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In preparation for exposing via sysfs add helpers for managing rps
> thresholds.
>
> v2:
> * Force sw and hw re-programming on threshold change.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rodri
On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
> being enabled for all interfaces, even the ones which do not have TE
> block. Move this bit setting to INTF_DSI_T
The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
case. HDP related interrupts can not be enabled until internal_hpd is set
to true. At current implementation dp_display_config_hpd() will initialize
On Tue, 23 May 2023 at 01:32, Marijn Suijten
wrote:
>
> On 2023-05-22 04:19:45, Dmitry Baryshkov wrote:
> > On 22/05/2023 00:23, Marijn Suijten wrote:
> > > This SOFEF01-M Display-IC driver supports two modes with different
> > > compatibles to differentiate between slightly different physical siz
Hi Tvrtko,
On Mon, May 22, 2023 at 12:59:26PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Record the default values as preparation for exposing the sysfs controls.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rodrigo Vivi
Reviewed-by: Andi Shyti
Andi
Hi Tvrtko,
On Mon, May 22, 2023 at 12:59:25PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
> thresholds are invariant so lets move their setting to init time.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rodrigo Vivi
On Mon, May 22, 2023 at 03:35:13PM -0700, Kuogee Hsieh wrote:
>
>
> > > > -static void dp_display_config_hpd(struct dp_display_private *dp)
> > > > -{
> > > > -
> > > > - dp_display_host_init(dp);
> > > > - dp_catalog_ctrl_hpd_config(dp->catalog);
> > > > -
> > > > - /* Enable plug and
On 2023-05-22 18:30:08, Konrad Dybcio wrote:
> On 22.05.2023 03:19, Dmitry Baryshkov wrote:
> > On 22/05/2023 00:23, Marijn Suijten wrote:
> >> This SOFEF01-M Display-IC driver supports two modes with different
> >> compatibles to differentiate between slightly different physical sizes
> >> (panels
On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
There is no need to assign a result to temp varable just to return it
two lines below. Drop the temporary variable.
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
-static void dp_display_config_hpd(struct dp_display_private *dp)
-{
-
- dp_display_host_init(dp);
- dp_catalog_ctrl_hpd_config(dp->catalog);
-
- /* Enable plug and unplug interrupts only if requested */
- if (dp->dp_display.internal_hpd)
- dp_catalog_hpd_config_intr(dp->c
On 5/18/2023 7:38 PM, Dmitry Baryshkov wrote:
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 5/20/2023 1:01 PM, Dmitry Baryshkov wrote:
In dsi_calc_clk_rate_v2() there is no need to call dsi_get_pclk_rate().
This function has just been called (from dsi_calc_pclk()) and its
result is stored at msm_host->pixel_clk_rate. Use this variable
directly.
Hi Dmitry,
LGTM.
Reviewed-by: Je
On 5/22/2023 2:31 PM, Marijn Suijten wrote:
On 2023-05-22 13:30:21, Jessica Zhang wrote:
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.
Signed-off-by: Jessica Zhang
As discussed previously, this patch would apply a lot more cleanly on
top of:
https:
On 2023-05-22 04:19:45, Dmitry Baryshkov wrote:
> On 22/05/2023 00:23, Marijn Suijten wrote:
> > This SOFEF01-M Display-IC driver supports two modes with different
> > compatibles to differentiate between slightly different physical sizes
> > (panels) found on the Xperia 5 (6.1") and 10 II (6.0").
On 2023-05-23 01:01:50, Dmitry Baryshkov wrote:
> On 23/05/2023 00:56, Marijn Suijten wrote:
> > Title suggestion: s/globally/on non-TE/DSI (INTF) blocks
> >
> > On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
> >> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> >> INTF_SC7280_MA
On 23/05/2023 01:18, Marijn Suijten wrote:
On 2023-05-23 01:14:40, Dmitry Baryshkov wrote:
On Tue, 23 May 2023 at 00:45, Jessica Zhang wrote:
On 5/22/2023 1:44 PM, Marijn Suijten wrote:
On 2023-05-22 13:30:20, Jessica Zhang wrote:
Currently, when compression is enabled, hdisplay is reduce
Sorry for the delay, other topics delayed my response on this one.
On 5/18/2023 6:50 PM, Dmitry Baryshkov wrote:
On 19/05/2023 02:46, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to us
On 2023-05-23 00:45:27, Dmitry Baryshkov wrote:
> While reworking interrupts masks, it was easier to keep old
> MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
> to drop them and use unified symbol names.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Dmitry Baryshkov
On 2023-05-23 01:17:50, Dmitry Baryshkov wrote:
> On Tue, 23 May 2023 at 01:12, Marijn Suijten
> wrote:
> >
> > On 2023-05-23 00:45:25, Dmitry Baryshkov wrote:
> > > Declaring the mask of supported interrupts proved to be error-prone. It
> > > is very easy to add a bit with no corresponding backin
On Tue, 23 May 2023 at 01:15, Marijn Suijten
wrote:
>
> On 2023-05-23 00:45:26, Dmitry Baryshkov wrote:
> > Now as the list of the interrupts is constructed from the catalog
> > data, drop the mdss_irqs field from catalog.
> >
> > Reviewed-by: Neil Armstrong
> > Signed-off-by: Dmitry Baryshkov
>
On 2023-05-23 01:14:40, Dmitry Baryshkov wrote:
> On Tue, 23 May 2023 at 00:45, Jessica Zhang wrote:
> >
> >
> >
> > On 5/22/2023 1:44 PM, Marijn Suijten wrote:
> > > On 2023-05-22 13:30:20, Jessica Zhang wrote:
> > >> Currently, when compression is enabled, hdisplay is reduced via integer
> > >>
On Tue, 23 May 2023 at 01:12, Marijn Suijten
wrote:
>
> On 2023-05-23 00:45:25, Dmitry Baryshkov wrote:
> > Declaring the mask of supported interrupts proved to be error-prone. It
> > is very easy to add a bit with no corresponding backing block or to miss
> > the INTF TE bit. Replace this with lo
On 2023-05-23 00:45:26, Dmitry Baryshkov wrote:
> Now as the list of the interrupts is constructed from the catalog
> data, drop the mdss_irqs field from catalog.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Dmitry Baryshkov
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8 --
On Tue, 23 May 2023 at 00:45, Jessica Zhang wrote:
>
>
>
> On 5/22/2023 1:44 PM, Marijn Suijten wrote:
> > On 2023-05-22 13:30:20, Jessica Zhang wrote:
> >> Currently, when compression is enabled, hdisplay is reduced via integer
> >> division. This causes issues for modes where the original hdispl
On 2023-05-23 00:45:25, Dmitry Baryshkov wrote:
> Declaring the mask of supported interrupts proved to be error-prone. It
> is very easy to add a bit with no corresponding backing block or to miss
> the INTF TE bit. Replace this with looping over the enabled INTF blocks
> to setup the irq mask.
>
On 5/22/2023 2:45 PM, Jessica Zhang wrote:
On 5/22/2023 1:44 PM, Marijn Suijten wrote:
On 2023-05-22 13:30:20, Jessica Zhang wrote:
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple o
... for 7xxx?
On 2023-05-23 00:45:24, Dmitry Baryshkov wrote:
> There is no point in having a single enum (and a single array) for both
> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> enum and two IRQ address arrays.
>
> Signed-off-by: Dmitry Baryshkov
Really like this
On 23/05/2023 01:05, Bjorn Andersson wrote:
On Mon, May 22, 2023 at 02:31:32PM -0700, Kuogee Hsieh wrote:
The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
case. HDP related interrupts can not be
On 5/22/2023 1:47 PM, Marijn Suijten wrote:
Can you fit DPU >= 7.0 in the title?
Hi Marijn,
Sure.
On 2023-05-22 13:30:22, Jessica Zhang wrote:
Add DATA_COMPRESS feature flag to DPU INTF block.
Nit: repeating the title, perhaps you can reflow this with the second
paragraph?
Acked.
T
On Mon, May 22, 2023 at 02:31:32PM -0700, Kuogee Hsieh wrote:
> The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
> false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
> case. HDP related interrupts can not be enabled until internal_hpd is set
> to tr
On 23/05/2023 00:56, Marijn Suijten wrote:
Title suggestion: s/globally/on non-TE/DSI (INTF) blocks
On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
INTF_SC7280_MASK) results in this bit (and corrsponding operations)
being enabled f
On 2023-05-23 00:45:23, Dmitry Baryshkov wrote:
> Inline __intr_offset(), there is no point in having a separate oneline
> function for setting base block address.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/d
Title suggestion: s/globally/on non-TE/DSI (INTF) blocks
On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
> being enabled for all interfaces, even the ones which d
On Mon, 22 May 2023 14:34:18 -0700, Umesh Nerlige Ramappa wrote:
>
> On Mon, May 22, 2023 at 01:17:49PM -0700, Ashutosh Dixit wrote:
> > Clearing out report id and timestamp as means to detect unlanded reports
> > only works if report size is power of 2. That is, only when report size is
> > a sub-
On Mon, May 22, 2023 at 03:51:01PM -0500, Bjorn Andersson wrote:
> On Fri, Oct 08, 2021 at 03:38:21PM +0300, Heikki Krogerus wrote:
> > Hi,
> >
> > On Thu, Oct 07, 2021 at 09:15:12AM -0700, Bjorn Andersson wrote:
> > > The one thing that I still don't understand though is, if the typec_mux
> > > i
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 1 +
.../msm/disp/dpu1/catalog/dpu_7
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this with looping over the enabled INTF blocks
to setup the irq mask.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp
Now as the list of the interrupts is constructed from the catalog
data, drop the mdss_irqs field from catalog.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8
.../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h |
While reworking interrupts masks, it was easier to keep old
MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
to drop them and use unified symbol names.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h |
Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
INTF_SC7280_MASK) results in this bit (and corrsponding operations)
being enabled for all interfaces, even the ones which do not have TE
block. Move this bit setting to INTF_DSI_TE(), so that it is only
enabled for those INTF blocks wh
Inline __intr_offset(), there is no point in having a separate oneline
function for setting base block address.
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this static configuration with the irq mask
calculated from the HW catalog data.
Changes since v1:
- Enable dpu_caps::has_7xxx_
On 5/22/2023 1:44 PM, Marijn Suijten wrote:
On 2023-05-22 13:30:20, Jessica Zhang wrote:
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
To fix this, use DIV_ROUND_UP to divide
On Tue, 23 May 2023 at 00:31, Kuogee Hsieh wrote:
>
> The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
> false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
> case. HDP related interrupts can not be enabled until internal_hpd is set
> to true. At cu
On Mon, May 22, 2023 at 01:17:49PM -0700, Ashutosh Dixit wrote:
Clearing out report id and timestamp as means to detect unlanded reports
only works if report size is power of 2. That is, only when report size is
a sub-multiple of the OA buffer size can we be certain that reports will
land at the
The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to
false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller
case. HDP related interrupts can not be enabled until internal_hpd is set
to true. At current implementation dp_display_config_hpd() will initialize
On 2023-05-22 13:30:21, Jessica Zhang wrote:
> Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
> is enabled.
>
> Signed-off-by: Jessica Zhang
As discussed previously, this patch would apply a lot more cleanly on
top of:
https://lore.kernel.org/linux-arm-msm/20230520200
On 5/22/2023 2:01 PM, Marijn Suijten wrote:
On 2023-05-22 13:30:24, Jessica Zhang wrote:
Currently, slice_count is being used to calculate word count and
pkt_per_line. Instead, these values should be calculated using slice per
packet, which is not the same as slice_count.
Slice count represe
On 5/22/2023 1:54 PM, Marijn Suijten wrote:
How about: Enable INTF DATA_COMPRESS bit (on cmdmode) for DCE/DSC 1.2?
Hi Marijn,
Acked.
Drop parenthesis at your convenience.
On 2023-05-22 13:30:23, Jessica Zhang wrote:
Add a DPU INTF op to set DATA_COMPRESS register if the
DPU_INTF_DATA_C
On 2023-05-22 12:30:50, Kuogee Hsieh wrote:
> There are two tiers of pending flush control, main controller and
> individual hardware block. Currently only the main controller of
I would call "main controller" "top level" instead, but not sure how the
hardware manual calls this?
> flush mask is r
On 5/22/2023 2:35 AM, Jani Nikula wrote:
On Wed, 17 May 2023, Jessica Zhang wrote:
Add helper to get the integer value of drm_dsc_config.bits_per_pixel
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 7 +++
1 file changed, 7 inser
On 5/22/2023 2:37 AM, Jani Nikula wrote:
On Wed, 17 May 2023, Jessica Zhang wrote:
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display
On 2023-05-22 23:18:02, Dmitry Baryshkov wrote:
> On 22/05/2023 22:30, Kuogee Hsieh wrote:
> > DSC flush bit is the bit 22 of CTL flush register. BIT(22) is expected
> > to be written to CTL flush register to indicates that DSC is ready for
> > flush. However 0x22 (BIT(1) and BIT(5)) was written mi
One more suggestion: DSC slice_count*
On 2023-05-22 13:30:24, Jessica Zhan
- Marijn
On 2023-05-22 13:30:24, Jessica Zhang wrote:
> Currently, slice_count is being used to calculate word count and
> pkt_per_line. Instead, these values should be calculated using slice per
> packet, which is not the same as slice_count.
>
> Slice count represents the number of soft slices per interf
On 2023-05-22 22:52:40, Konrad Dybcio wrote:
>
>
> On 22.05.2023 22:44, Marijn Suijten wrote:
> > On 2023-05-22 13:30:20, Jessica Zhang wrote:
> >> Currently, when compression is enabled, hdisplay is reduced via integer
> >> division. This causes issues for modes where the original hdisplay is
>
On Mon, 22 May 2023 15:50:32 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove strl
On Mon, 22 May 2023 15:52:45 +, Azeem Shaikh wrote:
> strlcpy() reads the entire source buffer first.
> This read may exceed the destination size limit.
> This is both inefficient and can lead to linear read
> overflows if a source string is not NUL-terminated [1].
> In an effort to remove strl
How about: Enable INTF DATA_COMPRESS bit (on cmdmode) for DCE/DSC 1.2?
Drop parenthesis at your convenience.
On 2023-05-22 13:30:23, Jessica Zhang wrote:
> Add a DPU INTF op to set DATA_COMPRESS register if the
> DPU_INTF_DATA_COMPRESS feature is enabled. This bit needs to be set in
> order for D
On 22.05.2023 22:44, Marijn Suijten wrote:
> On 2023-05-22 13:30:20, Jessica Zhang wrote:
>> Currently, when compression is enabled, hdisplay is reduced via integer
>> division. This causes issues for modes where the original hdisplay is
>> not a multiple of 3.
>>
>> To fix this, use DIV_ROUND_U
On Fri, Oct 08, 2021 at 03:38:21PM +0300, Heikki Krogerus wrote:
> Hi,
>
> On Thu, Oct 07, 2021 at 09:15:12AM -0700, Bjorn Andersson wrote:
> > The one thing that I still don't understand though is, if the typec_mux
> > is used by the typec controller to inform _the_ mux about the function
> > to
Can you fit DPU >= 7.0 in the title?
On 2023-05-22 13:30:22, Jessica Zhang wrote:
> Add DATA_COMPRESS feature flag to DPU INTF block.
Nit: repeating the title, perhaps you can reflow this with the second
paragraph?
- Marijn
> In DPU 7.x and later, DSC/DCE enablement registers have been moved fr
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