https://bugzilla.kernel.org/show_bug.cgi?id=217278
--- Comment #6 from wendy.w...@intel.com ---
Earlier mainline v6.1 version ast driver also failed.
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https://bugzilla.kernel.org/show_bug.cgi?id=217278
--- Comment #5 from wendy.w...@intel.com ---
Created attachment 304076
--> https://bugzilla.kernel.org/attachment.cgi?id=304076&action=edit
Failure log in mainline v6.1
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https://bugzilla.kernel.org/show_bug.cgi?id=217278
wendy.w...@intel.com changed:
What|Removed |Added
Attachment #304074|0 |1
is obsolete|
https://bugzilla.kernel.org/show_bug.cgi?id=217278
--- Comment #3 from wendy.w...@intel.com ---
Created attachment 304074
--> https://bugzilla.kernel.org/attachment.cgi?id=304074&action=edit
Failure log in mainline v6.1
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From: Gan Gecen
Smatch reports:
drivers/gpu/drm/tiny/bochs.c:290 bochs_hw_init()
warn: 'bochs->mmio' from ioremap() not released on
lines: 246,250,254.
In the function bochs_load() that calls bochs_hw_init()
only, if bochs_hw_init(dev) returns -ENODEV(-19), it
will jumps
On 01/04/2023 20:19, André Morishita wrote:
> Convert the Maxim Integrated MAX98371 audio codec bindings to DT schema.
>
> Signed-off-by: André Morishita
> ---
> Changes in v3:
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
Convert the Maxim Integrated MAX98371 audio codec bindings to DT schema.
Signed-off-by: André Morishita
---
Changes in v3:
- Make commit message and subject as v1 with ASoC subject prefix
Changes in v2:
- Generic node names - codec (Krzysztof)
- Drop label max98371 (Krzysztof)
- Add s
https://lore.kernel.org/r/20230330083205.12621-7-tzimmermann%40suse.de
patch subject: [PATCH 6/6] drm/omapdrm: Implement fbdev emulation as in-kernel
client
config: arm-randconfig-r046-20230401
(https://download.01.org/0day-ci/archive/20230402/202304020128.epl6d3zl-...@intel.com/config)
compi
On Fri, Mar 31, 2023 at 4:30 PM Nathan Chancellor wrote:
>
> On Fri, Mar 31, 2023 at 03:14:30PM -0700, Rob Clark wrote:
> > On Fri, Mar 31, 2023 at 1:44 PM Nathan Chancellor wrote:
> > >
> > > Hi Rob,
> > >
> > > On Wed, Mar 08, 2023 at 07:53:02AM -0800, Rob Clark wrote:
> > > > From: Rob Clark
From: Rob Clark
This should fix a crash that was reported on ast (and possibly other
drivers which do not initialize vblank).
fbcon: Taking over console
Unable to handle kernel NULL pointer dereference at virtual address
0074
Mem abort info:
ESR = 0x9604
Hi Andrzej,
Le vendredi 31 mars 2023 à 11:40 +0200, Andrzej Pietrasiewicz a écrit :
> Hi Paul,
>
> W dniu 22.03.2023 o 10:21, Paul Cercueil pisze:
> > Hi,
> >
> > This small patchset adds three new IOCTLs that can be used to
> > attach,
> > detach, or transfer from/to a DMABUF object.
> >
> > C
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset lin
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
Reviewed-b
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 47 +
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is
done in a6xx_bus_clear_pending_transactions(), but for the GMU-less
ones we have to do it *somewhere*. Unhalting both side by side sounds
like a good plan and
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno
A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
a
These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 4 ins
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat thes
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat thes
v5 -> v6:
- Rebase on 8ead96783163 ("drm/msm/gpu: Move BO allocation out of hw_init")
(Add .ucode_load to funcs_gmuwrapper)
- Drop A6[45]0 speedbin deps, merged into msm-next
Dependencies:
-
https://lore.kernel.org/linux-arm-msm/20230330231517.2747024-1-konrad.dyb...@linaro.org/
(to work prope
Recently I contributed the switch to OPP API for all Adreno generations.
I did however also skip over the fact that GPUs with a GMU don't specify
a core clock of any kind in the GPU node. While that didn't break
anything, it did introduce unwanted spam in the dmesg:
adreno 500.gpu: error -ENOE
asOn Sat, Apr 1, 2023 at 1:27 AM Fabio Estevam wrote:
>
> From: Jagan Teki
>
> Samsung MIPI DSIM bridge can be found on Exynos and NXP's
> i.MX8M Mini and Nano SoC's.
>
> Convert exynos_dsim.txt to yaml.
Thanks for rebasing this.
>
> Used the example node from latest Exynos SoC instead of
> th
On 31/03/2023 21:49, Jessica Zhang wrote:
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Changes in v2:
- Renamed det_thresh_flatness to flatness_det_thresh
- Set initial_scale_value directly in helper
Signed-off-by: J
On 31/03/2023 20:21, Rob Herring wrote:
> Cleanup bindings dropping unneeded quotes. Once all these are fixed,
> checking for this can be enabled in yamllint.
>
> Signed-off-by: Rob Herring
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 01/04/2023 05:57, André Morishita wrote:
> Improve Maxim Integrated MAX98371 audio codec bindings DT schema conversion
Your patch changed much more than your commit log is saying. I don't
understand why. Previous subject was better than this, I only commented
on missing prefix.
Commit msg now
On 01/04/2023 03:57, Abhinav Kumar wrote:
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
From: Konrad Dybcio
These blocks are of variable length on different SoCs. Set the
correct values where I was able to retrieve it from downstream
DTs and leave the old defaults (0x1c8 for sspp and 0x280 f
Hi Andrew
>
>
> Okay, will split for v2.
>
>
Was there a follow-up v2 of this patchset? AFAICT this series did not
make it into the mainline kernel.
Do you have any plans to work on it? If not I would like to help out
as we have a use case where we want to
use a dma-buf sram exporter.
--
greet
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. The 'D' in DCLK actually stands for
'Data' according to Allwinner's manuals. The clock is mostly referred to
as dclk throughout this driver already anyway, so stick with that.
Signed-off-by: R
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbrebiation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/sun5i.dtsi
In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane
bit rate.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +-
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbrebiation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/sun5i.dtsi
With bpp bits per pixel transmitted over n DSI lanes, the target DCLK
rate for a given pixel clock is obtained as follows:
DCLK rate = 1/4 * bpp / n * pixel clock
Effect of this change can be observed through the rate of Vblank IRQs
which should now match refresh rate implied by set display mode.
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