From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out its life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a defau
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by: F
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line. CT
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
Fei Yang (7):
drm/i915/mtl: Define MOCS and PAT tables for MTL
drm/i915/mtl: workaround coherency issue for Media
drm/i915/mtl:
From: Fei Yang
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for ADM/L4 cache calls a
MOCS/PAT table update.
Also add PTE encode functions for MTL as it has different PAT
index definition than previous platforms.
BSpec: 44509, 45101, 44235
Cc:
Improve Maxim Integrated MAX98371 audio codec bindings DT schema conversion
Signed-off-by: André Morishita
---
Changes in v2
- Generic node names - codec (Krzysztof)
- Drop label max98371 (Krzysztof)
- Add sound-dai-cells in example (Krzysztof)
.../devicetree/bindings/sound/max98371.txt| 17
Hi Mark,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next-fixes]
[also build test ERROR on linus/master v6.3-rc4]
[cannot apply to drm-misc/drm-misc-next drm-intel/for-linux-next drm/drm-next
next-20230331]
[If your patch is applied to the wrong
On Fri, 31 Mar 2023 19:00:49 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> @@ -478,20 +507,15 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
> *slpc, u32 val)
> val > slpc->max_freq_softlimit)
> return -EINVAL;
>
> + /* Ignore efficient freq if lower min freq
On Fri, 31 Mar 2023 03:23:33 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> > @@ -385,8 +395,22 @@ static int
> > hwm_power_max_write(struct hwm_drvdata *ddat, long val)
> > {
> > struct i915_hwmon *hwmon = ddat->hwmon;
> > + intel_wakeref_t wakeref;
> > u32 nval;
> > + if (val == PL
On ATSM the PL1 limit is disabled at power up. The previous uapi assumed
that the PL1 limit is always enabled and therefore did not have a notion of
a disabled PL1 limit. This results in erroneous PL1 limit values when the
PL1 limit is disabled. For example at power up, the disabled ATSM PL1 limit
SLPC enables use of efficient freq at init by default. It is
possible for GuC to request frequencies that are higher than
the 'software' max if user has set it lower than the efficient
level.
Scenarios/tests that require strict fixing of freq below the efficient
level will need to disable it throu
From: Hans de Goede
[ Upstream commit 03aecb1acbcd7a660f97d645ca6c09d9de27ff9d ]
Like the Windows Lenovo Yoga Book X91F/L the Android Lenovo Yoga Book
X90F/L has a portrait 1200x1920 screen used in landscape mode,
add a quirk for this.
When the quirk for the X91F/L was initially added it was wr
From: Hans de Goede
[ Upstream commit 03aecb1acbcd7a660f97d645ca6c09d9de27ff9d ]
Like the Windows Lenovo Yoga Book X91F/L the Android Lenovo Yoga Book
X90F/L has a portrait 1200x1920 screen used in landscape mode,
add a quirk for this.
When the quirk for the X91F/L was initially added it was wr
From: Hans de Goede
[ Upstream commit 03aecb1acbcd7a660f97d645ca6c09d9de27ff9d ]
Like the Windows Lenovo Yoga Book X91F/L the Android Lenovo Yoga Book
X90F/L has a portrait 1200x1920 screen used in landscape mode,
add a quirk for this.
When the quirk for the X91F/L was initially added it was wr
From: Jane Jian
[ Upstream commit e06bfcc1a1c41bcb8c31470d437e147ce9f0acfd ]
sriov needs to enter/exit safe mode in update umd p state
add the cg flag to let it enter or exit while needed
Signed-off-by: Jane Jian
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
From: YuBiao Wang
[ Upstream commit 033c56474acf567a450f8bafca50e0b610f2b716 ]
[Why]
For engines not supporting soft reset, i.e. VCN, there will be a failed
ib test before mode 1 reset during asic reset. The fences in this case
are never signaled and next time when we try to free the sa_bo, kern
From: Tong Liu01
[ Upstream commit 4eb0b49a0ad3e004a6a65b84efe37bc7e66d560f ]
[why]
when gfx do soft reset, mes will also do reset, if mes is not
resumed when do recover from soft reset, mes is unable to respond
in later sequence
[how]
resume mes when do gfx post soft reset
Signed-off-by: Tong
From: Hans de Goede
[ Upstream commit 03aecb1acbcd7a660f97d645ca6c09d9de27ff9d ]
Like the Windows Lenovo Yoga Book X91F/L the Android Lenovo Yoga Book
X90F/L has a portrait 1200x1920 screen used in landscape mode,
add a quirk for this.
When the quirk for the X91F/L was initially added it was wr
From: Jane Jian
[ Upstream commit e06bfcc1a1c41bcb8c31470d437e147ce9f0acfd ]
sriov needs to enter/exit safe mode in update umd p state
add the cg flag to let it enter or exit while needed
Signed-off-by: Jane Jian
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
From: Tong Liu01
[ Upstream commit 4eb0b49a0ad3e004a6a65b84efe37bc7e66d560f ]
[why]
when gfx do soft reset, mes will also do reset, if mes is not
resumed when do recover from soft reset, mes is unable to respond
in later sequence
[how]
resume mes when do gfx post soft reset
Signed-off-by: Tong
From: YuBiao Wang
[ Upstream commit 033c56474acf567a450f8bafca50e0b610f2b716 ]
[Why]
For engines not supporting soft reset, i.e. VCN, there will be a failed
ib test before mode 1 reset during asic reset. The fences in this case
are never signaled and next time when we try to free the sa_bo, kern
From: Hans de Goede
[ Upstream commit 03aecb1acbcd7a660f97d645ca6c09d9de27ff9d ]
Like the Windows Lenovo Yoga Book X91F/L the Android Lenovo Yoga Book
X90F/L has a portrait 1200x1920 screen used in landscape mode,
add a quirk for this.
When the quirk for the X91F/L was initially added it was wr
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
UBWC and highest bank settings differ slightly between different DPU
units of the same generation, while the dpu_caps and dpu_mdp_cfg are
much more stable. To ease configuration reuse move ubwc_swizzle and
highest_bank_bit data to separate structur
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
Fix several leftover _pp strutures and mark them as const, making all hw
catalog fit into the rodata section.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
DSC hw catalog data is not supposed to be changed, so mark it as const
data.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 3/30/2023 2:52 PM, Dmitry Baryshkov wrote:
From: Konrad Dybcio
These blocks are of variable length on different SoCs. Set the
correct values where I was able to retrieve it from downstream
DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
intf) otherwise.
Signed-off-by: Konrad
Hi Mark,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next-fixes]
[also build test WARNING on drm/drm-next linus/master v6.3-rc4 next-20230331]
[cannot apply to drm-misc/drm-misc-next drm-intel/for-linux-next]
[If your patch is applied to the
On Fri, Mar 31, 2023 at 12:39 AM Karol Herbst wrote:
>
> This allows us to advertise more modes especially on HDR displays.
>
> Fixes using 4K@60 modes on my TV and main display both using a HDMI to DP
> adapter. Also fixes similiar issues for users running into this.
>
> Cc: sta...@vger.kernel.or
0x50/0x70
> > [ 20.550987] do_fbcon_takeover+0x74/0xf8
> > [ 20.550989] do_fb_registered+0x13c/0x158
> > [ 20.550992] fbcon_register_existing_fbs+0x78/0xc0
> > [ 20.550995] process_one_work+0x1ec/0x478
> > [ 20.551000] worker_thread+0x74/0x418
> >
From: John Harrison
First release of GuC for Meteorlake.
NB: As this is still pre-release and likely to change, use explicit
versioning for now. The official, full release will use reduced
version naming.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file
Hi Dave, Daniel,
More new stuff for 6.4.
The following changes since commit d36d68fd1925d33066d52468b7c7c6aca6521248:
Merge tag 'drm-habanalabs-next-2023-03-20' of
https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into drm-next
(2023-03-22 10:35:46 +1000)
are available in the Gi
From: John Harrison
First release of GuC for Meteorlake.
NB: As this is still pre-release and likely to change, use explicit
versioning for now. The official, full release will use reduced
version naming.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file
/0x20
> [ 20.551011] Code: f944 b9409013 f940a082 9ba30a73 (b9407662)
> [ 20.551013] ---[ end trace ]---
>
> If there is any additional information that I can provide or patches I
> can test, I am more than happy to do so.
>
&g
From: Sean Paul
Add the register ranges required for HDCP key injection and
HDCP TrustZone interaction as described in the dt-bindings for the
sc7180 dp controller.
Reviewed-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v3:
-Split off into a new patc
From: Sean Paul
Add HDCP 1.x support to msm DP bridges using the new HDCP
helpers.
Cc: Stephen Boyd
Reviewed-by: Stephen Boyd
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v2:
-Squash [1] into this patch with the following changes (Stephen)
-Update the sc7180 dtsi fi
From: Sean Paul
The shim functions return error codes, but they are discarded in
intel_hdcp.c. This patch plumbs the return codes through so they are
properly handled.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v2:
-Non
From: Sean Paul
Now that all of the HDCP 1.x logic has been migrated to the central HDCP
helpers, use it in the i915 driver.
The majority of the driver code for HDCP 1.x will live in intel_hdcp.c,
however there are a few helper hooks which are connector-specific and
need to be partially or fully
From: Sean Paul
Add the bindings for the MSM DisplayPort HDCP registers
which are required to write the HDCP key into the display controller as
well as the registers to enable HDCP authentication/key
exchange/encryption.
Cc: Rob Herring
Cc: Stephen Boyd
Reviewed-by: Rob Herring
Reviewed-by: D
From: Sean Paul
Instead of forcing a modeset in the hdcp atomic check, rename to
drm_hdcp_has_changed and return true if the content protection value
is changing and let the driver decide whether a modeset is required or not.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean
From: Sean Paul
Expand upon the HDCP helper library to manage HDCP enable, disable, and check.
Previous to this patch, the majority of the state management and sink
interaction is tucked inside the Intel driver with the understanding
that once a new platform supported HDCP we could make good dec
From: Sean Paul
Stick all of the setup for HDCP into a dedicated function. No functional
change, but this will facilitate moving HDCP logic into helpers.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Change-Id: Ib358a503fa4520d072e477f708f1705b19f1c4fc
Signed-off-by: Sean Paul
---
Changes
From: Sean Paul
Update the connector's property value in 2 cases which were
previously missed:
1- Content type changes. The value should revert back to DESIRED from
ENABLED in case the driver must re-authenticate the link due to the
new content type.
2- Userspace sets value to DESIRED whi
From: Sean Paul
Move the hdcp atomic check from i915 to drm_hdcp so other
drivers can use it. No functional changes, just cleaned up some of the
code when moving it over.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Sean Paul
Signed-off-by: Mar
Hi all,
This is v7 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v8.
Patches 1-4 focus on moving the common HDCP helpers to common DRM.
This introduces a slight change in the original intel flow
as it splits the unique driver protoc
On Mon, Mar 27, 2023 at 09:59:55AM -0700, Matt Roper wrote:
On Thu, Mar 23, 2023 at 10:17:52PM -0700, Lucas De Marchi wrote:
The rev field is always 0 so it ends up never used. In i915 it was
introduced because of CML: up to rev 5 it reuses the guc and huc
firmware blobs from KBL. After that the
On Fri, Mar 31, 2023 at 4:02 PM Felix Kuehling wrote:
>
> There is a subsequent patch where amdgpu directly calls ttm_pool_init to
> create pools per NUMA node. That will depend on the updated function
> signature.
Then we probably want to take this through amdgpu then.
Alex
>
> Regards,
>F
On Fri, Mar 31, 2023 at 01:47:20PM -0700, Matt Roper wrote:
On Fri, Mar 31, 2023 at 07:22:06AM -0600, Lucas De Marchi wrote:
On Mon, Mar 27, 2023 at 10:02:38AM -0700, Matt Roper wrote:
> On Thu, Mar 23, 2023 at 10:17:53PM -0700, Lucas De Marchi wrote:
> > Platform order is important when looping
Reviewed-by: Lyude Paul
On Fri, 2023-03-31 at 00:39 +0200, Karol Herbst wrote:
> This allows us to advertise more modes especially on HDR displays.
>
> Fixes using 4K@60 modes on my TV and main display both using a HDMI to DP
> adapter. Also fixes similiar issues for users running into this.
>
On Fri, Mar 31, 2023 at 07:22:06AM -0600, Lucas De Marchi wrote:
> On Mon, Mar 27, 2023 at 10:02:38AM -0700, Matt Roper wrote:
> > On Thu, Mar 23, 2023 at 10:17:53PM -0700, Lucas De Marchi wrote:
> > > Platform order is important when looping through the list of guc
> > > firmware blobs since we us
--[ end trace ]---
If there is any additional information that I can provide or patches I
can test, I am more than happy to do so.
Cheers,
Nathan
# bad: [4b0f4525dc4fe8af17b3daefe585f0c2eb0fe0a5] Add linux-next specific files
for 20230331
# good: [b2bc47e9b2011a183f9d3d345
clang with W=1 reports
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c:221:7: error: variable
'loc' set but not used [-Werror,-Wunused-but-set-variable]
u32 loc, sig, cnt, *meta;
^
This variable is not used so remove it.
Signed-off-by: Tom Rix
---
drivers/gpu
Hi,
On Thu, Mar 30, 2023 at 8:02 PM Pin-yen Lin wrote:
>
> The default hpd_wait_us in panel_edp.c is 2 seconds. This makes the
> sleep time in the polling of _ps8640_wait_hpd_asserted become 200ms.
> Change it to a constant 20ms to speed up the function.
Ah, I see why I never ran into this. All
There is a subsequent patch where amdgpu directly calls ttm_pool_init to
create pools per NUMA node. That will depend on the updated function
signature.
Regards,
Felix
On 2023-03-31 15:17, Alex Deucher wrote:
On Fri, Mar 31, 2023 at 2:54 AM Christian König
wrote:
Should I push this to dr
From: Jagan Teki
Samsung MIPI DSIM bridge can be found on Exynos and NXP's
i.MX8M Mini and Nano SoC's.
Convert exynos_dsim.txt to yaml.
Used the example node from latest Exynos SoC instead of
the one used in legacy exynos_dsim.txt.
Signed-off-by: Jagan Teki
Signed-off-by: Fabio Estevam
---
On Sun, Mar 26, 2023 at 10:42:21PM +0200, Krzysztof Kozlowski wrote:
> Panels are supposed to have one port (defined in panel-common.yaml
> binding):
>
> px30-evb.dtb: panel@0: 'port' does not match any of the regexes:
> 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../bin
On Sun, 26 Mar 2023 18:47:00 +0200, Krzysztof Kozlowski wrote:
> The device comes with DCX pin which is already used in
> canaan/sipeed_maixduino.dts (although not in Linux driver).
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../devicetree/bindings/display/panel/sitronix,st7789v.yaml | 4
On Fri, Mar 31, 2023 at 01:40:27PM +0200, Stanislaw Gruszka wrote:
> From: Karol Wachowski
>
> VPU on MTL has hardware optimizations and does not require 10ms
> D0 - D3hot transition delay imposed by PCI specification.
PCIe r6.0, sec 5.9.
> The delay removal is traditionally done by adding PCI
On Fri, Mar 31, 2023 at 2:54 AM Christian König
wrote:
>
> Should I push this to drm-misc-next or do we take it through
> amd-staging-drm-next?
I think either way is fine. We can carry it internally as needed for
testing if you want to commit it to drm-misc-next. I don't think
there are any dir
Use the correct calculations for eol_byte_num and pkt_per_line.
Currently, pkt_per_line is calculated by dividing slice_per_intf by
slice_count. This is incorrect, as slice_per_intf should be divided by
slice_per_pkt, which is not always equivalent to slice_count as it is
possible for there to be
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Changes in V2:
- *_calculate_initial_scale_value --> *_set_initial_scale_value
- Split pkt_per_line and eol_byte_num changes to a separate patch
- Moved pclk_per_line calculation to hdisplay adjustment in `if (dsc)`
block of dsi_update
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Changes in v2:
- Moved files up to msm/ directory
- Dropped get_comp_ratio() helper
- Used drm_int2fixp() to convert to integers to fp
- Style changes to improve readability
- Dropped unused bpp variable
Use the DRM DSC helper for det_thresh_flatness to match downstream
implementation and the DSC spec.
Changes in V2:
- Added a Fixes tag
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 4 +++-
1 file chan
There are some overlap in calculations for MSM-specific DSC variables between
DP and DSI. In addition, the calculations for initial_scale_value and
det_thresh_flatness that are defined within the DSC 1.2 specifications, but
aren't yet included in drm_dsc_helper.c.
This series moves these calcul
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Jessica Zhang
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 +-
1 file changed, 5 inser
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Changes in v2:
- Renamed det_thresh_flatness to flatness_det_thresh
- Set initial_scale_value directly in helper
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_d
Hi Xiao,
Le lundi 30 janvier 2023 à 20:38 +0800, Xiaoyong Lu a écrit :
> Add mediatek av1 decoder linux driver which use the stateless API in
> MT8195.
>
I think this no longer needs an RFC tag. While at it, it would be nice for the
maintainer to rebase on top if latest media stage (you still ha
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.
Signed-off-by: Rob Herring
---
.../devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml | 6 +++---
.../bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml | 6 +++---
.../bindin
Hi Lee,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-misc/drm-misc-next next-20230331]
[cannot apply to drm-intel/for-linux-next-fixes lee-leds/for-leds-next
linus/master v6.3-rc4]
[If your patch is
On 09/03/2023 15:23, Alexandre Mergnat wrote:
Add compatible for the MT8365 SoC.
Signed-off-by: Alexandre Mergnat
Applied, thanks!
---
Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindin
clang with W=1 reports
drivers/gpu/drm/qxl/qxl_ioctl.c:149:14: error: variable
'num_relocs' set but not used [-Werror,-Wunused-but-set-variable]
int i, ret, num_relocs;
^
This variable is not used so remove it.
Signed-off-by: Tom Rix
---
drivers/gpu/drm/qxl/qxl_ioct
On Fri, Dec 2, 2022 at 9:24 AM Arvind Yadav wrote:
>
> This reverts commit e4dc45b1848bc6bcac31eb1b4ccdd7f6718b3c86.
>
> This is causing instability on Linus' desktop, and Observed System
> hung when running MesaGL benchmark or VK CTS runs.
>
> netconsole got me the following oops:
>
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.c:1700:6: error: variable
'num_of_active_display' set but not used [-Werror,-Wunused-but-set-variable]
int num_of_active_display = 0;
^
This variable is not used so remove it.
Signed-off-by: Tom Rix
---
Hi Dave, Daniel,
Small update. Slow week. Felt like sending a pull request regardless.
drm-misc-next-2023-03-31:
drm-misc-next for v6.4-rc1:
Cross-subsystem Changes:
- DT bindings update for adding Mali MT81xx devices.
- Assorted DT binding updates.
Core Changes:
- Documentation update to sche
Hi
Reviewed-by: Thomas Zimmermann
for the whole patchset.
Best regards
Thomas
Am 31.03.23 um 16:48 schrieb Geert Uytterhoeven:
Hi all,
Currently, there are two drivers for the LCD controller on Renesas
SuperH-based and ARM-based SH-Mobile and R-Mobile SoCs:
1. sh_mobile_lcdcfb, u
On venerdì 31 marzo 2023 13:30:20 CEST Tvrtko Ursulin wrote:
> On 31/03/2023 05:18, Ira Weiny wrote:
> > Zhao Liu wrote:
> >> From: Zhao Liu
> >>
> >> The use of kmap_atomic() is being deprecated in favor of
> >> kmap_local_page()[1], and this patch converts the calls from
> >> kmap_atomic() to k
Hi Lee,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-misc/drm-misc-next next-20230331]
[cannot apply to drm-intel/for-linux-next-fixes lee-leds/for-leds-next
linus/master v6.3-rc4]
[If your patch is
Hi,
I'm noticed you patch, interesting!
On 2023/3/29 13:26, Gencen Gan wrote:
From: Gan Gecen
Smatch reports:
drivers/gpu/drm/tiny/bochs.c:290 bochs_hw_init()
warn: 'bochs->mmio' from ioremap() not released on
lines: 246,250,254.
In the function bochs_load() that cal
On 3/30/23 20:10, Tom Rix wrote:
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15:
error: variable
'average_render_time_in_us' set but not used
[-Werror,-Wunused-but-set-variable]
unsigned int average_render_time_in_us = 0;
On Fri, 31 Mar 2023 at 16:59, Vinod Polimera wrote:
>
> In certain CPU stress conditions, there can be a delay in scheduling commit
> work and it was observed that PSR commit from a different work queue was
> scheduled. Avoid these commits as display is already in PSR mode.
>
> Signed-off-by: Vino
Hi Chun-Kuang Hu,
On 13/03/2023 16:02, Chun-Kuang Hu wrote:
Hi, Alexandre:
Alexandre Mergnat 於 2023年3月9日 週四 下午10:23寫道：
Display Adaptive Ambient Light for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Reviewed-by: Chun-Kuang Hu
I'm a bit puzzled
Replace the printing of hexadecimal fourcc format codes by
pretty-printed format names, using the "%p4cc" format specifier.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/shmobile/shmob_drm_crtc.c | 4 ++--
drivers/gpu/drm/shmobile/shmob_drm_kms.c | 4 ++--
2 files changed, 4 insertions(
Set up generic fbdev emulation, to enable support for the Linux console.
Use 16 as the preferred depth, as that is a good compromise between
colorfulness and resource utilization, and the default of the fbdev
driver.
Suggested-by: Laurent Pinchart
Signed-off-by: Geert Uytterhoeven
---
drivers/
The LCD Controller supported by the drm-shmob driver is not only present
on SuperH SH-Mobile SoCs, but also on Renesas ARM SH/R-Mobile SoCs.
Make its option visible, so the user can enable support for it.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/shmobile/Kconfig | 2 +-
1 file chang
DRM_FORMAT_XRGB aka XR24 is the modus francus of DRM, and should be
supported by all drivers.
The handling for DRM_FORMAT_XRGB is similar to DRM_FORMAT_ARGB,
just ignore the alpha channel.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/shmobile/shmob_drm_crtc.c | 1 +
driver
The SH-Mobile DRM driver uses the legacy drm_crtc_init(), which
advertizes only the formats in safe_modeset_formats[] (XR24 and AR24) as
being supported.
Switch to drm_crtc_init_with_planes(), and advertize all supported
(A)RGB modes, so we can use RGB565 as the default mode for the console.
Sign
Hi all,
Currently, there are two drivers for the LCD controller on Renesas
SuperH-based and ARM-based SH-Mobile and R-Mobile SoCs:
1. sh_mobile_lcdcfb, using the fbdev framework,
2. shmob_drm, using the DRM framework.
However, only the former driver can be used, as all platform support
On 31/03/2023 15:16, Andrzej Hajda wrote:
From: Chris Wilson
There may be a disconnect between the GT used by the engine and the GT
used for the VM, requiring us to hold a wakeref on both while the GPU is
active with this request.
v2: added explanation to __queue_and_release_pm
Signed-off-b
On Fri, 31 Mar 2023 at 16:59, Vinod Polimera wrote:
>
> Certain flags like dirty_fb will be updated into the plane state
> during crtc atomic_check. Allow those updates during PSR commit.
>
> Reported-by: Bjorn Andersson
> Link: https://lore.kernel.org/all/20230326162723.3lo6pnsfdwzsvbhj@ripper/
On Fri, 31 Mar 2023 at 16:59, Vinod Polimera wrote:
>
> While in virtual terminal mode with PSR enabled, there will be
> no atomic commits triggered without dirty_fb being set. This
> will create a notion of no screen update. Allow atomic commit
> when dirty_fb ioctl is issued, so that it can trig
On 09/03/2023 15:23, Alexandre Mergnat wrote:
According to the mtk-mutex.c driver and the SoC DTS, the clock isn't
required to work properly for some of MTK SoC. Improve the clock
requirement by adding a condition which is function to the compatible.
Signed-off-by: Alexandre Mergnat
Applie
From: Chris Wilson
There may be a disconnect between the GT used by the engine and the GT
used for the VM, requiring us to hold a wakeref on both while the GPU is
active with this request.
v2: added explanation to __queue_and_release_pm
Signed-off-by: Chris Wilson
[ahajda: removed not-yet-upst
In certain CPU stress conditions, there can be a delay in scheduling commit
work and it was observed that PSR commit from a different work queue was
scheduled. Avoid these commits as display is already in PSR mode.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/msm_atomic.c | 3 +++
1 fi
Certain flags like dirty_fb will be updated into the plane state
during crtc atomic_check. Allow those updates during PSR commit.
Reported-by: Bjorn Andersson
Link: https://lore.kernel.org/all/20230326162723.3lo6pnsfdwzsvbhj@ripper/
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu
While in virtual terminal mode with PSR enabled, there will be
no atomic commits triggered without dirty_fb being set. This
will create a notion of no screen update. Allow atomic commit
when dirty_fb ioctl is issued, so that it can trigger a PSR exit
and shows update on the screen.
Reported-by: Bj
while in virtual terminal with PSR enabled, there will be
no atomic commits triggered resulting in no screen update.
Update the dirtyfb flag into plane state during atomic check
to flush the pixel data explicitly.
Avoid scheduling PSR commits from different work queues while
running in PSR mode a
On Mon, Mar 27, 2023 at 10:02:38AM -0700, Matt Roper wrote:
On Thu, Mar 23, 2023 at 10:17:53PM -0700, Lucas De Marchi wrote:
Platform order is important when looping through the list of guc
firmware blobs since we use it to prevent loading a blob for a newer
platform onto an older one. Move PVC
On 2023-03-31 01:59, Christian König wrote:
> Am 31.03.23 um 02:06 schrieb Danilo Krummrich:
>> It already happend a few times that patches slipped through which
>> implemented access to an entity through a job that was already removed
>> from the entities queue. Since jobs and entities might have
1 - 100 of 203 matches
Mail list logo
