Hi Rasmus,
Am Montag, 30. Januar 2023, 13:45:38 CET schrieb Rasmus Villemoes:
> On 27/01/2023 12.30, Marek Vasut wrote:
> > On 1/27/23 12:04, Jagan Teki wrote:
> >>> Thanks, but that's exactly what I'm doing, and I don't see any
> >>> modification of imx8mp.dtsi in that branch. I'm basically looki
On Tue, Jan 31, 2023 at 01:03:05PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the usb tree got a conflict in:
>
> drivers/gpu/drm/i915/gt/intel_engine_cs.c
>
> between commit:
>
> 5bc4b43d5c6c ("drm/i915: Fix up locking around dumping requests lists")
>
> from
Hi Piccoli,
I agree with Alex's point, using ring->sched.name for such check is not a good
way. BTW, can you please attach a full dmesg long in bad case to help me
understand more?
Regards,
Guchun
-Original Message-
From: Alex Deucher
Sent: Tuesday, January 31, 2023 6:30 AM
To: Guilh
Hi Rusin,
Thank you for your timely response. I tested that this bug is not
reproducible in v6.2-rc5 yesterday.
On 1/31/23 03:54, Zack Rusin wrote:
On Tue, 2023-01-31 at 00:36 +0800, Keyu Tao wrote:
!! External Email
Hi vmwgfx maintainers,
An out-of-bound access in vmwgfx specific framebuf
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
There is no need to pass full dpu_hw_pipe_cfg instance to
_dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 -
drivers/gpu/drm/msm/dis
From: Zack Rusin
Problem with explicit placement selection in vmwgfx is that by the time
the buffer object needs to be validated the information about which
placement was supposed to be used is lost. To workaround this the driver
had a bunch of state in various places e.g. as_mob or cpu_blit to
s
From: Zack Rusin
Various bits of the driver used raw ttm_buffer_object instead of the
driver specific vmw_bo object. All those places used to duplicate
the mapped bo caching policy of vmw_bo.
Instead of duplicating all of that code and special casing various
functions to work both with vmw_bo an
From: Zack Rusin
Base mapped count is useless because the ttm unmap functions handle
null maps just fine so completely remove all the code related to it.
Signed-off-by: Zack Rusin
Reviewed-by: Martin Krastev
---
drivers/gpu/drm/vmwgfx/vmwgfx_bo.h | 3 ---
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
From: Zack Rusin
Rename dummy to is_iomem because that's what it is even if we're not
activelly using it. Makes the code easier to read.
Signed-off-by: Zack Rusin
---
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/driver
From: Zack Rusin
The rest of the drivers which are using ttm have mostly standardized on
driver_prefix_bo as the name for subclasses of the TTM buffer object.
Make vmwgfx match the rest of the drivers and follow the same naming
semantics.
This is especially clear given that the name of the file
From: Zack Rusin
Only the legacy display unit requires pinning of the fb memory in vram.
Both the screen objects and screen targets can present from any buffer.
That makes the pinning abstraction pointless. Simplify all of the code
and move it to the legacy display unit, the only place that needs
From: Zack Rusin
Remove the explicit bo_free parameter which was switching between
vmw_bo_bo_free and vmw_gem_destroy which had exactly the same
implementation.
It makes no sense to keep parameter which is always the same, remove it
and all code referencing it. Instead use the vmw_bo_bo_free dir
From: Zack Rusin
Before vmwgfx supported gem it needed to implement the entire mmap logic
explicitly. With GEM support that's not needed and the generic code
can be used by simply setting the vm_ops to vmwgfx specific ones on the
gem object itself.
Removes a lot of code from vmwgfx without any f
From: Zack Rusin
v2: Fix all the issues which Thomas pointed out in the initial review
and split the "simplify fb pinning" change into two commits with the
second one being just the rename.
The series refactors the buffer object code to make more alike the
other ttm drivers. The placement become
Hi all,
Today's linux-next merge of the usb tree got a conflict in:
drivers/gpu/drm/i915/gt/intel_engine_cs.c
between commit:
5bc4b43d5c6c ("drm/i915: Fix up locking around dumping requests lists")
from the drm-intel-fixes tree and commit:
4d70c74659d9 ("i915: Move list_count() to list.
From: Xinlei Lee
For "boe,tv105wum-nw0" this special panel, it is stipulated in
the panel spec that MIPI needs to keep the LP11 state before
the lcm_reset pin is pulled high.
Signed-off-by: Xinlei Lee
---
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 6 ++
1 file changed, 6 insertions(+
From: Xinlei Lee
Reduce the delay after LCM reset by removing an extra delay in the
initialization commands array. The required delay of at least 6ms after
reset is guaranteed by boe_panel_prepare().
Signed-off-by: Xinlei Lee
---
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 1 -
1 file cha
From: Xinlei Lee
The panel spec stipulates that after lcm_reset is pulled high, cmd
should be sent to initialize the panel. Within the allowable range of
the DSI spec, this time needs to be reduced to avoid panel exceptions.
Base on the branch of linus/master v6.2.
Change since v2:
1. Remove th
scripts/kernel-doc complains about the comment for hotplug_failed,
so fix it:
include/drm/drm_client.h:111: warning: Incorrect use of kernel-doc format:
* @hotplug failed:
Fixes: 6a9d5ad3af65 ("drm/client: Add hotplug_failed flag")
Signed-off-by: Randy Dunlap
Cc: Thomas Zimmermann
Cc:
On Mon, 2023-01-30 at 15:39 -0600, Rob Herring wrote:
> On Mon, Jan 30, 2023 at 04:39:05PM +0800, Liu Ying wrote:
> > On Sun, 2023-01-29 at 12:46 +0100, Krzysztof Kozlowski wrote:
> > > On 28/01/2023 04:47, Liu Ying wrote:
> > > > NXP i.MX93 mediamix blk-ctrl contains one DISPLAY_MUX register
> > >
On 1/30/23 14:02, Christian König wrote:
Am 29.01.23 um 19:46 schrieb Danilo Krummrich:
On 1/27/23 22:09, Danilo Krummrich wrote:
On 1/27/23 16:17, Christian König wrote:
Am 27.01.23 um 15:44 schrieb Danilo Krummrich:
[SNIP]
What you want is one component for tracking the VA allocations
(d
Hi, Justin:
Justin Green 於 2023年1月31日 週二 上午4:36寫道：
>
> Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver.
>
> Tested using "modetest -P" on an MT8195.
>
> Signed-off-by: Justin Green
> ---
> v2:
> * Rebase and resolve merge conflicts with the AFBC patch.
> v3:
> * Moved 10
On Thu, 26 Jan 2023 22:08:31 +0100
Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> CONFIG_VFIO_MDEV cannot be selected when VFIO itself is
> disabled, otherwise we get a link failure:
>
> WARNING: unmet direct dependencies detected for VFIO_MDEV
> Depends on [n]: VFIO [=n]
> Selected by [y]
On Fri, 20 Jan 2023 22:00:53 +0100, Konrad Dybcio wrote:
> v2.5.0 support was originally added for SC7280, but this hw is also
> present on SM8350, which has one more DSI host. Bump up the dsi count
> and fill in the register of the secondary host to allow it to probe.
>
> This should not have any
On Tue, 31 Jan 2023 at 09:09, Chris Clayton wrote:
>
> Hi again.
>
> On 30/01/2023 20:19, Chris Clayton wrote:
> > Thanks, Ben.
>
>
>
> >> Hey,
> >>
> >> This is a complete shot-in-the-dark, as I don't see this behaviour on
> >> *any* of my boards. Could you try the attached patch please?
> >
>
On Tue, 31 Jan 2023 at 09:19, Lyude Paul wrote:
>
> For the whole series:
>
> Reviewed-by: Lyude Paul
>
> Will push to drm-misc-fixes in just a moment
Thank you Lyude! Much appreciated.
Ben.
>
> On Tue, 2023-01-31 at 08:37 +1000, Ben Skeggs wrote:
> > Starting from Turing, the driver is no lon
For the whole series:
Reviewed-by: Lyude Paul
Will push to drm-misc-fixes in just a moment
On Tue, 2023-01-31 at 08:37 +1000, Ben Skeggs wrote:
> Starting from Turing, the driver is no longer responsible for initiating
> DEVINIT when required as the GPU started loading a FW image from ROM and
>
Don't know if this still needs reviews from me (feel free to respond if it
does!), but I wanted to say nice work! This is something I've wanted to see
added to DRM for a while ♥
On Mon, 2023-01-09 at 16:40 +0800, Pin-yen Lin wrote:
> This series introduces bindings for anx7625/it6505 to register
Hi again.
On 30/01/2023 20:19, Chris Clayton wrote:
> Thanks, Ben.
>> Hey,
>>
>> This is a complete shot-in-the-dark, as I don't see this behaviour on
>> *any* of my boards. Could you try the attached patch please?
>
> Unfortunately, the patch made no difference.
>
> I've been looking at how
Hi Dave & Daniel,
Here is msm-next for v6.3. There is one devfreq patch to address a
build break issue in configurations without PM_DEVFREQ enabled (such
as COMPILE_TEST=y).
The following changes since commit 03a0a1040895711e12c15ab28d4d1812928e171d:
Merge tag 'drm-misc-next-2023-01-03' of
gi
Acked-by: Lyude Paul
On Thu, 2023-01-12 at 21:11 +0100, Thomas Zimmermann wrote:
> Several lastclose helpers call vga_switcheroo_process_delayed_switch().
> It's better to call the helper from drm_lastclose() after the kernel
> client's screen has been restored. This way, all drivers can benefit
On 1/30/2023 2:31 PM, Marijn Suijten wrote:
Abhinav,
On 2023-01-30 13:22:03, Abhinav Kumar wrote:
Hi Marijn
On 1/30/2023 12:16 PM, Marijn Suijten wrote:
On 2023-01-24 15:52:46, Kuogee Hsieh wrote:
If only replying to a small chunk somewhere in the middle of a diff
and/or large review, p
Missed some Tegra-specific quirks when reworking ACR to support Ampere.
Fixes: 2541626cfb79 ("drm/nouveau/acr: use common falcon HS FW code for ACR
FWs")
Signed-off-by: Ben Skeggs
Tested-by: Diogo Ivo
Tested-By: Nicolas Chauvet
---
drivers/gpu/drm/nouveau/nvkm/core/firmware.c| 3 +++
dri
Turing apparently needs to use the same register we use on Ampere.
Not executing the scrubber ucode when required would result in large
areas of VRAM being inaccessible to the driver.
Signed-off-by: Ben Skeggs
---
.../gpu/drm/nouveau/include/nvkm/subdev/fb.h | 1 +
.../gpu/drm/nouveau/nvkm/en
Starting from Turing, the driver is no longer responsible for initiating
DEVINIT when required as the GPU started loading a FW image from ROM and
executing DEVINIT itself after power-on.
However - we apparently still need to wait for it to complete.
This should correct some issues with runpm on s
Abhinav,
On 2023-01-30 13:22:03, Abhinav Kumar wrote:
> Hi Marijn
>
> On 1/30/2023 12:16 PM, Marijn Suijten wrote:
> > On 2023-01-24 15:52:46, Kuogee Hsieh wrote:
> >
> >
> >
> > If only replying to a small chunk somewhere in the middle of a diff
> > and/or large review, please cut out unneces
On Mon, Jan 30, 2023 at 4:51 PM Guilherme G. Piccoli
wrote:
>
> + Luben
>
> (sorry, missed that in the first submission).
>
> On 30/01/2023 18:45, Guilherme G. Piccoli wrote:
> > Currently amdgpu calls drm_sched_fini() from the fence driver sw fini
> > routine - such function is expected to be cal
On 12/29/2022 11:18 AM, Dmitry Baryshkov wrote:
In preparation to adding fully virtualized planes, move struct
dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as
it will become a part of state (allocated during atomic check) rather
than part of a plane (allocated during b
+ Luben
(sorry, missed that in the first submission).
On 30/01/2023 18:45, Guilherme G. Piccoli wrote:
> Currently amdgpu calls drm_sched_fini() from the fence driver sw fini
> routine - such function is expected to be called only after the
> respective init function - drm_sched_init() - was exec
The series is,
Acked-by: Luben Tuikov
We don't want the kernel to be in the business of retrying client's
requests. Instead we want the kernel to provide a conduit for such
requests to be sent, executed by the GPU, and a result returned.
If the kernel cannot process requests for any reason, e.g.
Currently amdgpu calls drm_sched_fini() from the fence driver sw fini
routine - such function is expected to be called only after the
respective init function - drm_sched_init() - was executed successfully.
Happens that we faced a driver probe failure in the Steam Deck
recently, and the function d
On Mon, Jan 30, 2023 at 04:39:05PM +0800, Liu Ying wrote:
> On Sun, 2023-01-29 at 12:46 +0100, Krzysztof Kozlowski wrote:
> > On 28/01/2023 04:47, Liu Ying wrote:
> > > NXP i.MX93 mediamix blk-ctrl contains one DISPLAY_MUX register
> > > which
> > > configures parallel display format by using the
>
Hi Marijn
On 1/30/2023 12:16 PM, Marijn Suijten wrote:
On 2023-01-24 15:52:46, Kuogee Hsieh wrote:
If only replying to a small chunk somewhere in the middle of a diff
and/or large review, please cut out unnecessary bits to make your reply
easier to find :)
+ data = (dsc->flatness_min_
Hi Rodrigo,
first of all, thanks for looking into this!
> > > > > > In the call flow invoked by intel_pcode_init(), I've added brief
> > > > > > comments
> > > > > > where further clarification is needed in this scenario, and a
> > > > > > description of
> > > > > > the suspicious scenario at t
Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver.
Tested using "modetest -P" on an MT8195.
Signed-off-by: Justin Green
---
v2:
* Rebase and resolve merge conflicts with the AFBC patch.
v3:
* Moved 10-bit support detection to mtk_disk_ovl.c
v4:
* Moved formats to mtk_disp
Add support for AR30 and BA30 pixel formats to the Mediatek DRM driver.
Tested using "modetest -P" on an MT8195.
Signed-off-by: Justin Green
---
v2:
* Rebase and resolve merge conflicts with the AFBC patch.
v3:
* Moved 10-bit support detection to mtk_disk_ovl.c
v4:
* Moved formats to mtk_disp
On 2023-01-23 10:24:29, Kuogee Hsieh wrote:
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index d612419..70a74ed 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -892,6 +894,10 @@ st
Thanks, Ben.
On 30/01/2023 01:09, Ben Skeggs wrote:
> On Sat, 28 Jan 2023 at 21:29, Chris Clayton wrote:
>>
>>
>>
>> On 28/01/2023 05:42, Linux kernel regression tracking (Thorsten Leemhuis)
>> wrote:
>>> On 27.01.23 20:46, Chris Clayton wrote:
[Resend because the mail client on my phone de
On 2023-01-24 15:52:46, Kuogee Hsieh wrote:
If only replying to a small chunk somewhere in the middle of a diff
and/or large review, please cut out unnecessary bits to make your reply
easier to find :)
> >> + data = (dsc->flatness_min_qp & 0x1f);
> >> + data |= (dsc->flatness_max_qp & 0x1f) <
Hi Maíra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip
next-20230130]
[cannot apply to drm-intel/for-linux-next-fixes linus/master v6.2-rc6]
[If your patch is applied to
This is a very trivial code clean-up related to commit 5468c36d6285
("drm/amd/display: Filter Invalid 420 Modes for HDMI TMDS"). This commit
added a validation on driver probe to prevent invalid TMDS modes, but one
of the fake properties (swizzle) ended-up causing a warning on driver
probe; was rep
On Tue, 2023-01-31 at 00:36 +0800, Keyu Tao wrote:
> !! External Email
>
> Hi vmwgfx maintainers,
>
> An out-of-bound access in vmwgfx specific framebuffer implementation can
> be easily triggered by fbterm (a framebuffer terminal emulator) when it
> is going to scroll screen.
>
> With some debu
Hi Diogo,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tegra/for-next]
[also build test ERROR on drm/drm-next tegra-drm/drm/tegra/for-next
linus/master v6.2-rc6 next-20230130]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Ma-ra-Canal/drm-debugfs-Introduce-wrapper-for-debugfs-list/20230130-2
On 30/01/2023 17:21, Kalyan Thota wrote:
This series will enable color features on sc7280 target which has primary panel
as eDP
The series removes dspp allocation based on encoder type and allows the dspp
reservation
based on user request via ctm.
The series will release/reserve the dpu resou
On 30/01/2023 17:21, Kalyan Thota wrote:
Some features like ctm can be enabled dynamically. Release and reserve
the dpu resources whenever a topology change occurs such that
required hw blocks are allocated appropriately.
Changes in v1:
- Avoid mode_set call directly instead change the mode_chan
On Thu, 26 Jan 2023 18:24:35 +, Rayyan Ansari wrote:
> Document the new panel node and what it is used for.
>
> Signed-off-by: Rayyan Ansari
> ---
> .../devicetree/bindings/display/simple-framebuffer.yaml | 9 +
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Rob Herring
On 30/01/2023 17:21, Kalyan Thota wrote:
Add dspp blocks into the topology for reservation, if there is a ctm
request for that composition.
Changes in v1:
- Minor nits (Dmitry)
Signed-off-by: Kalyan Thota
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++
Hi vmwgfx maintainers,
An out-of-bound access in vmwgfx specific framebuffer implementation can
be easily triggered by fbterm (a framebuffer terminal emulator) when it
is going to scroll screen.
With some debugging, it seems that vmw_fb_dirty_flush() cannot handle
the vinfo.yoffset correctly
On 1/26/2023 5:09 PM, Douglas Anderson wrote:
If our interrupt handler gets called and we don't really handle the
interrupt then we should return IRQ_NONE. The current interrupt
handler didn't do this, so let's fix it.
NOTE: for some of the cases it's clear that we should return IRQ_NONE
and s
On 1/26/2023 5:09 PM, Douglas Anderson wrote:
The DP AUX interrupt handling was a bit of a mess.
* There were two functions (one for "native" transfers and one for
"i2c" transfers) that were quite similar. It was hard to say how
many of the differences between the two functions were on pu
On 1/28/2023 11:59, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
v2: pass gt to print_fw_ver
v3: prefer guc_dbg in suspend/resume logs
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel
On 1/28/2023 11:59, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
v2: drop redundant GuC strings, minor improvements
v3: more message improvements
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/
On Mon, Jan 30, 2023 at 11:37:29AM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 30, 2023 at 05:12:48PM +0100, Andi Shyti wrote:
> > Hi Rodrigo,
> >
> > > > > In the call flow invoked by intel_pcode_init(), I've added brief
> > > > > comments
> > > > > where further clarification is needed in this sce
On Tue, Jan 24, 2023 at 03:42:37PM +0530, Aradhya Bhatia wrote:
> Dual-link LVDS interfaces have 2 links, with even pixels traveling on
> one link, and odd pixels on the other. These panels are also generic in
> nature, with no documented constraints, much like their single-link
> counterparts, "pa
On Mon, Jan 30, 2023 at 05:12:48PM +0100, Andi Shyti wrote:
> Hi Rodrigo,
>
> > > > In the call flow invoked by intel_pcode_init(), I've added brief
> > > > comments
> > > > where further clarification is needed in this scenario, and a
> > > > description of
> > > > the suspicious scenario at th
On Sat, Jan 28, 2023 at 7:47 PM kernel test robot wrote:
>
> Hi Jonathan,
>
> Thank you for the patch! Perhaps something to improve:
Good bot.
>
> [auto build test WARNING on 93f875a8526a291005e7f38478079526c843cbec]
>
> url:
> https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cormier/dt
Hi Rodrigo,
> > > In the call flow invoked by intel_pcode_init(), I've added brief comments
> > > where further clarification is needed in this scenario, and a description
> > > of
> > > the suspicious scenario at the bottom.
> > >
> > > --
Le dim. 29 janv. 2023 à 23:36, Ben Skeggs a écrit :
>
> On Fri, 27 Jan 2023 at 20:42, Diogo Ivo wrote:
> >
> > On Fri, Jan 27, 2023 at 04:00:59PM +1000, Ben Skeggs wrote:
> > > On Fri, 20 Jan 2023 at 21:37, Diogo Ivo
> > > wrote:
> > > >
> > > > On Wed, Jan 18, 2023 at 11:28:49AM +1000, Ben Ske
On 1/27/2023 3:14 PM, Arnd Bergmann wrote:
From: Arnd Bergmann
At the moment, accel drivers can be built-in even with CONFIG_DRM=m,
but this causes a link failure:
x86_64-linux-ld: drivers/accel/ivpu/ivpu_drv.o: in function `ivpu_dev_init':
ivpu_drv.c:(.text+0x1535): undefined reference to `dr
Clear dspp reservations from the global state during
rm release
Signed-off-by: Kalyan Thota
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_
Some features like ctm can be enabled dynamically. Release and reserve
the dpu resources whenever a topology change occurs such that
required hw blocks are allocated appropriately.
Changes in v1:
- Avoid mode_set call directly instead change the mode_changed (Dmitry)
Signed-off-by: Kalyan Thota
This series will enable color features on sc7280 target which has primary panel
as eDP
The series removes dspp allocation based on encoder type and allows the dspp
reservation
based on user request via ctm.
The series will release/reserve the dpu resources when ever there is a topology
change
Add dspp blocks into the topology for reservation, if there is a ctm
request for that composition.
Changes in v1:
- Minor nits (Dmitry)
Signed-off-by: Kalyan Thota
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 ++---
1 file changed, 6 insertions(+),
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dis
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++-
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/bridge
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_brid
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Ba
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
Reviewed-by: Daniel Vetter
---
drivers/gpu/
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/di
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Chang
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu
On Tue, Jan 24, 2023 at 03:25:09PM +0100, Thierry Reding wrote:
> On Fri, Jan 20, 2023 at 10:58:56AM +, Diogo Ivo wrote:
> > Hello!
> >
> > This patch series adds support for correctly displaying tiled
> > framebuffers when no modifiers are reported by userspace.
> >
> > Patch 1 adds the sect
On Mon, Jan 30, 2023 at 09:48:31AM +0100, Andi Shyti wrote:
> Hi GG,
>
> thanks for the deep analysis!
>
> > Hi Andi,
> > In the call flow invoked by intel_pcode_init(), I've added brief comments
> > where further clarification is needed in this scenario, and a description of
> > the suspicious s
In preparation to implement Tegra20 parallel video capture, add a variable
to hold the required syncpt and document all the syncpt variables.
Signed-off-by: Luca Ceresoli
Reviewed-by: Dmitry Osipenko
---
Changed in v4:
- Added review tags
Changed in v3:
- recycle mw_ack_sp[0] instead of add
tegra_channel_host1x_syncpt_init() gets the host1x syncpts needed for the
Tegra210 implementation, and tegra_channel_host1x_syncpts_free() puts
them.
Tegra20 needs to get and put a different syncpt. In preparation for adding
Tegra20 support, move these functions to new ops in the soc-specific
`str
Tegra20 supports planar YUV422 capture, which can be implemented by writing
U and V base address registers in addition to the "main" base buffer
address register.
It also supports H and V flip, which among others requires to write the
start address (i.e. the 1st offset to write, at the end of the
Tegra20 can do horizontal and vertical image flip, but Tegra210 cannot
(either the hardware, or this driver).
In preparation to adding Tegra20 support, add a flag in struct tegra_vi_soc
so the generic vi.c code knows whether the flip controls should be added or
not.
Also provide a generic impleme
The VI peripheral of Tegra supports capturing from MIPI CSI-2 or parallel
video (called VIP in the docs).
The staging tegra-video driver currently implements MIPI CSI-2 video
capture for Tegra210. Add support for parallel video capture (VIP) on
Tegra20. With the generalizations added to the VI dri
The CSI module does not handle all the MIPI lane calibration procedure,
leaving a small part of it to the VI module. In doing this,
tegra_channel_enable_stream() (vi.c) manipulates the private data of the
upstream subdev casting it to struct 'tegra_csi_channel', which will be
wrong after introducin
The Tegra20 VI needs an additional operation to enable the VI, add an
operation for that.
Signed-off-by: Luca Ceresoli
Reviewed-by: Dmitry Osipenko
---
Changed in v4:
- Added review tags
No changes in v3
No changes in v2
---
drivers/staging/media/tegra-video/vi.c | 7 +++
drivers/stagin
The tegra_default_format in vi.c is specific to Tegra210 CSI.
In preparation for adding Tegra20 VIP support, move the default format to a
new field in the soc-specific `struct tegra_vi_soc`. Instead of an entire
format struct, only store a pointer to an item in the existing format
array.
No funct
tegra_channel_fmt_align() takes care of the size constraints, alignment and
rounding requirements of the Tegra210 VI peripheral. Tegra20 has different
constraints.
In preparation for adding Tegra20 support, move this function to a new op
in the soc-specific `struct tegra_vi_ops` .
Also move to te
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