On 24/01/2023 03:48, Abhinav Kumar wrote:
On 1/19/2023 9:26 PM, Dmitry Baryshkov wrote:
On Fri, 20 Jan 2023 at 00:54, Abhinav Kumar
wrote:
On 1/17/2023 5:04 PM, Dmitry Baryshkov wrote:
To simplify adding new platforms and to make settings more obvious,
rewrite the UBWC setup to use the d
(I missed this review you did before I had sent a v2.1, I will incorporate
what is missing in the next version)
On Mon, Jan 23, 2023 at 12:38:28PM +0200, Jani Nikula wrote:
On Fri, 20 Jan 2023, Lucas De Marchi wrote:
It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based
Am 24.01.23 um 04:56 schrieb James Jones:
On 1/23/23 08:58, Laurent Pinchart wrote:
Hi Christian,
On Mon, Jan 23, 2023 at 05:29:18PM +0100, Christian König wrote:
Am 23.01.23 um 14:55 schrieb Laurent Pinchart:
Hi Christian,
CC'ing James as I think this is related to his work on the unix devi
On 23/01/2023 20:24, Kuogee Hsieh wrote:
DSC V1.2 encoder engine is newly added hardware module. This patch
add support functions to configure and enable DSC V1.2 encoder engine.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/
On Mon, 2023-01-23 at 09:13 +0100, Lothar Waßmann wrote:
> Hi,
Hi,
>
> On Mon, 23 Jan 2023 15:23:58 +0800 Liu Ying wrote:
> > The LCDIF embedded in i.MX93 SoC is essentially the same to those
> > in i.MX8mp SoC. However, i.MX93 LCDIF may connect with MIPI DSI
> > controller through LCDIF cross
Am 24.01.23 um 06:19 schrieb John Stultz:
On Mon, Jan 23, 2023 at 8:29 AM Christian König
wrote:
Am 23.01.23 um 14:55 schrieb Laurent Pinchart:
- I assume some drivers will be able to support multiple heaps. How do
you envision this being implemented ?
I don't really see an use case for t
Hi Tomi,
Thanks for reviewing the patch series. I have implemented the most of
your suggestions, but for the others, I needed to clarify things. I have
made some comments there.
On 20-Dec-22 18:22, Tomi Valkeinen wrote:
Hi,
On 19/11/2022 19:30, Aradhya Bhatia wrote:
The newer version of DSS (
On Tue, 24 Jan 2023 at 01:49, Sam Ravnborg wrote:
>
> Hi Jagan.
>
> One small drive-by comment.
>
> On Tue, Jan 24, 2023 at 12:16:46AM +0530, Jagan Teki wrote:
> > Many downstream bridges or panels followed by dw-mipi-dsi were
> > using MIPI_DSI_MODE_NO_EOT_PACKET.
> >
> > So, handle the EOTP bits
On 1/23/23 11:47, Bart Van Assche wrote:
> On 1/23/23 05:44, Jason Gunthorpe wrote:
>> I've gone from quite a different starting point - I've been working
>> DMA API upwards, so what does the dma_map_XX look like, what APIs do
>> we need to support the dma_map_ops implementations to iterate/etc, ho
Hi
A user in Debian, cc'ed reporte the following issue when resuming from
hibernation, tested as well on recent 6.1.7 kernel, context see
https://bugs.debian.org/971068
> Can repro on the sid kernel, uname -a of
> Linux nabtop 6.1.0-2-686-pae #1 SMP PREEMPT_DYNAMIC Debian 6.1.7-1
> (2023-01-18
The Rockchip VOP2 features an internal RGB output block, which can be
attached any video port of the VOP2. Add support for this output block.
Signed-off-by: Michael Riesch
---
v3:
- fix commit messages (still assumed video port 2)
- fix condition to make 0 a valid video port
v2:
- move away fr
Let the function name vop2_create_crtcs reflect that the function creates
multiple CRTCS. Also, use a symmetric function pair to create and destroy
the CRTCs and the corresponding planes.
Signed-off-by: Michael Riesch
---
v3:
- no changes
v2:
- no changes
drivers/gpu/drm/rockchip/rockchip_drm
The rk3568-pinctrl.dtsi only defines the 24-bit RGB interface. Add separate
nodes for the 16-bit and 18-bit version, respectively. While at it, split
off the clock/sync signals from the data signals.
The exact mapping of the data pins was discussed here:
https://lore.kernel.org/linux-rockchip/f33a
The VOP2 driver has more than one video port, hence the hard-coded
port id will not work anymore. Add an extra parameter for the video
port id to the rockchip_rgb_init function.
Signed-off-by: Michael Riesch
---
v3:
- no changes
v2:
- no changes
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2
Commit 540b8f271e53 ("drm/rockchip: Embed drm_encoder into
rockchip_decoder") provides the means to pass the endpoint ID to the
VOP2 driver, which sets the interface MUX accordingly. However, this
step has not yet been carried out for the RGB output block. Embed the
drm_encoder structure into the r
The variable possible_crtcs is only initialized for primary and
overlay planes. Since the VOP2 driver only supports these plane
types at the moment, the current code is safe. However, in order
to provide a future-proof solution, fix the initialization of
the variable.
Reported-by: kernel test robo
Hi all,
This series adds support for the RGB output block that can be found in the
Rockchip Video Output Processor (VOP) 2. Version 2 of this series
incorporates the feedback by Dan Carpenter and Sascha Hauer. Version 3
fixes a dumb mistake pointed out by Sascha :-) Thanks for your comments!
Patc
From: Alexander Usyskin
Add device link with i915 as consumer and mei_pxp as supplier
to ensure proper ordering of power flows.
V2: condition on absence of heci_pxp to filter out DG
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 11 +++
drivers/gpu/d
A driver bug was recently discovered where the security firmware was
receiving internal HW signals indicating that session key expirations
had occurred. Architecturally, the firmware was expecting a response
from the GuC to acknowledge the event with the firmware side.
However the OS was in a suspe
From: Alexander Usyskin
Asynchronous runtime resume is not possible while the system
is suspending.
The power management subsystem resumes the device only in the
suspend phase, not in the prepare phase.
Force resume device in prepare to allow drivers on mei bus
to communicate in their prepare cal
From: Alexander Usyskin
Client on bus have only one vtag map slot and should disregard the vtag
value when cleaning pending read flag.
Fixes read flow control message unexpectedly generated when
clent on bus send messages with different vtags.
Signed-off-by: Alexander Usyskin
Reviewed-by: Tomas
A gap was recently discovered where if an application did not
invalidate all of the stream keys (intentionally or not), and the
driver did a full PXP global teardown on the GT subsystem, we
find that future session creation would fail on the security
firmware's side of the equation. i915 is the ent
During suspend flow, i915 currently achors' on the pm_suspend_prepare
callback as the location where we quiesce the entire GPU and perform
all necessary cleanup in order to go into suspend. PXP is also called
during this time to perform the arbitration session teardown (with
the assurance no additi
A customer issue was recently discovered and in the process a
gap in i915's PXP interaction with HW+FW architecure was also
realized. This series adds those missing pieces.
This fix includes changes where i915 calls into the mei
component interface in order to submit requests to the security
firmw
On Mon, Jan 23, 2023 at 8:29 AM Christian König
wrote:
> Am 23.01.23 um 14:55 schrieb Laurent Pinchart:
> > - I assume some drivers will be able to support multiple heaps. How do
> >you envision this being implemented ?
>
> I don't really see an use case for this.
>
> We do have some drivers w
On Mon, Jan 23, 2023 at 5:55 AM Laurent Pinchart
wrote:
>
> Hi Christian,
>
> CC'ing James as I think this is related to his work on the unix device
> memory allocator ([1]).
>
> [1]
> https://lore.kernel.org/dri-devel/8b555674-1c5b-c791-4547-2ea7c16ae...@nvidia.com/
>
> On Mon, Jan 23, 2023 at 0
On Mon, Jan 23, 2023 at 4:38 AM Christian König
wrote:
>
> This allows device drivers to specify a DMA-heap where they want their
> buffers to be allocated from. This information is then exposed as
> sysfs link between the device and the DMA-heap.
>
> Useful for userspace when in need to decide fr
On 1/23/23 08:58, Laurent Pinchart wrote:
Hi Christian,
On Mon, Jan 23, 2023 at 05:29:18PM +0100, Christian König wrote:
Am 23.01.23 um 14:55 schrieb Laurent Pinchart:
Hi Christian,
CC'ing James as I think this is related to his work on the unix device
memory allocator ([1]).
Thank you for
Hi Christian,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on media-tree/master drm-tip/drm-tip linus/master
v6.2-rc5]
[cannot apply to next-20230123]
[If your patch is applied to the wrong git tree, kindly drop us
On Mon, 2023-01-23 at 09:31 -0500, Vivi, Rodrigo wrote:
> On Sun, Jan 22, 2023 at 06:57:24AM +, Usyskin, Alexander wrote:
> > > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> > > > index d50354bfb993..bef6d7f8ac55 100644
> > > > --- a
On 1/16/2023 2:30 AM, Dmitry Baryshkov wrote:
Add missing DPU_CLK_CTRL_WB2 to sc7180_mdp clocks array.
Fixes: 51e4d60e6ba5 ("drm/msm/dpu: add writeback support for sc7180")
Signed-off-by: Dmitry Baryshkov
Tested-by: Jessica Zhang # Trogdor (sc7180)
---
drivers/gpu/drm/msm/disp/dpu1/dp
On 1/19/2023 9:26 PM, Dmitry Baryshkov wrote:
On Fri, 20 Jan 2023 at 00:54, Abhinav Kumar wrote:
On 1/17/2023 5:04 PM, Dmitry Baryshkov wrote:
To simplify adding new platforms and to make settings more obvious,
rewrite the UBWC setup to use the data structure to pass platform config
rath
On 1/17/2023 6:01 PM, Dmitry Baryshkov wrote:
Using strncpy can result in non-NULL-terminated destination string. Use
strscpy instead. This fixes following warning:
drivers/gpu/drm/msm/msm_fence.c: In function ‘msm_fence_context_alloc’:
drivers/gpu/drm/msm/msm_fence.c:25:9: warning: ‘strncpy’
On 1/22/2023 10:24 PM, Dmitry Baryshkov wrote:
Use the values from the vendor DTs to set ubwc_swizzle in the catalog.
Signed-off-by: Dmitry Baryshkov
Matches all the vendor DTs, hence
Reviewed-by: Abhinav Kumar
---
Changes since v1:
- Added data for sc7280 and sm8550
---
drivers/gp
On 1/21/2023 5:54 AM, Dmitry Baryshkov wrote:
The field ubwc_static was removed from struct dpu_mdp_cfg some time ago.
Drop the corresponding kerneldoc now.
Fixes: 544d8b96150d ("drm/msm/dpu: update UBWC config for sm8150 and sm8250")
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Ku
On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
rectangles and CSC. Drop corresponding features being incorrectly
enabled for qcm2290.
Can you please point me to which vendor DT you are referring to for this?
CSC is su
On 1/16/2023 2:30 AM, Dmitry Baryshkov wrote:
Add missing DPU_CLK_CTRL_WB2 to sc7180_mdp clocks array.
Fixes: 51e4d60e6ba5 ("drm/msm/dpu: add writeback support for sc7180")
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |
On 1/23/2023 12:08 AM, Dmitry Baryshkov wrote:
Correct the CTL size on sm8450 platform. This fixes the incorrect merge
of sm8350 support, which unfortunately also touched the SM8450 setup.
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: Dmitry Baryshkov
Matches
Hi Kuogee,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20230123]
[also build test WARNING on linus/master v6.2-rc5]
[cannot apply to drm-misc/drm-misc-next drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes
On 19/01/2023 16:26, Vinod Polimera wrote:
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set
On 19/01/2023 16:26, Vinod Polimera wrote:
Populate the enocder software structure to reflect the updated
crtc appropriately during crtc enable/disable for a new commit
while taking care of the self refresh transitions when crtc
disable is triggered from the drm self refresh library.
Signed-off-
On 19/01/2023 16:26, Vinod Polimera wrote:
Clear interface active register from the datapath for a clean shutdown of
the datapath.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu
On 19/01/2023 16:26, Vinod Polimera wrote:
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dp
On 19/01/2023 16:26, Vinod Polimera wrote:
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod P
On 19/01/2023 16:26, Vinod Polimera wrote:
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
5.0.0 is sm8
On 19/01/2023 16:26, Vinod Polimera wrote:
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
I'm not convinced by this c
Thanks - will go with your suggestion - ditch all the abstraction /
consolidation ..
add only the two additional calls with the explicit runtime-takes - that
minimizes the changes.
And won't forget to the fix the '&' -> '&&'
...alan
On Wed, 2023-01-18 at 18:17 -0800, Ceraolo Spurio, Daniele wrot
On 1/24/23 00:23, Niranjana Vishwanathapura wrote:
On Wed, Jan 18, 2023 at 07:12:45AM +0100, Danilo Krummrich wrote:
This adds the infrastructure for a manager implementation to keep track
of GPU virtual address (VA) mappings.
New UAPIs, motivated by Vulkan sparse memory bindings graphics drive
On 23/01/2023 20:24, Kuogee Hsieh wrote:
This patch add DSC related supporting functions into to both dp controller and
dpu enccoder
Kuogee Hsieh (14):
drm/msm/dp: add dpcd read of both dsc and fec capability
drm/msm/dp: add dsc factor into calculation of supported bpp
drm/msm/dp: add
Hi Kuogee,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20230123]
[also build test WARNING on linus/master v6.2-rc5]
[cannot apply to drm-misc/drm-misc-next drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes
Hi Christian,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on media-tree/master drm-tip/drm-tip linus/master
v6.2-rc5]
[cannot apply to next-20230123]
[If your patch is applied to the wrong git tree, kindly drop us
On 23/01/2023 20:24, Kuogee Hsieh wrote:
At display port, the pixel data is packed into TU (transfer units)
which is used to carry main video stream data during its horizontal active
period. TUs are mapping into the main-Link to facilitate the support of
various lane counts regardless of the pixe
On Mon, Jan 23, 2023 at 11:43 PM Simon Ser wrote:
>
> On Monday, January 23rd, 2023 at 21:25, Sebastian Wick
> wrote:
>
> > Why is the TF defined for GL formats and both the primaries and TF for
> > Vulkan formats? The only exception here should be sRGB formats. Where
> > did you get the informa
Hi Kuogee,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20230123]
[also build test WARNING on linus/master v6.2-rc5]
[cannot apply to drm-misc/drm-misc-next drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes
On 1/20/2023 08:40, Michal Wajdeczko wrote:
While we do have GT oriented print macros, add few more GuC
specific to have common look and feel across all messages
related to the GuC and to avoid chasing the gt pointer.
We will use these macros shortly in upcoming patches.
Signed-off-by: Michal W
On Wed, Jan 18, 2023 at 07:12:45AM +0100, Danilo Krummrich wrote:
This adds the infrastructure for a manager implementation to keep track
of GPU virtual address (VA) mappings.
New UAPIs, motivated by Vulkan sparse memory bindings graphics drivers
start implementing, allow userspace applications
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 74 +--
1 file changed, 36 insertions(+), 38 deletions(-)
diff --git
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 60 ---
1 file changed, 26 insertions(+), 34 deletions(-)
diff --git
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 35 +++---
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 17 +
1 file changed, 9 insertions(+), 8 d
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gp
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
1 file changed, 4 insertions(+), 4 deletions(
From: Koji Matsuoka
According to hardware manual, LVDCR0 register must be cleared bit by bit
when disabling LVDS.
Signed-off-by: Koji Matsuoka
Signed-off-by: LUU HOAI
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
Signed-off-by: Lauren
On 1/20/2023 08:40, Michal Wajdeczko wrote:
Use new macros to have common prefix that also include GT#.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 31 +-
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git
On Mon, Jan 23, 2023 at 12:50:52PM -0800, Dan Williams wrote:
> Matthew Wilcox wrote:
> > On Mon, Jan 23, 2023 at 11:36:51AM -0800, Dan Williams wrote:
> > > Jason Gunthorpe via Lsf-pc wrote:
> > > > I would like to have a session at LSF to talk about Matthew's
> > > > physr discussion starter:
> >
On 23/01/2023 20:24, Kuogee Hsieh wrote:
Add display compression related struct to support variant compression
mechanism. However, DSC is the only one supported at this moment.
VDC may be added later.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.h | 42 ++
On Monday, January 23rd, 2023 at 21:25, Sebastian Wick
wrote:
> Why is the TF defined for GL formats and both the primaries and TF for
> Vulkan formats? The only exception here should be sRGB formats. Where
> did you get the information from?
This is what upstream dfdutils does [1]. Can you exp
On Sun, 2023-01-22 at 18:48 +, SeongJae Park wrote:
> Some documents that listed on subsystem-apis have 'Linux' or 'The Linux'
> title prefixes. It's duplicated information, and makes finding the
> document of interest with human eyes not easy. Remove the prefixes from
> the titles.
>
> Sign
On 23/01/2023 20:24, Kuogee Hsieh wrote:
MSA MISC0 bit 1 to 7 contains Colorimetry Indicator Field. At current
implementation, Colorimetry Indicator Field of MISC0 is not configured
correctly. This patch add support of RGB formats Colorimetry.
Any Fixes tag? Not to mention that fixes should com
Hi Geert,
On Mon, Jan 23, 2023 at 03:28:08PM +0100, Geert Uytterhoeven wrote:
> On Mon, Jan 23, 2023 at 11:48 AM Tomi Valkeinen wrote:
> > From: Koji Matsuoka
> >
> > According to hardware manual, LVDCR0 register must be cleared bit by bit
> > when disabling LVDS.
> >
> > Signed-off-by: Koji Mats
On 23/01/2023 20:24, Kuogee Hsieh wrote:
Mainlink_levels determined when two actions to take place by hardware,
a new BS sequence due to start of video and a static HW MVID is sent
to panel. This patch add function to configure mainlink level properly
base on lane number.
Signed-off-by: Kuogee H
On 23/01/2023 20:24, Kuogee Hsieh wrote:
This patch provides DSC required functions at DP controller to
complete DSC feature. those functions include enable fec, configure
dsc, configure dto, transmit pps and finally flush hardware registers.
Too many items for a single patch in my opinion.
On 23/01/2023 20:24, Kuogee Hsieh wrote:
FEC is pre-requirement of DSC. Therefore FEC has to be enabled
before DSC enabled. This patch add functions to read sink's DSC
and FEC related DPCD and decode them and set enable flags
accordingly.
Please split this to FEC and DSC patches.
Signed-off-
This has nothing to do with /dp, make it /dpu
On 2023-01-23 10:24:27, Kuogee Hsieh wrote:
> Add DSC related supporting functions to calculate DSC related parameters.
> In addition, DSC hardware encoder customized configuration parameters are
> also included. Algorithms used to perform calculation
On 23/01/2023 20:24, Kuogee Hsieh wrote:
struct msm_compression_info is used to support several different
compression mechanisms. It also contains customized info required
to configure DSC encoder engine. This patch also make changes DSI
module to have DSI exports struct msm_compreion_info to dpu
On 23/01/2023 20:24, Kuogee Hsieh wrote:
Add DSC related supporting functions to calculate DSC related parameters.
In addition, DSC hardware encoder customized configuration parameters are
also included. Algorithms used to perform calculation are derived from
system engineer spreadsheet.
Overal
On 23/01/2023 20:24, Kuogee Hsieh wrote:
A new flushing mechanism is introduced to decouple peripheral metadata
flushing from timing engine related flush. This patch add peripheral
flushing functions.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 24
On 23/01/2023 20:24, Kuogee Hsieh wrote:
Current implementation timing engine programming does not consider
compression factors. This patch add consideration of DSC factors
while programming timing engine.
Signed-off-by: Kuogee Hsieh
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c |
On Thu, 19 Jan 2023 15:22:15 +0200, Dmitry Baryshkov wrote:
> Eventually all HDMI PHYs are going to provide the HDMI PLL clock to the
> MMCC. Add #clock-cells property required to provide the HDMI PLL clock to
> other devices.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../devicetree/bindings
On Thu, 19 Jan 2023 14:10:33 +0100, Krzysztof Kozlowski wrote:
> The type for operating-points-v2 property is coming from dtschema
> (/schemas/opp/opp.yaml), so individual bindings can just use simple
> "true".
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> This depends on my pull request
On Wed, 2023-01-18 at 18:01 -0800, Ceraolo Spurio, Daniele wrote:
>
>
> On 1/11/2023 1:42 PM, Alan Previn wrote:
> > Despite KCR subsystem being in the media-tile (close to the
> > GSC-CS), the IRQ controls for it are on GT-0 with other global
> > IRQ controls. Thus, add a helper for KCR hw inter
Matthew Wilcox wrote:
> On Mon, Jan 23, 2023 at 11:36:51AM -0800, Dan Williams wrote:
> > Jason Gunthorpe via Lsf-pc wrote:
> > > I would like to have a session at LSF to talk about Matthew's
> > > physr discussion starter:
> > >
> > > https://lore.kernel.org/linux-mm/ydykweu0htv8m...@casper.infr
Hi Thomas,
a quick drive-by comment.
On Mon, Jan 23, 2023 at 11:05:59AM +0100, Thomas Zimmermann wrote:
> The generic fbdev emulation names variables of type struct fb_info
> both 'fbi' and 'info'. The latter seems to be more common in fbdev
> code, so name fbi accordingly.
>
> Also replace the
Hi Thomas,
On Mon, Jan 23, 2023 at 09:57:13AM +0100, Thomas Zimmermann wrote:
> Hi Sam,
>
> please see my comment below.
>
> Am 21.01.23 um 21:09 schrieb Sam Ravnborg via B4 Submission Endpoint:
> > From: Sam Ravnborg
> >
> > drm_timeout_abs_to_jiffies() was implmented in drm_syncobj where
> >
Am 23.01.23 um 21:26 schrieb André Almeida:
Create a document that specifies how to deal with DRM device resets for
kernel and userspace drivers.
Signed-off-by: André Almeida
---
Documentation/gpu/drm-reset.rst | 51 +
Documentation/gpu/index.rst | 1 +
Follow the pattern for iommu_map() and remove iommu_map_sg_atomic().
This allows __iommu_dma_alloc_noncontiguous() to use a GFP_KERNEL
allocation here, based on the provided gfp flags.
Reviewed-by: Kevin Tian
Signed-off-by: Jason Gunthorpe
---
drivers/iommu/dma-iommu.c | 5 +++--
drivers/iomm
dma_alloc_cpu_table() and dma_alloc_page_table() are eventually called by
iommufd through s390_iommu_map_pages() and it should not be forced to
atomic. Thread the gfp parameter through the call chain starting from
s390_iommu_map_pages().
Reviewed-by: Niklas Schnelle
Reviewed-by: Matthew Rosato
S
These contexts are sleepable, so use the proper annotation. The GFP_ATOMIC
was added mechanically in the prior patches.
Reviewed-by: Niklas Schnelle
Reviewed-by: Matthew Rosato
Signed-off-by: Jason Gunthorpe
---
arch/s390/pci/pci_dma.c| 2 +-
drivers/iommu/s390-iommu.c | 2 +-
2 files chan
The internal mechanisms support this, but instead of exposting the gfp to
the caller it wrappers it into iommu_map() and iommu_map_atomic()
Fix this instead of adding more variants for GFP_KERNEL_ACCOUNT.
Reviewed-by: Kevin Tian
Signed-off-by: Jason Gunthorpe
---
arch/arm/mm/dma-mapping.c
These contexts are sleepable, so use the proper annotation. The GFP_ATOMIC
was added mechanically in the prior patches.
Reviewed-by: Lu Baolu
Reviewed-by: Kevin Tian
Signed-off-by: Jason Gunthorpe
---
drivers/iommu/intel/iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
There is only one call site and it can now just pass the GFP_ATOMIC to the
normal iommu_map().
Reviewed-by: Kevin Tian
Signed-off-by: Jason Gunthorpe
---
drivers/iommu/dma-iommu.c | 2 +-
drivers/iommu/iommu.c | 7 ---
include/linux/iommu.h | 9 -
3 files changed, 1 insertio
iommufd follows the same design as KVM and uses memory cgroups to limit
the amount of kernel memory a iommufd file descriptor can pin down. The
various internal data structures already use GFP_KERNEL_ACCOUNT.
However, one of the biggest consumers of kernel memory is the IOPTEs
stored under the iom
This is eventually called by iommufd through intel_iommu_map_pages() and
it should not be forced to atomic. Push the GFP_ATOMIC to all callers.
Reviewed-by: Kevin Tian
Reviewed-by: Lu Baolu
Signed-off-by: Jason Gunthorpe
---
drivers/iommu/intel/iommu.c | 14 +++---
drivers/iommu/intel/
Flow it down to alloc_pgtable_page() via pfn_to_dma_pte() and
__domain_mapping().
Reviewed-by: Kevin Tian
Reviewed-by: Lu Baolu
Signed-off-by: Jason Gunthorpe
---
drivers/iommu/intel/iommu.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/i
iommufd follows the same design as KVM and uses memory cgroups to limit
the amount of kernel memory a iommufd file descriptor can pin down. The
various internal data structures already use GFP_KERNEL_ACCOUNT to charge
its own memory.
However, one of the biggest consumers of kernel memory is the IO
This function does an allocation of a buffer to return to the caller and
then goes on to allocate some internal memory, eg the scatterlist and
IOPTEs.
Instead of hard wiring GFP_KERNEL and a wrong GFP_ATOMIC, continue to use
the passed in gfp flags for all of the allocations. Clear the zone and
po
On 1/23/2023 09:51, Tvrtko Ursulin wrote:
On 20/01/2023 23:28, john.c.harri...@intel.com wrote:
From: John Harrison
When GuC support was added to error capture, the locking around the
request object was broken. Fix it up.
The context based search manages the spinlocking around the search
inte
On Sun, Jan 22, 2023 at 06:48:34PM +, SeongJae Park wrote:
> Some documents that listed on subsystem-apis have 'Linux' or 'The Linux'
> title prefixes. It's duplicated information, and makes finding the
> document of interest with human eyes not easy. Remove the prefixes from
> the titles.
>
A new property to control YCC and subsampling would be the more
complete path here. If we actually want to fix this in the short-term
though, we should handle the YCC and RGB Colorspace values as
equivalent, everywhere. Technically we're breaking the user space API
here so it should be documented o
Create a document that specifies how to deal with DRM device resets for
kernel and userspace drivers.
Signed-off-by: André Almeida
---
Documentation/gpu/drm-reset.rst | 51 +
Documentation/gpu/index.rst | 1 +
2 files changed, 52 insertions(+)
create mode 10
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