Hi Daniel, Dave,
We might be fairly late for a drm-misc-next PR by now, but I chose to
send it anyway because we might have an -rc8, and this is almost
exclusively fixes that should go in anyway. This will be the last
drm-misc-next PR for this cycle
Maxime
drm-misc-next-2022-11-24:
drm-misc-next
On Wed, Nov 23, 2022 at 08:24:37PM +0100, Daniel Vetter wrote:
> It's a bit a FAQ, and we really can't claim to be the authoritative
> source for allocating these numbers used in many standard extensions
> if we tell closed source or vendor stacks in general to go away.
>
> Iirc this was already c
Hi,
> > > +#ifdef __BIG_ENDIAN
> >
> > Why do we need the #ifdef here? Iirc some hw has big endian flags in the
> > scanout registers, so could supprt this unconditionally if there's no
> > #ifdef around the format defines. Some drivers might then also want a
> > DRM_FORMAT_FOO_BE define to simp
Am 23.11.22 um 20:35 schrieb T.J. Mercier:
I've been collecting these typo fixes for a while and it feels like
time to send them in.
Signed-off-by: T.J. Mercier
Acked-by: Christian König
---
drivers/dma-buf/dma-buf.c | 14 +++---
include/linux/dma-buf.h | 6 +++---
2 files c
Thanks T.J and Christian for the inputs.
On 11/19/2022 7:00 PM, Christian König wrote:
>>
>> Yes, exactly that's the idea.
>>
>> The only alternatives I can see would be to either move allocating
>> the
>> file and so completing the dma_buf initialization last again or just
>>
On Thu, Nov 24, 2022 at 4:16 AM Sean Paul wrote:
>
> On Wed, Nov 23, 2022 at 10:05:29AM +, Hsin-Yi Wang wrote:
> > it6505 supports HDCP 1.3, but current implementation lacks the update of
> > HDCP status through drm_hdcp_update_content_protection().
> >
> > it6505 default enables the HDCP. Rem
On 11/24/22 01:27, Daniel Vetter wrote:
CAUTION: Email originated externally, do not click links or open attachments
unless you recognize the sender and know the content is safe.
On Thu, Nov 24, 2022 at 01:14:48AM +0800, Randy Li wrote:
On Nov 24, 2022, at 12:42 AM, Daniel Vetter wrote:
Hi Thierry,
looks like a rebase bug
dim: aad2a7d9d375 ("gpu: host1x: Update host1x_memory_context_alloc()
!IOMMU_API stub"): SHA1 in fixes line not found:
dim: 1508aa73ea38 ("gpu: host1x: Select context device based on
attached IOMMU")
dim: ERROR: issues in commits detected, aborting
Please
Commit f0601ef8631c ("drm/vc4: vec: Protect device resources after
removal") add fail path for vc4_vec_encoder_enable(), and will put
usage_counter only when pm_runtime_get_sync() succeeds. However,
pm_runtime_get_sync() will increment usage_counter even it failed. Fix
it by replacing it with pm_ru
On 11/16/22 02:26, David Hildenbrand wrote:
...
With this change, the new R/O long-term pinning tests for non-anonymous
memory succeed:
# [RUN] R/O longterm GUP pin ... with shared zeropage
ok 151 Longterm R/O pin is reliable
# [RUN] R/O longterm GUP pin ... with memfd
ok 152 Longterm
The dma_free_coherent() should be called when memory fails to
be allocated for list, or drm_map_handle() fails, otherwise there
will be a memory leak, so add dma_free_coherent to fix it.
In addition, if drm_map_handle() fails in drm_addmap_core(), list
will be freed, but list->head will not be rem
Add silicon specific compatible qcom,sc7280-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7280 against the yaml documentation.
Reviewed-by: Douglas Anderson
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
1 fil
Add silicon specific compatible qcom,msm8996-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8996 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 --
1 file changed, 4 insertions(+
Add silicon specific compatible qcom,sdm660-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm660 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 d
Add silicon specific compatible qcom,sdm845-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm845 against the yaml documentation.
Reviewed-by: Douglas Anderson
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 --
1
Add silicon specific compatible qcom,sm8250-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8250 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 --
1 file changed, 4 insertions(+),
Add silicon specific compatible qcom,sdm630-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm630 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 d
Each compatible has a different set of clocks which are associated with it.
Add in the list of clocks for each compatible.
Signed-off-by: Bryan O'Donoghue
---
.../display/msm/dsi-controller-main.yaml | 154 --
1 file changed, 143 insertions(+), 11 deletions(-)
diff --git
a
Currently we do not differentiate between the various users of the
qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one
compatible string but, the hardware does have some significant differences
in the number of clocks.
To facilitate documenting the clocks add the following compat
When converting from .txt to .yaml dt-binding descriptions we appear to
have missed some of the previous detail on the number and names of
permissible clocks.
Fix this by listing the clock descriptions against the clock names at a
high level.
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml
The existing msm8916.dtsi does not depend on nor require operating points.
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings")
Reviewed-by: Dmitry Baryshkov
Acked-by: Krzysztof Kozlowski
Signed-off-by: Bryan O'Donoghue
---
.../devicetree/bindings/display/msm/dsi-co
When converting from .txt to .yaml we didn't include descriptions for the
existing regulator supplies.
- vdd
- vdda
- vddio
Add those descriptions into the yaml now as they were prior to the
conversion. In the .txt description we marked these regulators as required,
however, that requirement appe
Add silicon specific compatible qcom,msm8916-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8916 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++-
1 file changed, 2 insertions(+),
Add silicon specific compatible qcom,sc7180-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7180 against the yaml documentation.
Reviewed-by: Douglas Anderson
Signed-off-by: Bryan O'Donoghue
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++-
1 fil
There's a typo in describing the core clock as an 'escape' clock. The
accurate description is 'core'.
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings")
Reviewed-by: Dmitry Baryshkov
Acked-by: Krzysztof Kozlowski
Signed-off-by: Bryan O'Donoghue
---
.../devicetree/
Add silicon specific compatible qcom,msm8974-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8974 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1
Append silicon specific compatible qcom,apq8064-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for apq8064 against the yaml documentation.
Reviewed-by: David Heidelberg
Signed-off-by: Bryan O'Donoghue
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 3 ++-
1
We will add in a number of compat strings to dsi-controller-main.yaml in
the format "qcom,socname-dsi-ctrl" convert the currently unused
qcom,dsi-ctrl-6g-qcm2290 to qcom,qcm2290-dsi-ctrl.
Signed-off-by: Bryan O'Donoghue
---
.../devicetree/bindings/display/msm/dsi-controller-main.yaml| 2 +-
power-domain is required for the sc7180 dispcc GDSC but not every qcom SoC
has a similar dependency for example the aqp8064.
Most Qcom SoC's using mdss-dsi-ctrl seem to have the ability to
power-collapse the MDP without collapsing DSI.
For example the qcom vendor kernel commit for apq8084, msm822
V3:
- Moves declaration of mdss-dsi-ctrl into compat string declaration
patch - Krzysztof, Dmitry
- Renames qcm-2290 compat string to agreed compat "qcom,socname-dsi-ctrl"
Dmirty, Krzysztof
- Adds empty line after if clause in yaml control flow section - Dmirty
- Adds Rb/Ack - Krzysztof, Dmitry
On 24.11.2022 01:16, Adam Skladowski wrote:
> Add required display hw catalog changes for SM6115.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Adam Skladowski
> ---
Reviewed-by: Konrad Dybcio
Konrad
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 87 +++
> .../gpu/d
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not re
Add required display hw catalog changes for SM6115.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Adam Skladowski
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 87 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
This patch series add support for MDSS and DPU block found on SM6115.
These patches were tested on Xiaomi Redmi 9T smartphone.
Changes since v1
1. Adjusted YAMLs per requests.
2. Changed MDP regs to lowercase hex.
3. Rebased series over latest next and SM8450 patches.
Adam Sklado
On Wed, Nov 23, 2022 at 02:46:18PM -0800, John Harrison wrote:
> On 11/17/2022 09:33, Matt Roper wrote:
> > ...
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 830edffe88cc..d9a8ff9e5e57 100644
> > --- a/drivers/gpu/drm/i915/gt/in
The fence is only tracking if the HuC load is in progress or not and
doesn't distinguish between already loaded, not supported or disabled,
so we can always initialize it to completed, no matter the actual
support. We already do that for most platforms, but we skip it on
GTs that lack VCS engines (
Hi, Dave & Daniel:
This includes:
1. Fixup of dpi and hdmi
2. Move panel connector to head
3. Add MT8188 dpi support
4. Add MT8195 AFBC support
Regards,
Chun-Kuang.
The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780:
Linux 6.1-rc1 (2022-10-16 15:36:24 -0700)
are ava
On 11/9/2022 1:18 AM, Pekka Paalanen wrote:
On Tue, 8 Nov 2022 23:01:47 +0100
Sebastian Wick wrote:
On Tue, Nov 8, 2022 at 7:51 PM Simon Ser wrote:
cc'ing Pekka and wayland-devel for userspace devs feedback on the new uAPI.
Hi all,
thanks! Comments below.
Thanks for the feedback!
On 20/11/2022 15:37, Adam Skladowski wrote:
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
On 11/17/2022 09:33, Matt Roper wrote:
...
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 830edffe88cc..d9a8ff9e5e57 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -730,17 +730,19 @@ void in
From: John Harrison
As a precursor to a coming change (for adding a GuC submission API
version), abstract the UC version number into its own private
structure separate to the firmware filename.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/int
From: John Harrison
The way delimiters (underscores and dots) were added to the UC
filenames was different for different types of delimiter. Rationalise
them to all be done the same way - implicitly in the concatenation
macro rather than explicitly in the file name prefix.
Signed-off-by: John Ha
From: John Harrison
Start using the 'submission API version' for deciding which GuC API to
use in the submission code.
Correct version number manipulation code to support full 32bit
major/minor/patch components, except for GuC which is guaranteed to be
8bit safe.
Other minor code clean ups arou
From: John Harrison
The GuC firmware includes an extra version number to specify the
submission API level. So use that rather than the main firmware
version number for submission related checks.
Also, while it is guaranteed that GuC version number components are
only 8-bits in size, other firmwa
Replace the use of drm_debugfs_create_files() with the new
drm_debugfs_add_files() function, which centers the debugfs files
management on the drm_device instead of drm_minor. Moreover, remove the
debugfs_init hook and add the debugfs files directly on vkms_create(),
before drm_dev_register().
Sig
The structs drm_debugfs_info and drm_debugfs_entry introduced a new
debugfs structure to DRM, centered on drm_device instead of drm_minor.
Therefore, remove the tasks related to create a new device-centered
debugfs structure and add a new task to replace the use of
drm_debugfs_create_files() for th
Replace the use of drm_debugfs_create_files() with the new
drm_debugfs_add_files() function in all DRM core files, centering the
debugfs files management on the drm_device instead of drm_minor.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/drm_atomic.c | 11 +--
drivers/gpu/drm
Replace the use of drm_debugfs_create_files() with the new
drm_debugfs_add_files() function, which centers the debugfs files
management on the drm_device instead of drm_minor.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 22 ++
1 file changed, 10 inserti
Introduce the ability to track requests for the addition of DRM debugfs
files at any time and have them added all at once during
drm_dev_register().
Drivers can add DRM debugfs files to a device-managed list and, during
drm_dev_register(), all added files will be created at once.
Now, the drivers
Currently, vc4 has its own debugfs infrastructure that adds the debugfs
files on drm_dev_register(). With the introduction of the new debugfs,
functions, replace the vc4 debugfs structure with the DRM debugfs
device-centered function, drm_debugfs_add_file().
Moreover, remove the explicit error han
This series introduces the initial structure to make DRM debugfs more
device-centered and it is the first step to drop the
drm_driver->debugfs_init hooks in the future [1].
Currently, DRM debugfs files are created using drm_debugfs_create_files()
on request. The first patch of this series makes it
From: Vinod Koul
Add the LT9611uxc DSI-HDMI bridge and supplies
Signed-off-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 59 +
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/
Enable MDSS/DPU/DSI0 on SM8450-HDK device.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
b/arch/arm64/boot/dts/qcom/sm845
Add devices tree nodes describing display hardware on SM8450:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs
This does not provide support for DP controllers present on SM8450.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/s
From: Vinod Koul
Add the HDMI display nodes and link it to DSI.
Signed-off-by: Vinod Koul
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 36 +
1 file changed, 36 insertions(+)
Add another power saving state used on SM8450. Unfortunately adding it
in proper place causes renumbering of all the opp states in sm8450.dtsi
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20
include/dt-bindings/pow
Add device tree nodes for MDSS, DPU and DSI devices on Qualcomm SM8450
platform. Enable these devices and add the HDMI bridge configuration on
SM8450 HDK.
Changes since v2:
- Dropped clock-names from mdss device node
- Fixed pinctrl configuration used by lt9611uxc (Krzysztof)
Changes since v1:
-
On 23/11/2022 01:54, Dmitry Baryshkov wrote:
On 20/11/2022 15:37, Adam Skladowski wrote:
Add required display hw catalog changes for SM6115.
Signed-off-by: Adam Skladowski
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 87 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.
Co-developed-by: Robert Foss
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: D
Add support for DSI 2.6.0 (block used on sm8450).
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 3 inse
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/
Add definitions for the display hardware used on Qualcomm SM8450
platform.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 224 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_cata
Add support for the MDSS block on SM8450 platform.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/m
Require only properties declared in given schema, which makes the code a
bit more readable and easy to follow.
Suggested-by: Krzysztof Kozlowski
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 -
.../device
In preparation to adding the sm8350 and sm8450 PHYs support, rearrange
register values calculations in dsi_7nm_phy_enable(). This change bears
no functional changes itself, it is merely a preparation for the next
patch.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/
SM8350 and SM8450 platforms use the same driver and same bindings as the
existing 7nm DSI PHYs. Add corresponding compatibility strings.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++
1 file changed, 2 ins
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8450 platform.
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 +++
.../display/msm/qcom,sm8450-mdss.yaml | 343 ++
2 files changed, 482 insertions(+)
c
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Change since v4:
- Fixed commit messages for the first two patches (Krzysztof)
- Dropped clock-names requirement patch
- Removed clock-names from qcom,sm8450-mdss.yaml schema
- Fixed the schema changes lost between v3 and v4 (
Require only properties declared in given schema, which makes the code a
bit more readable and easy to follow.
Suggested-by: Krzysztof Kozlowski
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-common.yaml| 4
.../devicet
On 23/11/2022 11:01, Krzysztof Kozlowski wrote:
On 23/11/2022 00:36, Dmitry Baryshkov wrote:
From: Vinod Koul
Add the LT9611uxc DSI-HDMI bridge and supplies
Signed-off-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
+
&sdhc_2 {
cd-gpios = <&tlmm 9
On 23.11.2022 02:25, John Harrison wrote:
> On 11/22/2022 09:54, Michal Wajdeczko wrote:
>> On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
>>> From: John Harrison
>>>
>>> Re-work the existing GuC CT printers and extend as required to match
>>> the new wrapping scheme.
>>>
>>> Signed-off-
On 23/11/2022 12:19, Krzysztof Kozlowski wrote:
On 23/11/2022 00:12, Dmitry Baryshkov wrote:
Mark clock-names property as required to be used on all MDSS devices.
This we see from the diff. Please tell why you are doing it. In some
other recent bindings we dropped clock-names from required, so
On Wed, Nov 23, 2022 at 10:05:29AM +, Hsin-Yi Wang wrote:
> it6505 supports HDCP 1.3, but current implementation lacks the update of
> HDCP status through drm_hdcp_update_content_protection().
>
> it6505 default enables the HDCP. Remove this and only turn on when user
> requests it.
>
> Signe
On Sat, Nov 19, 2022 at 7:45 PM Marek Vasut wrote:
>
> On 11/17/22 14:04, Marek Szyprowski wrote:
> > On 17.11.2022 05:58, Marek Vasut wrote:
> >> On 11/10/22 19:38, Jagan Teki wrote:
> >>> DSI host initialization handling in previous exynos dsi driver has
> >>> some pitfalls. It initializes the h
I no longer have access to the HiKey boards, so while I'm happy to
review code, I wanted to add Sumit and Yongqin to the reviewers list
so they would get CC'ed on future changes and would be able to have
a chance to validate and provide Tested-by: tags
Cc: Xinliang Liu
Cc: Tian Tao
Cc: Yongqin
From: John Harrison
Create a set of GuC printers and start using them.
v2: Tweaks to output messages. (review feedback from Michal W).
Split definitions to separate header (review feedback from Jani).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 33 +---
From: John Harrison
Create a set of HuC printers and start using them.
v2: Minor tweaks (review feedback from MichalW).
Split definitions into separate header (review feedback from Jani).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 32
From: John Harrison
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a
From: John Harrison
Re-work the existing GuC CT printers and extend as required to match
the new wrapping scheme.
v2: Improve probe_error definition (review feedback from MichalW).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 218 +++---
1 file
From: John Harrison
Use the new module oriented output message helpers where possible.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 110 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 99 ++--
2 files changed, 102 insertions(+
From: John Harrison
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a
On 11/23/22 11:35, T.J. Mercier wrote:
> I've been collecting these typo fixes for a while and it feels like
> time to send them in.
>
> Signed-off-by: T.J. Mercier
Reviewed-by: Randy Dunlap
Thanks.
(although I would prefer to see CPU instead of cpu, but that's no
reason to hold up this pa
I've been collecting these typo fixes for a while and it feels like
time to send them in.
Signed-off-by: T.J. Mercier
---
drivers/dma-buf/dma-buf.c | 14 +++---
include/linux/dma-buf.h | 6 +++---
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/dma-buf/dma-buf
On 23/11/2022 12:15, Krzysztof Kozlowski wrote:
On 23/11/2022 00:12, Dmitry Baryshkov wrote:
Per Krzysztof's request, move a clause requiring certain properties to
the file where they are declared.
Commit msg could be a bit more generic, without naming me (there are few
Krzysztofs), e.g.:
Re
It's a bit a FAQ, and we really can't claim to be the authoritative
source for allocating these numbers used in many standard extensions
if we tell closed source or vendor stacks in general to go away.
Iirc this was already clarified in some vulkan discussions, but I
can't find that anywhere anymo
On Mon, Nov 21, 2022 at 10:24 AM Christian König
wrote:
>
> Hi Dawei,
>
> from the technical description, coding style etc.. it looks clean to me,
> but I'm the completely wrong person to ask for a background check.
>
> I have a high level understanding of how dma-heaps work, but not a
> single li
Hi Tvrtko,
[...]
> > @@ -768,6 +768,9 @@ i915_vma_insert(struct i915_vma *vma, struct
> > i915_gem_ww_ctx *ww,
> > GEM_BUG_ON(!IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
> > GEM_BUG_ON(!is_power_of_2(alignment));
> > + guard = vma->guard; /* retain guard across rebinds */
> > +
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 736b6d81d93cf61a0601af90bd552103ef997b3f Add linux-next specific
files for 20221123
Error/Warning reports:
https://lore.kernel.org/linux-mm/202210261404.b6ulzg7h-...@intel.com
https
On Tue, Nov 22, 2022 at 02:58:37PM -0800, Ceraolo Spurio, Daniele wrote:
>
>
> On 11/22/2022 12:52 PM, Rodrigo Vivi wrote:
> > On Mon, Nov 21, 2022 at 03:16:16PM -0800, Daniele Ceraolo Spurio wrote:
> > > From: Jonathan Cavitt
> > >
> > > The GSC CS is only used for communicating with the GSC F
On Tue, Nov 22, 2022 at 02:50:17PM -0800, Ceraolo Spurio, Daniele wrote:
>
>
> On 11/22/2022 12:46 PM, Rodrigo Vivi wrote:
> > On Mon, Nov 21, 2022 at 03:16:15PM -0800, Daniele Ceraolo Spurio wrote:
> > > If the GSC was loaded, the only way to stop it during the driver unload
> > > flow is to do
The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timi
Move rcar_du_vsp_atomic_begin() to RCar DU VSP lib.
Signed-off-by: Biju Das
---
v6:
* Rebased on drm-misc-next and DU-next.
v1->v2:
* Rebased on drm-misc-next and DU-next.
---
drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 -
drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 2 --
drivers/gpu/drm
Move rcar_du_vsp_atomic_flush() to RCar DU vsp lib.
Signed-off-by: Biju Das
---
v6:
* Rebased on drm-misc-next and DU-next.
v1->v2:
* Rebased on drm-misc-next and DU-next.
---
drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 13 -
drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 2 --
drive
RZ/G2L does not have plane registers as well as it uses different
CRTC. The below functions are SoC specific
* rcar_du_crtc_finish_page_flip()
* __rcar_du_plane_setup
* __rcar_du_plane_atomic_check
All other function can be handled in common code. This patch introduces
rcar_du_lib_vsp_init() to
RZ/G2L supports only DSI and DPI. Add rcar_du_encoders_init() to handle
the pointer to du_output_name(), so that we can share du_encoders_init()
between RCar and RZ/G2L kms drivers.
Signed-off-by: Biju Das
---
v5->v6:
* Updated header files.
v5:
* New patch
---
drivers/gpu/drm/rcar-du/rcar_du_
Add rcar_du_lib_mode_cfg_helper_get() in RCar DU kms lib to get the
pointer to rcar_du_mode_config_helper, so that both rcar_du_atomic_
commit_tail() and rcar_du_mode_config_helper can be reused by
rcar_du_modeset_init() and rzg2l_du_modeset_init().
Signed-off-by: Biju Das
---
v5->v6:
* Updated
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