https://bugzilla.kernel.org/show_bug.cgi?id=216716
Bug ID: 216716
Summary: [drm:psp_resume [amdgpu]] *ERROR* PSP resume failed on
r9 7950x igpu
Product: Drivers
Version: 2.5
Kernel Version: 6.0.9
Hardware: All
Add bindings for Cadence HDP-TX HDMI PHY.
Signed-off-by: Sandor Yu
---
.../bindings/phy/cdns,hdptx-hdmi-phy.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml
diff --git a/Documentation/devicetr
Add Cadence HDP-TX HDMI PHY driver.
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
HDMI PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
---
drivers/phy/cadence/Kconfig | 8 +
drivers/phy/cadence/Makefile
Add Cadence HDP-TX DisplayPort PHY driver.
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
DisplayPort PHY mode is configurated in the driver.
Signed-off-by: Sandor Yu
---
drivers/phy/cadence/Kconfig| 8 +
drivers/phy/cadence/Ma
Add a new DRM HDMI bridge driver for Candence MHDP used in i.MX8MQ
SOC. MHDP IP could support HDMI or DisplayPort standards according
embedded Firmware running in the uCPU.
For iMX8MQ SOC, the HDMI FW was loaded and activated by SOC ROM code.
Bootload binary included HDMI FW was required for the d
Add bindings for Cadence HDP-TX DisplayPort PHY.
Signed-off-by: Sandor Yu
---
.../bindings/phy/cdns,hdptx-dp-phy.yaml | 68 +++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml
diff --git a/Documentation/devi
Add bindings for i.MX8MQ MHDP HDMI.
Signed-off-by: Sandor Yu
---
.../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml
diff --git
a/Documentation/
Add bindings for i.MX8MQ MHDP DisplayPort.
Signed-off-by: Sandor Yu
---
.../display/bridge/cdns,mhdp-imx8mq-dp.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml
diff --git
a/Documenta
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
---
include/l
Add a new DRM DisplayPort bridge driver for Candence MHDP
used in i.MX8MQ SOC. MHDP IP could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort FW was loaded and activated by SOC
ROM code. Bootload binary included HDMI FW was requ
Mailbox access functions could be share to other mhdp driver and
HDP-TX HDMI/DP PHY drivers, move those functions to head file
include/drm/bridge/cdns-mhdp-mailbox.h and convert them to
macro functions.
Signed-off-by: Sandor Yu
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 197 +---
The patch set initial support for Cadence MHDP(HDMI/DP) DRM bridge
drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for iMX8MQ.
The patch set compose of DRM bridge drivers and PHY drivers.
Both of them need the followed two patches to pass build.
drm: bridge: cadence: convert mailbox functions to
One-element arrays are deprecated, and we are replacing them with
flexible array members instead. So, replace one-element array with
flexible-array member in struct GOP_VBIOS_CONTENT and refactor the
rest of the code accordingly.
Important to mention is that doing a build before/after this patch
r
tree: git://anongit.freedesktop.org/drm/drm drm-next
head: a143bc517bf31c4575191efbaac216a11ec016e0
commit: 67059b9fb8997f3d4515d72052c331503b00274b [741/803] drm/nouveau/fifo:
add chan start()/stop()
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
includecheck warnings: (new ones prefixed by >>)
On Sun, 20 Nov 2022 at 06:44, Oded Gabbay wrote:
>
> This is the fourth (and hopefully last) version of the patch-set to add the
> new subsystem for compute accelerators. I removed the RFC headline as
> I believe it is now ready for merging.
>
> Compare to v3, this patch-set contains one additiona
Hi all,
Friendly ping on this patch.
Regards,
Pin-yen
On Thu, Nov 3, 2022 at 5:13 PM allen wrote:
>
> From: allen chen
>
> Add driver to read data-lanes and link-frequencies from dt property to
> restrict output bandwidth.
>
> Signed-off-by: Allen chen
> Signed-off-by: Pin-yen Lin
> ---
> dr
Hi,
2022년 11월 8일 (화) 오전 2:52, Paul Cercueil 님이 작성:
>
> Use the DEFINE_RUNTIME_DEV_PM_OPS(), SYSTEM_SLEEP_PM_OPS(),
> RUNTIME_PM_OPS() and pm_ptr() macros to handle the runtime and suspend
> PM callbacks.
>
> These macros allow the suspend and resume functions to be automatically
> dropped by the c
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
between commit:
b09d6acba1d9 ("drm/amdgpu: handle gang submit before VMID")
from the drm-misc-fixes tree and commits:
c5093cddf56b ("drm/amdgpu: drop the fence argument from amdgp
On 11/19/2022 1:44 PM, Oded Gabbay wrote:
This is the fourth (and hopefully last) version of the patch-set to add the
new subsystem for compute accelerators. I removed the RFC headline as
I believe it is now ready for merging.
Compare to v3, this patch-set contains one additional patch that adds
On 11/19/2022 1:44 PM, Oded Gabbay wrote:
Add an introduction section for the accel subsystem. Most of the
relevant data is in the DRM documentation, so the introduction only
presents the why of the new subsystem, how are the compute accelerators
exposed to user-space and what changes need to be
https://bugzilla.kernel.org/show_bug.cgi?id=213145
Viktor (sgas...@gmail.com) changed:
What|Removed |Added
CC||sgas...@gmail.com
--- Commen
On 11/19/2022 1:44 PM, Oded Gabbay wrote:
diff --git a/drivers/accel/drm_accel.c b/drivers/accel/drm_accel.c
index fac6ad6ac28e..703d40c4ff45 100644
--- a/drivers/accel/drm_accel.c
+++ b/drivers/accel/drm_accel.c
@@ -8,14 +8,25 @@
#include
#include
+#include
Including xarray, but using
syzbot has bisected this issue to:
commit 997acaf6b4b59c6a9c259740312a69ea549cc684
Author: Mark Rutland
Date: Mon Jan 11 15:37:07 2021 +
lockdep: report broken irq restoration
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=115b350d88
start commit: 84368d882b96 Merg
[Note: this mail is primarily send for documentation purposes and/or for
regzbot, my Linux kernel regression tracking bot. That's why I removed
most or all folks from the list of recipients, but left any that looked
like a mailing lists. These mails usually contain '#forregzbot' in the
subject, to
On Wed, 16 Nov 2022 17:32:18 +0100, Konrad Dybcio wrote:
> On some SoCs (hello SM6350) vdds-supply is not wired to any smd-rpm
> or rpmh regulator, but instead powered by the VDD_MX/mx.lvl line,
> which is voted for in the DSI ctrl node.
>
> Signed-off-by: Konrad Dybcio
> ---
> Documentation/d
On Sun, Nov 20, 2022 at 02:37:36PM +0100, Adam Skladowski wrote:
> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
> SM6115 platform.
> Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
> Lack of dsi phy supply in example is intended
> due to fact
On Sat, Nov 19, 2022 at 10:44:31PM +0200, Oded Gabbay wrote:
> This is the fourth (and hopefully last) version of the patch-set to add the
> new subsystem for compute accelerators. I removed the RFC headline as
> I believe it is now ready for merging.
>
> Compare to v3, this patch-set contains one
This patch series add support for MDSS and DPU block found on SM6115.
These patches were tested on Xiaomi Redmi 9T smartphone.
Adam Skladowski (2):
dt-bindings: display/msm: add support for the display on SM6115
drm/msm/disp/dpu1: add support for display on SM6115
.../bindings/display/msm/qc
From: Lino Sanfilippo
In vc4_platform_drm_probe() function vc4_match_add_drivers() is called to
find component matches for the component drivers. If no such match is found
the passed variable "match" is still NULL after the function returns.
Do not pass "match" to component_master_add_with_match
Add required display hw catalog changes for SM6115.
Signed-off-by: Adam Skladowski
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 87 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not re
On Sun, 20 Nov 2022 14:37:36 +0100, Adam Skladowski wrote:
> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
> SM6115 platform.
> Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
> Lack of dsi phy supply in example is intended
> due to fact on q
The vrefresh field in drm_display_mode struct was removed so the
function no longer checks if it is set before calculating it.
Fixes: 0425662fdf05 ("drm: Nuke mode->vrefresh")
Signed-off-by: Jonathan Liu
---
drivers/gpu/drm/drm_modes.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
dif
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