From: Kees Cook
Implement a robust overflows_type() macro to test if a variable or
constant value would overflow another variable or type. This can be
used as a constant expression for static_assert() (which requires a
constant expression[1][2]) when used on constant values. This must be
construc
On 27 9月 22 13:38:47, Yuan Can wrote:
> After commit 64ff18911878("drm/omap: Enable COLOR_ENCODING and COLOR_RANGE
Hi yuan,
This is not a valid Fixes: tag.
Add to your ~/.gitconfig and add:
[pretty]
fixes = Fixes: %h (\"%s\")
You can then do
git log --pretty=fixes 64ff18911878
and get
On 10/12/22 21:18, Kees Cook wrote:
Add MIPS to fb_* helpers list for iomem addresses. This silences Sparse
warnings about lacking __iomem address space casts:
drivers/video/fbdev/pvr2fb.c:800:9: sparse: sparse: incorrect type in argument
1 (different address spaces)
drivers/video/fbdev/pvr2fb.
On Wed, 2022-10-12 at 21:29 +, David Laight wrote:
> From: Joe Perches
> > Sent: 12 October 2022 20:17
> >
> > On Wed, 2022-10-05 at 23:48 +0200, Jason A. Donenfeld wrote:
> > > The prandom_u32() function has been a deprecated inline wrapper around
> > > get_random_u32() for several releases n
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be loaded on
the same GGTT at the same time. On MTL, however, this can happend if both
GTs are reset at t
From: Stuart Summers
MTL supports GuC deprivilege. Add the feature flag to this platform.
Signed-off-by: Stuart Summers
Cc: Radhakrishna Sripada
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
On MTL the primary GT doesn't have any media capabilities, so no video
engines and no HuC. We must therefore skip the HuC fetch and load on
that specific case. Given that other multi-GT platforms might have HuC
on the primary GT, we can't just check for that and it is easier to
instead check for th
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB for GCD/GT.
+=+===> ++ <== WOPCM TOP
The render and media GuCs share the same interrupt enable register, so
we can no longer disable interrupts when we disable communication for
one of the GuCs as this would impact the other GuC. Instead, we keep the
interrupts always enabled in HW and use a variable in the GuC structure
to determine
The FW binaries are independently loaded on each GT. On MTL, the memory
is shared so we could potentially re-use a single allocation, but on
discrete multi-gt platforms we are going to need independent copies,
so it is easier to do the same on MTL as well, given that the amount
of duplicated memory
The media GT shares the G-unit with the root GT, so a second set of
communication registers is required for the media GuC.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++
dri
The introduction of the media GT brings a few changes for GuC/HuC. The
main difference between the 2 GTs is that only the media one has the
HuC, while both have the GuC. Also, the fact that both GTs use the same
G-unit and GGTT means we now have parallel interrupt/communication
paths. Lastly, WOPCM
On 10/9/2022 11:53 AM, Marijn Suijten wrote:
The bpg_offset array contains negative BPG offsets which fill the full 8
bits of a char thanks to two's complement: this however results in those
bits bleeding into the next field when the value is packed into DSC PPS
by the drm_dsc_helper function,
On 10/9/2022 11:53 AM, Marijn Suijten wrote:
drm_dsc_config's bits_per_pixel field holds a fractional value with 4
bits, which all panel drivers should adhere to for
drm_dsc_pps_payload_pack() to generate a valid payload. All code in the
DSI driver here seems to assume that this field doesn't
On 10/9/2022 11:51 AM, Marijn Suijten wrote:
According to the `/* bpc 8 */` comment below only values for a
bits_per_component of 8 are currently hardcoded in place. This is
further confirmed by downstream sources [1] containing different
constants for other BPC values (and different initial_
On 10/9/2022 11:50 AM, Marijn Suijten wrote:
As per the FIXME this code is entirely duplicate with what is already
provided inside drm_dsc_compute_rc_parameters(), and it is yet unknown
why this comment was put in place instead of resolved from the get-go.
Not only does it save on duplication,
On 10/9/2022 11:48 AM, Marijn Suijten wrote:
This field is currently unread but will come into effect when duplicated
code below is migrated to call drm_dsc_compute_rc_parameters(), which
uses the bpc-dependent value of the local variable mux_words_size in
much the same way.
The hardcoded con
...oops, totally forgot to actually give you the magic tag so patchwork knows
I reviewed it:
Reviewed-by: Lyude Paul
On Sat, 2022-09-24 at 17:25 +0800, ruanjinjie wrote:
> When build Linux kernel with 'make C=2', encounter the following warnings:
>
> ./drivers/gpu/drm/nouveau/dispnv50/disp.c:13
Looks good to me (sorry for the slow response! I think this one just got lost
in the noise). Will push to drm-misc-next in a moment
On Sat, 2022-09-24 at 17:25 +0800, ruanjinjie wrote:
> When build Linux kernel with 'make C=2', encounter the following warnings:
>
> ./drivers/gpu/drm/nouveau/dispn
The RTNI field is multiplied by 16 and incremented by 512 before being
used as the minimum number of pixel clock per horizontal line, hence
it is necessary to subtract those 512 bytes from htotal and then divide
the result by 16 before writing the value into the RTNI field. Fix the
calculation.
Fi
From: Joe Perches
> Sent: 12 October 2022 20:17
>
> On Wed, 2022-10-05 at 23:48 +0200, Jason A. Donenfeld wrote:
> > The prandom_u32() function has been a deprecated inline wrapper around
> > get_random_u32() for several releases now, and compiles down to the
> > exact same code. Replace the depre
On Mon, Oct 10, 2022 at 10:36:00PM +0200, Linus Walleij wrote:
> On Thu, Oct 6, 2022 at 12:05 PM Daniel Thompson
> wrote:
> > On Thu, Oct 06, 2022 at 11:03:15AM +0200, Linus Walleij wrote:
> > > On Tue, Oct 4, 2022 at 10:35 PM Dmitry Torokhov
> > > wrote:
> > >
> > > > > Dmitry, could you fix thi
On Sat, Oct 8, 2022 at 10:43 AM Konrad Dybcio
wrote:
>
> drm/msm capitalizes hex numbers rather randomly. Try to unify it.
yeah, there were some different preferences of various patch authors
for shouty HEX vs quiet hex... tbh I prefer the latter, but not really
sure it is worth the noise in git
Add MIPS to fb_* helpers list for iomem addresses. This silences Sparse
warnings about lacking __iomem address space casts:
drivers/video/fbdev/pvr2fb.c:800:9: sparse: sparse: incorrect type in argument
1 (different address spaces)
drivers/video/fbdev/pvr2fb.c:800:9: sparse: expected void con
On Wed, 2022-10-05 at 23:48 +0200, Jason A. Donenfeld wrote:
> The prandom_u32() function has been a deprecated inline wrapper around
> get_random_u32() for several releases now, and compiles down to the
> exact same code. Replace the deprecated wrapper with a direct call to
> the real function.
[]
Tested on MT8195 and confirmed both correct video output and improved DRAM
bandwidth performance.
v3:
* Replaced pitch bitshift math with union based approach.
* Refactored overlay register writes to shared code between non-AFBC and
AFBC.
* Minor code cleanups.
v2:
* Marked mtk_ovl_set_afbc as
On Wed, Oct 12, 2022 at 11:51:48AM +0300, Jani Nikula wrote:
On Tue, 11 Oct 2022, Lucas De Marchi wrote:
Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
ranges. This should cover most of our needs for _MMIO_PLL3 and such.
To show what is achieved with the new macro, convert so
GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.
Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.
Signed-o
By crash, I mean that an error is returned here:
https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux.git/+/refs/heads/master/drivers/gpu/drm/drm_edid_load.c#195
I don't really know what happens next, but on my machine the built-in
screen and the external remains dark. Also the
Move the DPCD read and link setup steps to HPD IRQ handler to remove
an unnecessary dependency between .detect callback and the HPD IRQ
handler before registering it6505 as a DRM bridge. This is safe because
there is always a .detect call after each HPD IRQ handler triggered by
the drm_helper_hpd_i
Originally, the it6505 relies on a short sleep in the IRQ handler and a
long sleep to make sure it6505->lane_swap and it6505->lane_count is
configured in it6505_extcon_work and it6505_detect, respectively.
Use completion and additional DPCD read to remove the unnecessary waits,
and use a different
During device boot, the HPD interrupt could be triggered before the DRM
subsystem registers it6505 as a DRM bridge. In such cases, the driver
tries to access AUX channel and causes NULL pointer dereference.
Initializing the AUX channel earlier to prevent such error.
Fixes: b5c84a9edcd4 ("drm/bridg
The main purpose of this series is to improve the synchronizations of
it6505 driver. The first two patches are required for the third one, but
they alone can be clean ups to the driver.
Pin-yen Lin (3):
drm/bridge: it6505: Initialize AUX channel in it6505_i2c_probe
drm/bridge: it6505: Setup l
Hi Dave, Daniel,
Fixes for 6.1.
The following changes since commit 65898687cf7392c372ea8d04a88617e2cb794465:
Merge tag 'amd-drm-next-6.1-2022-09-30' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2022-10-04 09:42:24
+1000)
are available in the Git repository at:
https://git
On 30.09.2022 17:45, Matt Roper wrote:
> Rather than relying on the implicit behavior of intel_uncore_*()
> functions, let's always use the intel_gt_mcr_*() functions to operate on
> multicast/replicated registers.
>
> v2:
> - Add TLB invalidation registers
>
> Signed-off-by: Matt Roper
> ---
>
On Wed, Oct 12, 2022 at 05:59:45PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 12, 2022 at 04:31:14PM +0200, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 12.10.22 um 15:12 schrieb Arnd Bergmann:
> > > On Wed, Oct 12, 2022, at 2:00 PM, Thomas Zimmermann wrote:
> > >>
> > >> Could well be. But ofdrm int
On Wed, Oct 12, 2022 at 11:32:18AM +0100, Matthew Auld wrote:
On 10/10/2022 07:58, Niranjana Vishwanathapura wrote:
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not hav
Il 12/10/22 16:12, Justin Green ha scritto:
These would be different from the macros that are available in bitfield.h, but
not *fundamentally* different, so these would look a little redundant...
I think that you refer to that `pitch` variable that's coming from the DRM(/fb)
API... and bitfield
Hi Danilo,
Appologies again for the delay in reviewing this as I was at XDC last week.
This patch is causing a regression at 'rmmod' time as the drm_crtc_vblank_off()
does
not get called when we disable outputs and the HDLCD remains active as I keep
getting
unhandled context faults from the arm
On Wed, Oct 12, 2022 at 04:31:14PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 12.10.22 um 15:12 schrieb Arnd Bergmann:
> > On Wed, Oct 12, 2022, at 2:00 PM, Thomas Zimmermann wrote:
> >>
> >> Could well be. But ofdrm intents to replace offb and this test has
> >> worked well in offb for almost 15
Hi
Am 12.10.22 um 15:12 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 2:00 PM, Thomas Zimmermann wrote:
Could well be. But ofdrm intents to replace offb and this test has
worked well in offb for almost 15 yrs. If there are bug reports, I'm
happy to take patches, but until then I see no reaso
Hello,
On Wed, Oct 12, 2022 at 03:12:35PM +0200, Arnd Bergmann wrote:
> On Wed, Oct 12, 2022, at 2:00 PM, Thomas Zimmermann wrote:
> >
> > Could well be. But ofdrm intents to replace offb and this test has
> > worked well in offb for almost 15 yrs. If there are bug reports, I'm
> > happy to take
> These would be different from the macros that are available in bitfield.h, but
> not *fundamentally* different, so these would look a little redundant...
>
> I think that you refer to that `pitch` variable that's coming from the
> DRM(/fb)
> API... and bitfield macros are for register access...
On Wed, 12 Oct 2022, Maxime Ripard wrote:
> On Wed, Oct 12, 2022 at 03:32:32PM +0300, Jani Nikula wrote:
>> On Tue, 11 Oct 2022, Jani Nikula wrote:
>> > While it takes more vertical space, sorted build lists with one object
>> > per line are arguably easier to manage, especially when there are
>>
Applied. Thanks!
Alex
On Wed, Oct 12, 2022 at 3:37 AM Yang Yingliang wrote:
>
> After commit 571c05365892 ("drm/amdgpu: switch sdma buffer function
> tear down to a helper"), the variable 'ring' is not used anymore, it
> can be removed.
>
> Signed-off-by: Yang Yingliang
> ---
> drivers/gpu/dr
That essentially looks like the right approach, but I would go a few
steps further.
I think we should add a drm_sched_fence_set_parent() function to
sched_fence.c and move a good part of the handling into that C file.
Just a simple signal function which tells the scheduler that it should
decr
Hi, I just wonder is there any further comment towards this patch? or
anything needs to be correct?
Greetings,
Zeng Heng
On 2022/9/22 17:18, Zeng Heng wrote:
Fix below compile warning when open enum-conversion
option check (compiled with -Wenum-conversion):
drivers/gpu/drm/amd/amdgpu/../di
This is purely a timing issue. Here, sometimes Job free
is happening before the job is done.
To fix this issue moving 'dma_fence_cb' callback from
job(struct drm_sched_job) to scheduler fence (struct drm_sched_fence).
BUG: kernel NULL pointer dereference, address: 0088
#PF: supervisor
On Wed, 12 Oct 2022 12:32:53 +
Simon Ser wrote:
> Introduce a new DRM_IOCTL_SYNCOBJ_EVENTFD IOCTL which signals an
> eventfd from a syncobj.
>
> This is useful for Wayland compositors to handle wait-before-submit.
> Wayland clients can send a timeline point to the compositor
> before the poi
On Wed, Oct 12, 2022, at 2:00 PM, Thomas Zimmermann wrote:
>
> Could well be. But ofdrm intents to replace offb and this test has
> worked well in offb for almost 15 yrs. If there are bug reports, I'm
> happy to take patches, but until then I see no reason to change it.
I wouldn't change the cod
On Wed, Oct 12, 2022 at 03:32:32PM +0300, Jani Nikula wrote:
> On Tue, 11 Oct 2022, Jani Nikula wrote:
> > While it takes more vertical space, sorted build lists with one object
> > per line are arguably easier to manage, especially when there are
> > conflicting changes.
> >
> > Split anything wi
On 2022/10/12 20:56, Christian König wrote:
Am 12.10.22 um 14:47 schrieb Zeng Heng:
Remove unnecessary `drm_mm_clean` calling in
`ttm_range_man_fini_nocheck`, due to effective
check is already included in the following
`drm_mm_takedown`.
Signed-off-by: Zeng Heng
Reviewed-by: Christian Köni
Am 12.10.22 um 14:47 schrieb Zeng Heng:
Remove unnecessary `drm_mm_clean` calling in
`ttm_range_man_fini_nocheck`, due to effective
check is already included in the following
`drm_mm_takedown`.
Signed-off-by: Zeng Heng
Reviewed-by: Christian König
Can you push it to drm-misc-next or should
Remove unnecessary `drm_mm_clean` calling in
`ttm_range_man_fini_nocheck`, due to effective
check is already included in the following
`drm_mm_takedown`.
Signed-off-by: Zeng Heng
---
drivers/gpu/drm/ttm/ttm_range_manager.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/tt
Am 12.10.22 um 14:32 schrieb Simon Ser:
Introduce a new DRM_IOCTL_SYNCOBJ_EVENTFD IOCTL which signals an
eventfd from a syncobj.
This is useful for Wayland compositors to handle wait-before-submit.
Wayland clients can send a timeline point to the compositor
before the point has materialized yet,
On 28/09/2022 20:52, Aradhya Bhatia wrote:
The AM625 DSS IP contains 2 OLDI TXes which can work to enable 2
duplicated displays of smaller resolutions or enable a single Dual Link
display with a higher resolution (1920x1200).
Configure the necessary register to enable and disable the OLDI TXes
w
Introduce a new DRM_IOCTL_SYNCOBJ_EVENTFD IOCTL which signals an
eventfd from a syncobj.
This is useful for Wayland compositors to handle wait-before-submit.
Wayland clients can send a timeline point to the compositor
before the point has materialized yet, then compositors can wait
for the point t
On Tue, 11 Oct 2022, Jani Nikula wrote:
> While it takes more vertical space, sorted build lists with one object
> per line are arguably easier to manage, especially when there are
> conflicting changes.
>
> Split anything with more than one object file.
>
> v2: also split drm_cache.o and put it a
On 28/09/2022 20:52, Aradhya Bhatia wrote:
The ctrl mmr module of the AM625 is different from the AM65X SoC. Thus
the ctrl mmr registers that supported the OLDI TX power have become
different in AM625 SoC.
Add IO CTRL support and control the OLDI TX power for AM625.
Signed-off-by: Aradhya Bhati
On 28/09/2022 20:52, Aradhya Bhatia wrote:
The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal.
These can be configured to support the following modes:
1. OLDI_SINGLE_LINK_SINGLE_MODE
Single Output over OLDI 0.
+--++-+ +---+
| ||
On 28/09/2022 20:52, Aradhya Bhatia wrote:
Add support for the DSS controller on TI's new AM625 SoC in the tidss
driver.
The first video port (VP0) in am625-dss can output OLDI signals through
2 OLDI TXes. A 3rd port has been added with "DISPC_VP_OLDI" bus type.
Signed-off-by: Aradhya Bhatia
-
On Wed, Oct 12, 2022 at 10:38:29AM +0200, Arnd Bergmann wrote:
> On Wed, Oct 12, 2022, at 10:27 AM, Thomas Zimmermann wrote:
> > Am 12.10.22 um 09:44 schrieb Arnd Bergmann:
> >> On Wed, Oct 12, 2022, at 9:40 AM, Thomas Zimmermann wrote:
> >>> Am 12.10.22 um 09:17 schrieb Arnd Bergmann:
> On We
Clear interface active register from the datapath for a clean shutdown of
the datapath.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/panel.c | 20 +++
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
---
.../gpu/drm/msm/disp/dpu1/dpu_e
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/bridge/panel.c | 48 ++
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_brid
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++-
Timing gen status can be read reliablly from intf status
register rather than from the timing gen control register,
which will readback as "0" after disable though the timing
gen is still under going disable path. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
---
d
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 +
1 file change
Update crtc retrieval from dpu_enc to dpu_enc connector state,
since new links get set as part of the dpu enc virt mode set.
The dpu_enc->crtc cache is no more needed, hence cleaning it as
part of this change.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ---
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dis
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Chang
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/drm_atomic.c | 60 ++
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Ba
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Tuesday, September 13, 2022 10:36 PM
> To: Vinod Polimera (QUIC) ; dri-
> de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org; ro
https://bugzilla.kernel.org/show_bug.cgi?id=213145
Paul Menzel (pmenzel+bugzilla.kernel@molgen.mpg.de) changed:
What|Removed |Added
CC||
Hi
Am 12.10.22 um 10:38 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 10:27 AM, Thomas Zimmermann wrote:
Am 12.10.22 um 09:44 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 9:40 AM, Thomas Zimmermann wrote:
Am 12.10.22 um 09:17 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 8:46 AM, Thom
On 28/09/2022 20:52, Aradhya Bhatia wrote:
Add support for the DSS controller on TI's new AM625 SoC in the tidss
driver.
The first video port (VP0) in am625-dss can output OLDI signals through
2 OLDI TXes. A 3rd port has been added with "DISPC_VP_OLDI" bus type.
Signed-off-by: Aradhya Bhatia
-
On 28/09/2022 20:52, Aradhya Bhatia wrote:
Add ti,am625-dss compatible string.
The DSS IP on TI's AM625 SoC is an update from the DSS on TI's AM65X
SoC. The former has an additional OLDI TX to enable a 2K resolution on
OLDI displays or enable 2 duplicated displays with a smaller resolution.
Sign
Am 12.10.22 um 12:25 schrieb Simon Ser:
On Tuesday, October 11th, 2022 at 14:10, Christian König
wrote:
Am 10.10.22 um 11:13 schrieb Simon Ser:
On Sunday, October 9th, 2022 at 20:00, Christian König
wrote:
Am 09.10.22 um 16:40 schrieb Simon Ser:
Introduce a new DRM_IOCTL_SYNCOBJ_TIMELI
https://bugzilla.kernel.org/show_bug.cgi?id=213145
--- Comment #25 from James Le Cuirot (ch...@gentoo.org) ---
I do, yes, under Wayland. I did a system update recently but if the problem
reoccurs, I'll try that next. Thanks!
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On 10/10/2022 07:58, Niranjana Vishwanathapura wrote:
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects
On Tuesday, October 11th, 2022 at 14:10, Christian König
wrote:
> Am 10.10.22 um 11:13 schrieb Simon Ser:
> > On Sunday, October 9th, 2022 at 20:00, Christian König
> > wrote:
> >
> >> Am 09.10.22 um 16:40 schrieb Simon Ser:
> >>
> >>> Introduce a new DRM_IOCTL_SYNCOBJ_TIMELINE_REGISTER_EVENTF
On Tue, 11 Oct 2022, Lucas De Marchi wrote:
> Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
> ranges. This should cover most of our needs for _MMIO_PLL3 and such.
> To show what is achieved with the new macro, convert some PLL-related
> macros to use it instead of _MMIO_PLL3.
On Wed, Oct 12, 2022, at 10:27 AM, Thomas Zimmermann wrote:
> Am 12.10.22 um 09:44 schrieb Arnd Bergmann:
>> On Wed, Oct 12, 2022, at 9:40 AM, Thomas Zimmermann wrote:
>>> Am 12.10.22 um 09:17 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 8:46 AM, Thomas Zimmermann wrote:
>>>
Does qemu
Ping?
On Thu, 15 Sep 2022, Jani Nikula wrote:
> Hey all, I'd be interested in having the pr-tracker-bot [1] set up for
> the drm subsystem, following the dri-devel mailing list [2] and
> notifying when the pull requests have been merged to either the drm-next
> or drm-fixes branches of the main
Hi
Am 12.10.22 um 09:44 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 9:40 AM, Thomas Zimmermann wrote:
Am 12.10.22 um 09:17 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 8:46 AM, Thomas Zimmermann wrote:
Does qemu mark the device has having a particular endianess then, or
does it switc
On Tue, 11 Oct 2022, Matthieu CHARETTE wrote:
> Currently the EDID is requested during the resume. But since it's
> requested too early, this means before the filesystem is mounted, the
> firmware request fails. This make the DRM driver crash when resuming.
> This kind of issue should be prevented
Il 11/10/22 20:28, Justin Green ha scritto:
Hi Angelo,
Thanks for the suggestions! I'll upload another patch with those changes.
Re the pitch register math, would it be acceptable to define separate
macros for the LSB and MSB to abstract away the magic numbers? For
example:
#define OVL_PITCH_MSB
On Mon, 2022-09-05 at 21:53 +0800, xinlei@mediatek.com wrote:
> From: Xinlei Lee
>
> Modify dpi power on/off sequence so that the first gpio operation
> will take effect.
>
> Fixes: 6bd4763fd532 ("drm/mediatek: set dpi pin mode to gpio low to
> avoid leakage
> current")
>
> Signed-off-by: X
On Wed, Oct 12, 2022, at 9:40 AM, Thomas Zimmermann wrote:
> Am 12.10.22 um 09:17 schrieb Arnd Bergmann:
>> On Wed, Oct 12, 2022, at 8:46 AM, Thomas Zimmermann wrote:
>
>> Does qemu mark the device has having a particular endianess then, or
>> does it switch the layout of the framebuffer to match w
Hi
Am 12.10.22 um 09:17 schrieb Arnd Bergmann:
On Wed, Oct 12, 2022, at 8:46 AM, Thomas Zimmermann wrote:
Am 11.10.22 um 22:06 schrieb Arnd Bergmann:
On Tue, Oct 11, 2022, at 1:30 PM, Thomas Zimmermann wrote:
Am 11.10.22 um 09:46 schrieb Javier Martinez Canillas:
+static bool display_get_big
After commit 571c05365892 ("drm/amdgpu: switch sdma buffer function
tear down to a helper"), the variable 'ring' is not used anymore, it
can be removed.
Signed-off-by: Yang Yingliang
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/
Am 11.10.22 um 18:51 schrieb Javier Martinez Canillas:
There's no need to add planes to the atomic state. Remove the call
to drm_atomic_add_affected_planes() from mgag200.
On full modesets, the DRM helpers already add a CRTC's planes to the
atomic state; see drm_atomic_helper_check_modeset().
On Wednesday, October 12th, 2022 at 08:18, Christian König
wrote:
> DRM auth based authentication is seen as a security risk and we want to
> get rid of that for render only devices (at least for the new ones).
Right, that makes sense for new hw/drivers. So we really need this to
be opt-in, we
Hi Doug,
I incorporated the comments in v7.
>Hi,
>
>On Mon, Jul 11, 2022 at 5:57 AM Vinod Polimera
> wrote:
>>
>> @@ -359,6 +367,24 @@ void dp_catalog_ctrl_lane_mapping(struct
>dp_catalog *dp_catalog)
>> ln_mapping);
>> }
>>
>> +void dp_catalog_ctrl_psr_mainlink_enable(str
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