> -Original Message-
> From: Greg Kroah-Hartman
> Sent: Friday, September 09, 2022 09:16
> To: Ceraolo Spurio, Daniele
> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> Winkler, Tomas ; Lubart, Vitaly
> ; Teres Alexis, Alan Previn
>
> Subject: Re: [PATCH v4 06/
On Fri, Sep 09, 2022 at 06:38:33AM +, Winkler, Tomas wrote:
> >
> > On Thu, Sep 08, 2022 at 05:16:02PM -0700, Daniele Ceraolo Spurio wrote:
> > > +static ssize_t mei_pxp_gsc_command(struct device *dev, u8 client_id,
> > u32 fence_id,
> > > +struct scatterlist *sg_in
>
> On Thu, Sep 08, 2022 at 05:16:02PM -0700, Daniele Ceraolo Spurio wrote:
> > +static ssize_t mei_pxp_gsc_command(struct device *dev, u8 client_id,
> u32 fence_id,
> > + struct scatterlist *sg_in, size_t
> > total_in_len,
> > + struct sc
> On Thu, Sep 08, 2022 at 05:15:58PM -0700, Daniele Ceraolo Spurio wrote:
> > From: Tomas Winkler
> >
> > GSC extend header is of variable size and data is provided in a sgl
> > list inside the header and not in the data buffers, need to enable the
> > path.
> >
> > V2:
> > 1. Add missing kdoc f
On Fri, Sep 09, 2022 at 06:21:10AM +, Winkler, Tomas wrote:
> > > >
> > > > On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote:
> > > > > --- a/drivers/misc/mei/hw-me.c
> > > > > +++ b/drivers/misc/mei/hw-me.c
> > > > > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struc
> > >
> > > On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote:
> > > > --- a/drivers/misc/mei/hw-me.c
> > > > +++ b/drivers/misc/mei/hw-me.c
> > > > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struct
> > > > mei_device
> > > *dev,
> > > > u32 dw_cnt;
> > > >
Delete the redundant word 'to'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 24b414cff3ec..cd5f8b219bf9 100644
--- a/dri
Delete the redundant word 'in'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index bdd48f87d098..fab71091099
VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12,
not 16-28.
Without this the output tends to have a pink hue, changing it results
in better color accuracy.
The vendor kernel doesn't use this register. However the code which
sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. Th
From: Easwar Hariharan
Move the Microsoft PCI Vendor ID from the various drivers to the pci_ids
file
Signed-off-by: Easwar Hariharan
---
drivers/gpu/drm/hyperv/hyperv_drm_drv.c | 1 -
drivers/net/ethernet/microsoft/mana/gdma_main.c | 4
drivers/video/fbdev/hyperv_fb.c
Delete the redundant word 'to'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/i915/i915_memcpy.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_memcpy.h
b/drivers/gpu/drm/i915/i915_memcpy.h
index 3df063a3293b..126dfb4352f0 100644
--- a/drivers/gpu/
On 9/5/22 14:18, Maxime Ripard wrote:
On Wed, Aug 31, 2022 at 04:42:05PM +0200, Maxime Ripard wrote:
Sorry for the fairly broad list of recipients, I'm not entirely sure
where the issue lies exactly, and it seems like multiple areas are
involved.
Martin reported me an issue discovered with the
Delete the redundant word 'to'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index f085dbd4736d..7677475b5d93 100644
---
From: Easwar Hariharan
Signed-off-by: Easwar Hariharan
---
drivers/gpu/drm/hyperv/hyperv_drm_drv.c | 4 +---
drivers/net/ethernet/microsoft/mana/gdma.h | 3 ---
drivers/net/ethernet/microsoft/mana/gdma_main.c | 6 +++---
drivers/video/fbdev/hyperv_fb.c | 6 ++
i
VIU_OSD1_CTRL_STAT.GLOBAL_ALPHA is a 9 bit field, so the maximum
value is 0x100 not 0xff.
This matches the vendor kernel.
Signed-off-by: Stuart Menefy
---
drivers/gpu/drm/meson/meson_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/meson/meson_plane.c
Delete the redundant word 'in'.
Signed-off-by: wangjianli
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index bdb6bac8dd97..c9
On Thu, Sep 08, 2022 at 05:16:03PM -0700, Daniele Ceraolo Spurio wrote:
> From: Tomas Winkler
>
> With on-boards graphics card, both i915 and MEI
> are in the same device hierarchy with the same parent,
> while for discrete gfx card the MEI is its child device.
> Adjust the match function for tha
On Thu, Sep 08, 2022 at 05:16:02PM -0700, Daniele Ceraolo Spurio wrote:
> +static ssize_t mei_pxp_gsc_command(struct device *dev, u8 client_id, u32
> fence_id,
> +struct scatterlist *sg_in, size_t
> total_in_len,
> +struct scatterlis
On Thu, Sep 08, 2022 at 05:16:00PM -0700, Daniele Ceraolo Spurio wrote:
> From: Tomas Winkler
>
> Fix kdoc for struct mei_ext_hdr and mei_ext_begin().
Shouldn't this go in the function that made the changes in the first
place?
>
> V4: New in the series
Again, below the --- line please.
thank
On Thu, Sep 08, 2022 at 05:15:58PM -0700, Daniele Ceraolo Spurio wrote:
> From: Tomas Winkler
>
> GSC extend header is of variable size and data
> is provided in a sgl list inside the header
> and not in the data buffers, need to enable the path.
>
> V2:
> 1. Add missing kdoc for mei_cl_cb
> 2.
> On DG2, HuC loading is performed by the GSC, via a PXP command. The load
> operation itself is relatively simple (just send a message to the GSC with the
> physical address of the HuC in LMEM), but there are timing changes that
> requires special attention. In particular, to send a PXP command
On Thu, Sep 08, 2022 at 09:24:07PM +, Winkler, Tomas wrote:
>
> >
> > On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote:
> > > --- a/drivers/misc/mei/hw-me.c
> > > +++ b/drivers/misc/mei/hw-me.c
> > > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struct mei_device
> >
https://bugzilla.kernel.org/show_bug.cgi?id=205089
Oscar Parada (oparada1...@gmail.com) changed:
What|Removed |Added
CC||oparada1...@gmail.c
> From: Jason Gunthorpe
> Sent: Thursday, September 8, 2022 8:37 PM
>
> On Thu, Sep 08, 2022 at 11:39:07AM +0200, Eric Auger wrote:
>
> > >> I am not totally clear about remaining 'struct device *dev;' in
> > >> vfio_device struct. I see it used in some places. Is it supposed to
> > >> disappear
With the addition of vfio_put_device() now the names become confusing.
vfio_put_device() is clear from object life cycle p.o.v given kref.
vfio_device_put()/vfio_device_try_get() are helpers for tracking
users on a registered device.
Now rename them:
- vfio_device_put() -> vfio_device_put_regi
From: Yi Liu
and replace kref. With it a 'vfio-dev/vfioX' node is created under the
sysfs path of the parent, indicating the device is bound to a vfio
driver, e.g.:
/sys/devices/pci\:6f/\:6f\:01.0/vfio-dev/vfio0
It is also a preparatory step toward adding cdev for supporting future
devi
ccw is the only exception which cannot use vfio_alloc_device() because
its private device structure is designed to serve both mdev and parent.
Life cycle of the parent is managed by css_driver so vfio_ccw_private
must be allocated/freed in css_driver probe/remove path instead of
conforming to vfio
Implement amba's own vfio_device_ops.
Remove vfio_platform_probe/remove_common() given no user now.
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Eric Auger
---
drivers/vfio/platform/vfio_amba.c | 72 ++-
drivers/vfio/platform/vfio_platform_co
Move vfio_device to the start of intel_vgpu as required by the new
helpers.
Change intel_gvt_create_vgpu() to use intel_vgpu as the first param
as other vgpu helpers do.
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gvt.h | 5 +
Move vfio_device_ops from platform core to platform drivers so device
specific init/cleanup can be added.
Introduce two new helpers vfio_platform_init/release_common() for the
use in driver @init/@release.
vfio_platform_probe/remove_common() will be deprecated.
Signed-off-by: Kevin Tian
Reviewe
From: Yi Liu
Also add a comment to mark that vfio core releases device_set if @init
fails.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
drivers/vfio/fsl-mc/vfio_fsl_mc.c | 85 ++-
1 file changed, 49 insertions(+), 36 deletions(-
From: Yi Liu
and manage mdpy_count inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
samples/vfio-mdev/mdpy.c | 81 +++-
1 file changed, 47 insertions(+), 34 deletions(-)
diff --git a/samples/vfio-mdev
From: Yi Liu
and manage avail_mbytes inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
samples/vfio-mdev/mbochs.c | 73 --
1 file changed, 46 insertions(+), 27 deletions(-)
diff --git a/samples/vfio-md
From: Yi Liu
and manage available_instances inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Tony Krowiak
Reviewed-by: Jason Gunthorpe
---
drivers/s390/crypto/vfio_ap_ops.c | 50 ++-
1 file changed, 29 insertions(+), 21 deletion
From: Yi Liu
mlx5 has its own @init/@release for handling migration cap.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
drivers/vfio/pci/mlx5/main.c | 50 ++--
1 file changed, 36 insertions(+), 14 deletions(-)
diff --git a/dr
From: Yi Liu
and manage available ports inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
samples/vfio-mdev/mtty.c | 67 +++-
1 file changed, 39 insertions(+), 28 deletions(-)
diff --git a/samples/vfio
The idea is to let vfio core manage the vfio_device life cycle instead
of duplicating the logic cross drivers. This is also a preparatory
step for adding struct device into vfio_device.
New pair of helpers together with a kref in vfio_device:
- vfio_alloc_device()
- vfio_put_device()
Drivers c
The idea is to let vfio core manage the vfio_device life cycle instead
of duplicating the logic cross drivers. Besides cleaner code in driver
side this also allows adding struct device to vfio_device as the first
step toward adding cdev uAPI in the future. Another benefit is that
user can now look
From: Yi Liu
Tidy up @probe so all migration specific initialization logic is moved
to migration specific @init callback.
Remove vfio_pci_core_{un}init_device() given no user now.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Shameer Kolothum
---
From: Yi Liu
Also introduce two pci core helpers as @init/@release for pci drivers:
- vfio_pci_core_init_dev()
- vfio_pci_core_release_dev()
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
drivers/vfio/pci/vfio_pci.c | 20 +-
drivers/v
Since qxl_io_reset(qdev) will be called immediately
after qxl_ring_create() been called,
and parameter like notify_on_prod will be set to default value.
So the call to qxl_ring_init_hdr() before becomes meaningless.
Signed-off-by: Zongmin Zhou
Suggested-by: Ming Xie
---
drivers/gpu/drm/qxl/qxl_cm
> From: Eric Farman
> Sent: Friday, September 9, 2022 4:51 AM
>
> On Thu, 2022-09-08 at 07:19 +, Tian, Kevin wrote:
> > ping @Eric Farman.
> >
> > ccw is the only tricky player in this series. Please help take a look
> > in case of
> > any oversight here.
>
> Apologies, I had started looking
On Wed, Sep 07, 2022 at 08:35:13AM -0500, Chris Morgan wrote:
> On Wed, Sep 07, 2022 at 02:53:56PM +0200, Krzysztof Kozlowski wrote:
> > On 06/09/2022 20:52, Chris Morgan wrote:
> > > From: Chris Morgan
> > >
> > > Add documentation for the NewVision NV3051D panel bindings.
> > > Note that for th
On Tue, 06 Sep 2022 12:48:20 -0500, Chris Morgan wrote:
> From: Chris Morgan
>
> Add a compatible string for the rk3568 dsi-dphy.
>
> Signed-off-by: Chris Morgan
> ---
> .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob H
On Tue, 06 Sep 2022 12:48:19 -0500, Chris Morgan wrote:
> From: Chris Morgan
>
> The rk3568 uses the same dw-mipi-dsi controller as previous Rockchip
> SOCs, so add a compatible string for it.
>
> Signed-off-by: Chris Morgan
> ---
> .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
I've submitted a merge request to have those flags turned on by default
in our CI builds:
https://gitlab.freedesktop.org/gfx-ci/i915-infra/-/merge_requests/116
Daniele
On 9/8/2022 5:16 PM, Daniele Ceraolo Spurio wrote:
Both are required for HuC loading.
Signed-off-by: Daniele Ceraolo Spurio
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
2 file
Both are required for HuC loading.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Kconfig.debug | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..a6576ffbc4dc 100644
--- a/drivers/gpu
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
V4:
1. Remove unnecessary include in intel_pxp_huc.h (Jani)
2. Adjust copyright year to 2022
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by:
From: Tomas Winkler
With on-boards graphics card, both i915 and MEI
are in the same device hierarchy with the same parent,
while for discrete gfx card the MEI is its child device.
Adjust the match function for that scenario
by matching MEI parent device with i915.
V2:
1. More detailed commit me
From: Vitaly Lubart
The discrete graphics card with GSC firmware
using command streamer API hence it requires to enhance
pxp module with the new gsc_command() handler.
The handler is implemented via mei_pxp_gsc_command() which is
just a thin wrapper around mei_cldev_send_gsc_command()
V2:
1. M
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
dr
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to b
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a couple of them,
INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
their expected return v
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as follows
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and sync
From: Vitaly Lubart
Add mei bus API for sending gsc commands: mei_cldev_send_gsc_command()
The GSC commands are originated in the graphics stack
and are in form of SGL DMA buffers.
The GSC commands are synchronous, the response is received
in the same call on the out sg list buffers.
The functio
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
V2:
1. Add missing kdoc for mei_cl_cb
2. In mei_me_hbuf_write()
use dev_err() when validationg parameters instead of WARN_ON()
The GSC will perform both the load and the authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele
From: Tomas Winkler
Fix kdoc for struct mei_ext_hdr and mei_ext_begin().
V4: New in the series
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/hw.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/driv
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need to
Please ignore this cover letter, I've only realized I was missing a
title and aborted the git-send after sending it. Proper series coming in
a couple of mins.
Daniele
On 9/8/2022 5:10 PM, Daniele Ceraolo Spurio wrote:
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
op
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need to
On 9/8/2022 3:45 PM, Matt Roper wrote:
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the sta
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the standalone media's
intel_uncore structure, it c
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 47c191411b68a771261be3dc0bd6f68394cef358 Add linux-next specific
files for 20220908
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209042337.fqi69rlv-...@intel.com
https
On Thu, Sep 08, 2022 at 02:16:27PM -0700, Ceraolo Spurio, Daniele wrote:
>
>
> On 9/6/2022 4:49 PM, Matt Roper wrote:
> > GT non-engine registers (referred to as "GSI" registers by the spec)
> > have the same relative offsets on standalone media as they do on the
> > primary GT, just with an addi
On Fri, 9 Sept 2022 at 00:18, Kuogee Hsieh wrote:
>
> Bring sink out of D3 (power down) mode into D0 (normal operation) mode
> by setting DP_SET_POWER_D0 bit to DP_SET_POWER dpcd register. This
> patch will retry 3 times if written to DP_SET_POWER register failed.
>
> Changes in v4:
> -- split int
>
> On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote:
> > --- a/drivers/misc/mei/hw-me.c
> > +++ b/drivers/misc/mei/hw-me.c
> > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struct mei_device
> *dev,
> > u32 dw_cnt;
> > int empty_slots;
> >
> > - if (WARN_ON(!
On 9/6/2022 4:49 PM, Matt Roper wrote:
When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow. As
such, we should share the same IRQ lock with the primary GT. Let's
convert gt->irq_lock into a pointer and jus
Bring sink out of D3 (power down) mode into D0 (normal operation) mode
by setting DP_SET_POWER_D0 bit to DP_SET_POWER dpcd register. This
patch will retry 3 times if written to DP_SET_POWER register failed.
Changes in v4:
-- split into two patches
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm
DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
upstream device disconnect. This patch will enforce this rule by always
cleared DOWNSPREAD_CTRL register to 0 before start link training. At rare
case that DP MSA timing parameters may be mis-interpreted by the sink
which cause
cleared DP_DOWNSPREAD_CTRL register before start link training
Kuogee Hsieh (2):
drm/msm/dp: cleared DP_DOWNSPREAD_CTRL register before start link
training
drm/msm/dp: retry 3 times if set sink to D0 poweer state failed
drivers/gpu/drm/msm/dp/dp_ctrl.c | 13 +
drivers/gpu/drm
On 9/6/2022 4:49 PM, Matt Roper wrote:
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the sta
On 9/6/2022 4:49 PM, Matt Roper wrote:
In preparation for enabling a second GT, there are a number of GT/uncore
operations that happen during initialization or suspend flows that need
to be performed on each GT, not just the primary,
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Re
On 9/6/2022 4:49 PM, Matt Roper wrote:
In a multi-GT system we need to initialize MMIO access for each GT, not
just the primary GT.
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 27 +
On Thu, 2022-09-08 at 07:19 +, Tian, Kevin wrote:
> ping @Eric Farman.
>
> ccw is the only tricky player in this series. Please help take a look
> in case of
> any oversight here.
Apologies, I had started looking at v1 before I left on holiday, and
only returned today.
>
> > From: Tian, Kev
tree: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
head: 5d832b6694e094b176627ed9918a1b21c56fb742
commit: ec491291dc94914cf962dcd399c3e9b43b00a770 [1/1] drm/sun4i: tv: Merge
mode_set into atomic_enable
config: parisc-randconfig-r003-20220907
(https://download.01.org/0day-ci/archiv
On Thu, Sep 01, 2022 at 11:03:41PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> In Display version 14, Transcoder Chicken Registers have updated address.
> This patch performs checks to use the right register when required.
>
> v2: Omit display version check
On 08/09/2022 22:37, Rob Herring wrote:
On Thu, Sep 08, 2022 at 03:37:38PM +0200, Krzysztof Kozlowski wrote:
On 01/09/2022 12:23, Dmitry Baryshkov wrote:
Split Mobile Display SubSystem (MDSS) root node bindings to the separate
yaml file. Changes to the existing (txt) schema:
- Added optional
Instead of calling read_clock_frequency() to walk the if/else ladder
per platform, move the ladder to intel_gt_init_clock_frequency() and
use one function per branch.
With the new logic, it's now clear the call to
gen9_get_crystal_clock_freq() was just dead code, as gen9 is handled by
another func
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_g
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch tak
deletions(-)
---
base-commit: adc57f2b82896fed07bc8e34956c15bb1448fca2
change-id: 20220908-if-ladder-df33a06d4f4e
Best regards,
--
Lucas De Marchi
Dne torek, 06. september 2022 ob 17:30:29 CEST je Clément Péron napisal(a):
> Hi,
>
> This is a refresh of previous patches sent to enable GPU Devfreq on H6
> Beelink GS1 but that wasn't stable at that time[0].
>
> With the recent fix on GPU PLL from Roman Stratiienko I have retested
> and everyt
On Thu, Sep 01, 2022 at 11:03:40PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms have different credits values
> compared to ADL-P. Update the credits based on pipe usage.
>
> v2: Simplify DBOX BW Credit definition(MattR)
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc:
On Thu, Sep 08, 2022 at 03:37:38PM +0200, Krzysztof Kozlowski wrote:
> On 01/09/2022 12:23, Dmitry Baryshkov wrote:
> > Split Mobile Display SubSystem (MDSS) root node bindings to the separate
> > yaml file. Changes to the existing (txt) schema:
> > - Added optional "vbif_nrt_phys" region used by
Hi Dmitry
On 9/8/2022 7:46 AM, Dmitry Baryshkov wrote:
On 30/08/2022 06:33, Abhinav Kumar wrote:
DSI interface used with a bridge chip connected to an external
display is subject to the same pixel clock limits as one
which is natively pluggable like DisplayPort.
Hence filter out DSI modes havi
On 9/7/2022 6:12 PM, Stephen Boyd wrote:
Quoting Abhinav Kumar (2022-08-29 20:33:09)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index bfd0aeff3f0d..8b91d8adf921 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_displa
Hi Stephen
On 9/7/2022 6:06 PM, Stephen Boyd wrote:
Quoting Abhinav Kumar (2022-08-29 20:33:08)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 39bbabb5daf6..3a06a157d1b1 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -265,6 +2
will merge Rusticl tomorrow or so unless somebody complains.
On Wed, Aug 24, 2022 at 5:34 PM Karol Herbst wrote:
>
> On Wed, Aug 24, 2022 at 5:18 PM Jason Ekstrand
> wrote:
> >
> > +mesa-dev and my jlekstrand.net e-mail
> >
> > On Sun, 2022-08-21 at 20:44 +0200, Karol Herbst wrote:
> > > On Sun,
iput() has already handled null and non-null parameter, so it is no
need to use if().
Signed-off-by: Jingyu Wang
---
drivers/gpu/drm/drm_drv.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 8214a0b1ab7f..beec4
On 2022-09-08 14:10, Lucas Stach wrote:
Track the accumulated time that jobs from this entity were active
on the GPU. This allows drivers using the scheduler to trivially
implement the DRM fdinfo when the hardware doesn't provide more
specific information than signalling job completion anyways.
Please send everything together because otherwise it's not clear why we
need this.
Andrey
On 2022-09-08 11:09, James Zhu wrote:
Yes, it is for NPI design. I will send out patches for review soon.
Thanks!
James
On 2022-09-08 11:05 a.m., Andrey Grodzovsky wrote:
So this is the real need of th
On 2022-09-08 09:17, wangjianli wrote:
Delete the redundant word 'to'.
Signed-off-by: wangjianli
Reviewed-by: Felix Kuehling
I'll apply this to amd-staging-drm-next.
Thanks,
Felix
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 2022-09-08 12:35, Alex Deucher wrote:
On Thu, Sep 8, 2022 at 12:29 PM Felix Kuehling wrote:
On 2022-09-08 11:52, Alex Deucher wrote:
Hi Dave, Daniel,
New stuff for 6.1.
The following changes since commit 085292c3d78015412b752ee1ca4c7725fd2bf2fc:
Revert "drm/amd/amdgpu: add pipe1 hard
On Thu, Sep 01, 2022 at 11:03:38PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
> changed wrt. previous platforms, adjust the code accordingly.
>
> Signed-off-by: Imre Deak
> Signed-off-by: Radhakrishna Sripada
As no
On Thu, Sep 08, 2022 at 11:07:16AM -0700, Matt Roper wrote:
> On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak
> >
> > Add support for display power wells on MTL. The differences from XE_LPD:
> > - The AUX HW block is moved to the PICA block, where the reg
Allows to easily track if several fd are pointing to the same
execution context due to being dup'ed.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 3 +++
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/e
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