On Tue, 21 Jun 2022 at 03:50, Jessica Zhang wrote:
>
> Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
> helper method. This way, we can make it easier to get CRCs from other HW
> blocks by adding other get_crc helper methods.
>
> Changes since V1:
> - Move common bitmasks
On Tue, 21 Jun 2022 at 03:50, Jessica Zhang wrote:
>
> Move layer mixer specific MISR methods to generalized helper methods.
> This will make it easier to add CRC support for other blocks in the
> future.
>
> Changes since V2:
> - Reordered parameters so that offsets are after hw_blk_reg_map
> - F
On Tue, 21 Jun 2022 at 03:50, Jessica Zhang wrote:
>
> Add support for writing CRC values for the interface block to
> the debugfs by calling the necessary MISR setup/collect methods.
>
> Changes since V1:
> - Set values_cnt to only include phys with backing hw_intf
> - Loop over all drm_encs conn
Hi Stephen,
Thank you for the patch.
On Thu, Jun 16, 2022 at 07:08:21PM +0200, Stephen Kitt wrote:
> This started with work on the removal of backlight_properties'
> deprecated fb_blank field, much of which can be taken care of by using
> helper functions provided by backlight.h instead of direct
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, June 16, 2022 7:58 PM
> To: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy
>
> On Thu, 16 Jun 20
Hi "Adrián,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on linus/master v5.19-rc2 next-20220617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--ba
On 20-06-22, 13:43, Kuogee Hsieh wrote:
>
> On 6/20/2022 1:07 PM, Kuogee Hsieh wrote:
> >
> > On 6/16/2022 5:02 PM, Vinod Koul wrote:
> > > On 25-05-22, 14:02, Kuogee Hsieh wrote:
> > > > 1) add regulator_set_load() to eDP phy
> > > > 2) add regulator_set_load() to DP phy
> > > > 3) remove vdda r
documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Cai-Huoqing/drm-Make-drm_buddy-a-part-of-drm-module/20220621-095417
base: git://anongit.freedesktop.org/drm/drm drm-next
config: microblaze-buildonly-randconfig-r003-20220620
(https:
Hi Cai,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on linus/master v5.19-rc2 next-20220617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented
Hi "Adrián,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on linus/master v5.19-rc2 next-20220617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as d
On 6/20/22 1:13 PM, Jernej Skrabec wrote:
> Kernel occasionally complains that there is mismatch in segment size
> when trying to render HW decoded videos and rendering them directly with
> sun4i DRM driver. Following message can be observed on H6 SoC:
>
> [ 184.298308] [ cut here ]--
Hi Jonathan,
Thanks for your reply!
Jonathan Cameron 於 2022年6月21日 週二 凌晨2:35寫道：
>
> On Mon, 20 Jun 2022 14:00:43 +0800
> ChiaEn Wu wrote:
>
> > Hi Jonathan,
> >
> > Thanks for your helpful comments, and I have some questions want to
> > ask you below.
> >
> > Jonathan Cameron 於 2022年6月18日 週六 晚
mits that dropped includes from
drm-ctrc.h.
I have used the drm-misc tree from next-20220620 for today.
--
Cheers,
Stephen Rothwell
pgphDF419MeEb.pgp
Description: OpenPGP digital signature
In the event of a job timeout, debug dump information will be written into
/sys/class/devcoredump.
Inspired by etnaviv's similar feature.
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panfrost/Kconfig | 1 +
drivers/gpu/drm/panfrost/Makefile| 3 +-
drivers/gpu/drm/panfro
This is v2 for a previous patch series being discussed at
https://lore.kernel.org/dri-devel/20220517174216.381287-1-adrian.laru...@collabora.com/.
Mesa MR under review can be found at:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14034
Changes with respect to v1 of the same patch:
Hi Steven,
Thanks a lot for your feedback, it was quite useful.
Also I'm sorry about having taken so long to write a reply, but other things
held me
back from working on Panfrost for way too long already.
On 18.05.2022 12:03, Steven Price wrote:
>On 17/05/2022 18:42, Adrián Larumbe wrote:
>> In
The drm_buddy is just a software allocator, so don't need to create
a module for this small part.
If drm_buddy is included in drm module, then only need to insmod drm.ko
Signed-off-by: Cai Huoqing
---
drivers/gpu/drm/Kconfig | 2 +-
drivers/gpu/drm/Makefile| 1 +
drivers/gpu/drm/drm_bu
Add support for setting MISR registers within the interface
Changes since V1:
- Replaced dpu_hw_intf collect_misr and setup_misr implementations with
calls to dpu_hw_utils helper methods
Signed-off-by: Jessica Zhang
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Changes since V1:
- Set values_cnt to only include phys with backing hw_intf
- Loop over all drm_encs connected to crtc
Changes since V2:
- Remove vblank.h inclusion
- Ch
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Changes since V1:
- Move common bitmasks to dpu_hw_util.h
- Move common CRC methods to dpu_hw_util.c
- Upd
Move layer mixer specific MISR methods to generalized helper methods.
This will make it easier to add CRC support for other blocks in the
future.
Changes since V2:
- Reordered parameters so that offsets are after hw_blk_reg_map
- Fixed mismatched whitespace in bitmask definitions
Signed-off-by: J
Refactor existing CRC code for layer mixer and add CRC support for interface
blocks
Changes since V1:
- Create helper methods for collect_misr and setup_misr in dpu_hw_util.c
- Move common bitmasks into dpu_hw_util.h
- Update copyrights
- Create a dynamically allocated crcs array in dpu_crtc_stat
On 6/1/2022 9:13 AM, Dmitry Baryshkov wrote:
There is little point in having a separate header just for a single
opaque struct definition. Drop it now and move the struct to the
dpu_hw_util.h header.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp
Hello Alex,
On 6/16/22 22:38, Alex Williamson wrote:
> Console drivers can create conflicts with PCI resources resulting in
> userspace getting mmap failures to memory BARs. This is especially
> evident when trying to re-use the system primary console for userspace
> drivers. Use the aperture he
On 6/1/2022 9:13 AM, Dmitry Baryshkov wrote:
There is little point in keeping a separate MDP address and block offset
in this struct. Merge them to form a new blk_addr field used for all
register access.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/
On 6/16/22 22:38, Alex Williamson wrote:
> From: Thomas Zimmermann
>
> Implement DRM's aperture helpers under video/ for sharing with other
> sub-systems. Remove DRM-isms from the interface. The helpers track
> the ownership of framebuffer apertures and provide hand-over from
> firmware, such as
On 6/1/2022 9:13 AM, Dmitry Baryshkov wrote:
We (nearly) do not use the length field from struct dpu_hw_blk_reg_map,
so we can drop it safely.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 1 -
drivers/gpu/drm/msm/disp/
On 6/1/2022 9:13 AM, Dmitry Baryshkov wrote:
Drop the unused field xin_id.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
b/driv
Applied the series. Thanks,
Alex
On Mon, Jun 20, 2022 at 5:44 AM Hans de Goede wrote:
>
> The DRM_RADEON Kconfig code contains:
>
> select BACKLIGHT_CLASS_DEVICE
>
> So the condition these ifdefs test for is always true, drop them.
>
> Signed-off-by: Hans de Goede
> ---
> drivers/gpu/
I sent out the same patch last week. I just pushed it to drm-misc-next.
Thanks!
Alex
On Sat, Jun 18, 2022 at 1:38 AM Simon Ser wrote:
>
> Reviewed-by: Simon Ser
Align refcount behaviour for amdgpu_job embedded HW fence with
classic pointer style HW fences by increasing refcount each
time emit is called so amdgpu code doesn't need to make workarounds
using amdgpu_job.job_run_counter to keep the HW fence refcount balanced.
Also since in the previous patch w
Problem:
After we start handling timed out jobs we assume there fences won't be
signaled but we cannot be sure and sometimes they fire late. We need
to prevent concurrent accesses to fence array from
amdgpu_fence_driver_clear_job_fences during GPU reset and amdgpu_fence_process
from a late EOP inte
Problem:
This patch caused negative refcount as described in [1] because
for that case parent fence did not signal by the time of drm_sched_stop and
hence
kept in pending list the assumption was they will not signal and
so fence was put to account for the s_fence->parent refcount but for
amdgpu wh
This function should drop the fence refcount when it extracts the
fence from the fence array, just as it's done in amdgpu_fence_process.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/g
Problem:
In amdgpu_job_submit_direct - The refcount should drop by 2
but it drops only by 1.
amdgpu_ib_sched->emit -> refcount 1 from first fence init
dma_fence_get -> refcount 2
dme_fence_put -> refcount 1
Fix:
Add put for external_hw_fence in amdgpu_job_free/free_cb
Signed-off-by: Andrey Grodz
Yiqing raised a problem of negative fence refcount for resubmitted jobs
in amdgpu and suggested a workaround in [1]. I took a look myself and
discovered
some deeper problems both in amdgpu and scheduler code.
Yiqing helped with testing the new code and also drew a detailed refcount and
flow
tra
Maybe someone more familiar with the generic drm fbdev helpers can
help me understand why they don't work with hibernation, at least with
AMD GPUs. We converted amdgpu to use the generic helpers instead of
rolling our own in this patch[1], but it seems to have broken
hibernation[2]. amdgpu has al
On Sat, Jun 18, 2022 at 7:27 PM Guenter Roeck wrote:
>
> ppc:allmodconfig builds fail with the following error.
>
> powerpc64-linux-ld:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
> uses hard float,
> drivers/gpu/drm/amd/amdgpu/../display/dc/dc
refactor stolen memory region to use ttm.
this necessitates using ttm resources to track reserved stolen regions
instead of drm_mm_nodes.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/display/intel_fbc.c | 78 ++--
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 -
drivers/gpu
prepare for ttm based stolen region by using ttm range manager
as the resource manager for stolen region.
Signed-off-by: Robert Beckett
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 6 ++--
drivers/gpu/drm/i915/intel_region_ttm.c | 31 +++
ttm managed buffers start off with system resource definitions and ttm_tt
tracking structures allocated (though unpopulated).
currently this prevents clearing of buffers on first move to desired
placements.
The desired behaviour is to clear user allocated buffers and any kernel
buffers that specif
For situations where allocations need to fail on alloc instead of
delayed get_pages, add a new alloc flag to pin the ttm bo.
This makes sure that the resource has been allocated during buffer
creation, allowing it to fail with an error if the placement is
exhausted.
This allows existing fallback op
During testing make can_mmap consider whether the region is private.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftest
add callbacks for alloc and free.
this allows region creators to allocate any extra storage they may
require.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/intel_memory_region.c | 16 +---
drivers/gpu/drm/i915/intel_memory_region.h | 2 ++
2 files changed, 15 insertions(+),
Stolen regions are not page backed or considered iomem.
Prevent flags indicating such.
This correctly prevents stolen buffers from attempting to directly map
them.
See i915_gem_object_has_struct_page() and i915_gem_object_has_iomem()
usage for where it would break otherwise.
Signed-off-by: Robert
i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c
b/drivers/gpu/drm/i915
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.
Signed-of
Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.
TTM movement code came along and decided that it could make that
decision at that time, which is usually well after
This series refactors i915's stolen memory region to use ttm.
v2: handle disabled stolen similar to legacy version.
relying on ttm to fail allocs works fine, but is dmesg noisy and causes
testing
dmesg warning regressions.
v3: rebase to latest drm-tip.
fix v2 code
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback. While we are at it, replace irq_of_parse_and_map() with
platform_get_irq().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_k
To let the probe function bail early if any of the resources is
unavailable, move resource allocattion from kms_init directly to the
probe callback.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 97 +++-
1 file changed, 45 insertions(+), 52 de
The rest of the code expects that master's device drvdata is the
struct msm_drm_private instance. Do not override the mdp5's drvdata.
Fixes: 6874f48bb8b0 ("drm/msm: make mdp5/dpu devices master components")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 19 +++
As discussed several times on IRC, move display subdriver resource
allocation from kms_init to probe time to let it bail early.
The first patch fixes an issue with drvdata and is probably a -fixes
material, but it is still included as a base for the rest of mdp5
changes.
Dmitry Baryshkov (4):
d
On 6/20/2022 1:07 PM, Kuogee Hsieh wrote:
On 6/16/2022 5:02 PM, Vinod Koul wrote:
On 25-05-22, 14:02, Kuogee Hsieh wrote:
1) add regulator_set_load() to eDP phy
2) add regulator_set_load() to DP phy
3) remove vdda related function out of eDP/DP controller
Kuogee Hsieh (3):
phy: qcom-edp:
On 20/06/2022 23:22, Kuogee Hsieh wrote:
On 6/20/2022 1:15 PM, Dmitry Baryshkov wrote:
On 20/06/2022 23:12, Kuogee Hsieh wrote:
This patch add regulator_set_load() before enable regulator at
DP phy driver.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
On 6/20/2022 1:15 PM, Dmitry Baryshkov wrote:
On 20/06/2022 23:12, Kuogee Hsieh wrote:
This patch add regulator_set_load() before enable regulator at
DP phy driver.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
drivers/phy/qualcomm/phy-qcom-qmp.c
On 20/06/2022 23:12, Kuogee Hsieh wrote:
This patch add regulator_set_load() before enable regulator at
DP phy driver.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 40 -
Thi
On 20/06/2022 23:12, Kuogee Hsieh wrote:
This patch add regulator_set_load() before enable regulator at
eDP phy driver.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Douglas Anderson
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Vdda regulators are related to both eDP and DP phy so that it should be
managed at eDP and DP phy driver instead of controller. This patch removes
vdda regulators related functions out of eDP/DP controller.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Reviewed-by: Dmitry Baryshkov
Revi
This patch add regulator_set_load() before enable regulator at
DP phy driver.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 40 -
1 file changed, 31 insertions(+), 9 deletions(-)
This patch add regulator_set_load() before enable regulator at
eDP phy driver.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Douglas Anderson
---
drivers/phy/qualcomm/phy-qcom-edp.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c
b/drivers/phy/q
0) rebase on https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
tree
1) add regulator_set_load() to eDP phy
2) add regulator_set_load() to DP phy
3) remove vdda related function out of eDP/DP controller
Kuogee Hsieh (3):
phy: qcom-edp: add regulator_set_load to edp phy
phy: qco
On Tue, 14 Jun 2022 at 11:58, Alexander Stein
wrote:
>
> Add more warning/debug messages during probe. E.g. a single -EPROBE_DEFER
> might have several causes, these messages help finding the origin.
>
> Signed-off-by: Alexander Stein
> ---
> * New in v2
>
> drivers/gpu/drm/bridge/ti-sn65dsi83.c
On 6/16/2022 5:02 PM, Vinod Koul wrote:
On 25-05-22, 14:02, Kuogee Hsieh wrote:
1) add regulator_set_load() to eDP phy
2) add regulator_set_load() to DP phy
3) remove vdda related function out of eDP/DP controller
Kuogee Hsieh (3):
phy: qcom-edp: add regulator_set_load to edp phy
phy: q
On Thu, 16 Jun 2022 at 00:25, Jiri Vanek wrote:
>
> This patchset fixes two bugs in the driver for TC358775 DSI to LVDS bridge.
>
> Jiri Vanek (2):
> drm/bridge/tc358775: Return before displaying inappropriate error
> message
> drm/bridge/tc358775: Fix DSI clock division for vsync delay
>
On Thu, 5 May 2022 17:47:01 +0200, Krzysztof Kozlowski wrote:
> On PM660L, PMI8994 and PMI8998, the WLED has two address spaces. This
> also fixes dtbs_check warnings like:
>
> arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dtb: leds@d800: reg:
> [[55296], [2]] is too long
>
>
Applied, t
On Thu, 16 Jun 2022 at 13:18, Sakari Ailus wrote:
>
> On Sat, Jun 11, 2022 at 10:14:07PM +0800, Liu Ying wrote:
> > Patch 1/14 and 2/14 add bus formats used by pixel combiner.
>
> Thanks!
>
> For these:
>
> Acked-by: Sakari Ailus
Applied to drm-misc-next.
On Fri, 17 Jun 2022 at 12:32, Chen-Yu Tsai wrote:
>
> Hi,
>
> On Mon, May 23, 2022 at 4:37 PM Robert Foss wrote:
> >
> > On Mon, 23 May 2022 at 09:18, Chen-Yu Tsai wrote:
> > >
> > > On Mon, May 23, 2022 at 11:13 AM Xin Ji wrote:
> > > >
> > > > On Sat, May 21, 2022 at 06:28:42PM +0200, Daniel
Hi
Am 20.06.22 um 16:45 schrieb Thomas Zimmermann:
Hi
Am 20.06.22 um 16:39 schrieb Maxime Ripard:
On Mon, Jun 20, 2022 at 04:25:38PM +0200, Thomas Zimmermann wrote:
Hi
Am 20.06.22 um 15:48 schrieb Maxime Ripard:
Hi,
On Mon, Jun 20, 2022 at 12:44:24PM +0200, Thomas Zimmermann wrote:
Am 10.
This is an SMMU for the adreno gpu, and adding this compatible lets
the driver use per-fd page tables, which are required for security
between GPU clients.
Signed-off-by: Emma Anholt
Reviewed-by: Dmitry Baryshkov
---
v2: moved qcom,adreno-smmu earlier
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2
Required for turning on per-process page tables for the GPU.
Signed-off-by: Emma Anholt
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/driv
This enable per-process page tables on the Qualcomm RB5 boards I'm
setting up for Mesa CI. Has survived a full deqp-vk run.
v2: moved qcom,adreno-smmu compatible earlier
Emma Anholt (2):
iommu: arm-smmu-impl: Add 8250 display compatible to the client list.
arm64: dts: qcom: sm8250: Enable pe
On Mon, 20 Jun 2022 14:00:43 +0800
ChiaEn Wu wrote:
> Hi Jonathan,
>
> Thanks for your helpful comments, and I have some questions want to
> ask you below.
>
> Jonathan Cameron 於 2022年6月18日 週六 晚上11:39寫道：
> >
> > On Mon, 13 Jun 2022 19:11:38 +0800
> > ChiaEn Wu wrote:
> >
> > > From: ChiaEn
On 6/2/22 12:50, Hans de Goede wrote:
> Hi,
>
> On 6/2/22 11:42, Yihao Han wrote:
>> clk_put() already checks the clk ptr using !clk and IS_ERR()
>> so there is no need to check it again before calling it.
>>
>> Signed-off-by: Yihao Han
>> ---
>> drivers/video/fbdev/simplefb.c | 3 +--
>> 1 file
On 6/8/22 13:43, Yihao Han wrote:
> clk_disable() already checks the clk ptr using IS_ERR_OR_NULL(clk)
> and clk_enable() checks the clk ptr using !clk, so there is no
> need to check clk ptr again before calling them.
>
> Signed-off-by: Yihao Han
applied to fbdev tree.
Thanks!
Helge
> ---
> d
On 6/11/22 18:50, Christophe Leroy wrote:
> A lot of drivers were getting platform and of headers
> indirectly via headers like asm/pci.h or asm/prom.h
>
> Most of them were fixed during 5.19 cycle but a newissue was
> introduced by commit 52b1b46c39ae ("of: Create platform devices
> for OF framebu
Kernel occasionally complains that there is mismatch in segment size
when trying to render HW decoded videos and rendering them directly with
sun4i DRM driver. Following message can be observed on H6 SoC:
[ 184.298308] [ cut here ]
[ 184.298326] DMA-API: sun4i-drm display
Hi Dave,
Here are fixes for v5.19, summary below (and in tag msg)
The following changes since commit 24df12013853ac59c52cc726e9cbe51e38d09eda:
MAINTAINERS: Add Dmitry as MSM DRM driver co-maintainer (2022-05-07
12:02:29 -0700)
are available in the Git repository at:
https://gitlab.freedesk
On Mon, Jun 20, 2022 at 11:43:10AM +0100, Tvrtko Ursulin wrote:
Hi,
On 17/06/2022 06:14, Niranjana Vishwanathapura wrote:
VM_BIND design document with description of intended use cases.
v2: Reduce the scope to simple Mesa use case.
since I expressed interest please add me to cc when sending
On Mon, 20 Jun 2022, "Jason A. Donenfeld" wrote:
> Hi Jani,
>
> On Mon, Jun 20, 2022 at 07:10:30PM +0300, Jani Nikula wrote:
>> On Mon, 20 Jun 2022, "Jason A. Donenfeld" wrote:
>> > Hi Jani,
>> >
>> > Do you plan to merge this revert?
>>
>> Yes, I've done that now, thanks for the bisection and t
Hi Jani,
On Mon, Jun 20, 2022 at 07:10:30PM +0300, Jani Nikula wrote:
> On Mon, 20 Jun 2022, "Jason A. Donenfeld" wrote:
> > Hi Jani,
> >
> > Do you plan to merge this revert?
>
> Yes, I've done that now, thanks for the bisection and the patch.
Thanks!
I see that this went into `drm-intel-next
On Mon, 20 Jun 2022, "Jason A. Donenfeld" wrote:
> Hi Jani,
>
> Do you plan to merge this revert?
Yes, I've done that now, thanks for the bisection and the patch.
Ankit, Imre, we need to figure out what to do with [1] now.
BR,
Jani.
[1] https://gitlab.freedesktop.org/drm/intel/-/issues/5272
Explain how to run the KUnit tests present in the DRM subsystem and
clarify why the UML-only options were not added to the configuration
file present in drivers/gpu/drm/.kunitconfig [1] [2].
[1]
https://lore.kernel.org/dri-devel/CABVgOSn8i=lo5p7830h2xu1jgg0krn0qtnxkomhf1otgxja...@mail.gmail.com/
Test the conversion from XRGB to RGB332.
What is tested?
- Different values for the X in XRGB to make sure it is ignored
- Different clip values: Single pixel and full and partial buffer
- Well known colors: White, black, red, green, blue, magenta, yellow
and cyan
- Other colors: R
Add a helper macro to initialize a rectangle from x, y, width and
height information.
Reviewed-by: Jani Nikula
Acked-by: Thomas Zimmermann
Signed-off-by: José Expósito
---
include/drm/drm_rect.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/drm/drm_rect.h b/incl
Hello everyone,
Following the style used in the selftest to KUnit series [1] and the AMD
series [2], the tests were moved to the "tests" folder.
In addition, to be consistent naming functions, I renamed the
kunit_suite and the test cases to use underscores as suggested in [3].
It is not clear yet
On 20.06.2022 14:36, Thomas Hellström wrote:
In vma destruction, the following race may occur:
Thread 1: Thread 2:
i915_vma_destroy();
...
list_del_init(vma->vm_link);
...
mutex_unlock(vma->vm->mutex);
__i915_vm_release();
re
On Mon, Jun 20, 2022 at 07:42:25AM -0700, Zeng, Oak wrote:
Thanks,
Oak
-Original Message-
From: Vishwanathapura, Niranjana
Sent: June 17, 2022 1:15 AM
To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vetter,
Daniel
Cc: Hellstrom, Thomas ; Wilson, Chris P
; ja...
On Sun, Jun 19, 2022 at 11:32:07PM -0700, Christoph Hellwig wrote:
> > This helps because we now block io memory from ever getting into these
> > call paths. I'm pretty sure this is a serious security bug, but would
> > let the IBM folks remark as I don't know it all that well..
>
> Prevent as in
()
On Thu, May 26, 2022 at 4:55 PM Dmitry Osipenko
wrote:
>
> Introduce a common DRM SHMEM shrinker framework that allows to reduce
> code duplication among DRM drivers by replacing theirs custom shrinker
> implementations with the generic shrinker.
>
> In order to start using DRM SHMEM shrinker
On Sun, Jun 19, 2022 at 11:37:47PM -0700, Christoph Hellwig wrote:
> On Sun, Jun 19, 2022 at 10:51:47PM -0700, Christoph Hellwig wrote:
> > On Mon, Jun 20, 2022 at 12:00:46AM -0300, Jason Gunthorpe wrote:
> > > On Fri, Jun 17, 2022 at 01:54:05AM -0700, Christoph Hellwig wrote:
> > > > There is a bu
On 6/17/2022 3:50 PM, Dmitry Baryshkov wrote:
On 17/06/2022 23:47, Stephen Boyd wrote:
Let's move these functions around to avoid having to forward declare
dp_ctrl_on_stream_phy_test_report(). Also remove
dp_ctrl_reinitialize_mainlink() forward declaration because we're doing
that sort of task
On 6/17/2022 1:47 PM, Stephen Boyd wrote:
This API isn't really more than a couple lines now that we don't store
the pixel_rate to the struct member. Inline it into the caller.
Cc: Kuogee Hsieh
Signed-off-by: Stephen Boyd
Reviewed-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c |
On Mon, Jun 20, 2022 at 7:09 AM Dmitry Osipenko
wrote:
>
> On 6/19/22 20:53, Rob Clark wrote:
> ...
> >> +static unsigned long
> >> +drm_gem_shmem_shrinker_count_objects(struct shrinker *shrinker,
> >> +struct shrink_control *sc)
> >> +{
> >> + struct drm_
Hi
Am 20.06.22 um 16:39 schrieb Maxime Ripard:
On Mon, Jun 20, 2022 at 04:25:38PM +0200, Thomas Zimmermann wrote:
Hi
Am 20.06.22 um 15:48 schrieb Maxime Ripard:
Hi,
On Mon, Jun 20, 2022 at 12:44:24PM +0200, Thomas Zimmermann wrote:
Am 10.06.22 um 11:28 schrieb Maxime Ripard:
The DRM-manage
Hi
Am 20.06.22 um 16:40 schrieb Maxime Ripard:
On Mon, Jun 20, 2022 at 04:19:43PM +0200, Thomas Zimmermann wrote:
Hi
Am 20.06.22 um 14:18 schrieb Maxime Ripard:
+ * At driver unload time the driver's &drm_connector_funcs.destroy hook
+ * should call drm_connector_unregister(), drm_connector_c
Thanks,
Oak
> -Original Message-
> From: Vishwanathapura, Niranjana
> Sent: June 17, 2022 1:15 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vetter,
> Daniel
> Cc: Hellstrom, Thomas ; Wilson, Chris P
> ; ja...@jlekstrand.net;
> christian.koe...@amd.com; Bro
On Mon, Jun 20, 2022 at 04:19:43PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 20.06.22 um 14:18 schrieb Maxime Ripard:
> > + * At driver unload time the driver's &drm_connector_funcs.destroy hook
> > + * should call drm_connector_unregister(), drm_connector_cleanup() and
> > + * kfree() the conne
On Mon, Jun 20, 2022 at 04:25:38PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 20.06.22 um 15:48 schrieb Maxime Ripard:
> > Hi,
> >
> > On Mon, Jun 20, 2022 at 12:44:24PM +0200, Thomas Zimmermann wrote:
> > > Am 10.06.22 um 11:28 schrieb Maxime Ripard:
> > > > The DRM-managed function to register
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