On Fri, May 27, 2022 at 4:41 PM Sudip Mukherjee
wrote:
>
> I just tested with various values, sizeof(*edid) is 144 bytes at that place.
Hmm. What compiler do you have? Because it seems very broken.
You don't actually have to try with various sizes, you could have just
done something like
int s
On Fri, May 27, 2022 at 7:56 PM Linus Torvalds
wrote:
>
> On Fri, May 27, 2022 at 2:07 AM Sudip Mukherjee
> wrote:
> >
> > declared with attribute error: BUILD_BUG_ON failed: sizeof(*edid)
> > != EDID_LENGTH
> >
> > And, reverting it on top of mainline branch has fixed the build failure.
On 5/27/2022 12:46 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
During display resolution changes display have to be disabled first
followed by display enabling with new resolution. Display disable
will turn off both pixel clock and main link clock so that main link
have to be re trained during display enable to have new video stream
flow again. At current impl
On Fri, 27 May 2022 11:55:42 +0100
Tvrtko Ursulin wrote:
> On 27/05/2022 10:09, Mauro Carvalho Chehab wrote:
> > i915 selftest hangcheck is causing the i915 driver timeouts, as
> > reported by Intel CI:
> >
> >
> > http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a9
On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_
On 2022-05-27 22:38:24, Dmitry Baryshkov wrote:
> [..]
> > #define INTF_CFG2_DATABUS_WIDEN BIT(0)
> > #define INTF_CFG2_DATA_HCTL_ENBIT(4)
> >
> > +#define INTF_MISR_CTRL 0x180
> > +#define INTF_MISR_SIGNATURE0x184
> > +#define INTF_MISR_FRAME_COUNT_
On 27/05/2022 21:54, Jessica Zhang wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Signed-off-by: Jessica Zhang
Reviewed-by: Dmitry Baryshkov
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 43 ++-
drivers/gpu/drm/msm/disp
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions
On Fri, May 27, 2022 at 2:07 AM Sudip Mukherjee
wrote:
>
> declared with attribute error: BUILD_BUG_ON failed: sizeof(*edid) !=
> EDID_LENGTH
>
> And, reverting it on top of mainline branch has fixed the build failure.
Hmm. That BUILD_BUG_ON() looks entirely correct, and if that sizeof()
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 43 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 3 +
drivers/gpu/drm/ms
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 72 +++-
Refactor existing CRC code for layer mixer and add CRC support for interface
blocks
Jessica Zhang (3):
drm/msm/dpu: Separate LM-specific CRC code from generic CRC code
drm/msm/dpu: Add MISR register support for interface
drm/msm/dpu: Add interface support for CRC debugfs
drivers/gpu/drm/m
On Thu, May 26, 2022 at 11:18:17AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2022 19:05, Matt Roper wrote:
> > On Wed, May 25, 2022 at 05:03:13PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 24/05/2022 18:51, Matt Roper wrote:
> > > > On Tue, May 24, 2022 at 10:43:39AM +0100, Tvrtko Ursulin wrote:
From: Rob Clark
Previously the BO_PINNED state in the submit was tracking two related
but different things: (1) that the buffer object was pinned, and (2)
that the vma (mapping within a set of pagetables) was pinned. But with
fenced vma unpin (needed so that userspace couldn't race with retire
p
On Fri, 27 May 2022 at 19:08, Kuogee Hsieh wrote:
>
> During display resolution changes display have to be disabled first
> followed by display enabling with new resolution. At current
> implementation, display enable function manually kicks up
> irq_hpd_handle which will read panel link status an
On Fri, May 27, 2022 at 01:10:46AM -0700, Lucas De Marchi wrote:
> This reverts commit bcefacd359f07dee18795dd80f834acb47fd21eb.
>
> IGT conversion is ready, so these execptions can already be removed.
> Once CI is clean, this commit will actually be removed from
> topic/core-for-CI.
>
> Signed-o
From: Stuart Summers
Bspec: 64027
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 ++---
drivers/gpu/drm/i915/i
For PVC, the base die and compute tile have separate stepping values
that we need to track; we'll use the existing graphics_step field to
represent the compute tile stepping and add a new 'basedie_step' field.
Unlike past platforms, steppings for these components are represented by
specific bitfie
Matt Roper (1):
drm/i915/pvc: Extract stepping information from PCI revid
Stuart Summers (1):
drm/i915/pvc: Add initial PVC workarounds
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 +
Reviewed-by: Lyude Paul
Do you need me to push this to drm-misc? Or will this be pushed as one series?
On Fri, 2022-05-27 at 12:22 +0800, 1064094...@qq.com wrote:
> From: pengfuyuan
>
> Fix spelling typo in comments.
>
> Reported-by: k2ci
> Signed-off-by: pengfuyuan
> ---
> drivers/gpu/drm
During display resolution changes display have to be disabled first
followed by display enabling with new resolution. At current
implementation, display enable function manually kicks up
irq_hpd_handle which will read panel link status and start link
training if link status is not in sync state. Ho
Acked-by: Alyssa Rosenzweig
On Fri, May 27, 2022 at 02:50:22AM +0300, Dmitry Osipenko wrote:
> Calling madvise IOCTL twice on BO causes memory shrinker list corruption
> and crashes kernel because BO is already on the list and it's added to
> the list again, while BO should be removed from from t
On 5/26/2022 5:07 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-05-26 10:26:18)
During display resolution changes display have to be disabled first
followed by display enable with new resolution. This patch force
main link always be retrained during display enable procedure to
simplify im
On 27.05.2022 09:24, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have long standing customer complaints that pressing Ctrl-C (or to the
effect of) causes engine resets with otherwise well behaving programs.
Not only is logging engine resets during normal operation not desirable
since it crea
Acked-by: Alyssa Rosenzweig
On Fri, May 27, 2022 at 02:50:40AM +0300, Dmitry Osipenko wrote:
> Replace Panfrost's memory shrinker with a generic drm-shmem memory
> shrinker.
>
> Tested-by: Steven Price
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/gpu/drm/panfrost/Makefile |
https://bugzilla.kernel.org/show_bug.cgi?id=205089
--- Comment #43 from Luke A. Guest (lagu...@archeia.com) ---
Oh, and I've tested 5.18.0, 5.17.7/6/5 - all the same error/hang.
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https://bugzilla.kernel.org/show_bug.cgi?id=205089
Luke A. Guest (lagu...@archeia.com) changed:
What|Removed |Added
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On Fri, May 27, 2022 at 10:24:42AM +0800, ChiYuan Huang wrote:
> Daniel Thompson 於 2022年5月26日 週四 下午6:05寫道：
> >
> > On Thu, May 26, 2022 at 11:16:35AM +0800, cy_huang wrote:
> > > From: ChiYuan Huang
> > >
> > > Add the property parsing for ocp level selection.
> >
> > Isn't this just restating th
On 27/05/2022 10:09, Mauro Carvalho Chehab wrote:
i915 selftest hangcheck is causing the i915 driver timeouts, as
reported by Intel CI:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only outpu
On 26/05/2022 23:08, Linus Walleij wrote:
On Wed, May 25, 2022 at 3:36 PM Dmitry Baryshkov
wrote:
On Mon, 23 May 2022 at 15:55, Linus Walleij wrote:
Nope, failed:
$ dim push-branch drm-misc-next
dim: ac890b9eeb9b ("drm/display: Fix build error without CONFIG_OF"):
Fixes: SHA1 in not pointi
On Thu, 2022-05-19 at 13:48 +0200, Marek Vasut wrote:
> Add support for i.MX8MP LCDIF variant. This is called LCDIFv3 and is
> completely different from the LCDIFv3 found in i.MX23 in that it has
> a completely scrambled register layout compared to all previous LCDIF
> variants. The new LCDIFv3 als
i915 selftest hangcheck is causing the i915 driver timeouts, as
reported by Intel CI:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only output is:
[ 68.811639] i915: Performing live se
Hi All,
The latest mainline kernel branch fails to build for arm spear3xx_defconfig
with the error:
In function 'edid_block_data',
inlined from 'drm_edid_is_valid' at drivers/gpu/drm/drm_edid.c:1904:25:
././include/linux/compiler_types.h:352:45: error: call to
'__compiletime_assert_250'
From: Mauro Carvalho Chehab
i915 selftest hangcheck is causing the i915 driver timeouts, as
reported by Intel CI:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only output is:
[ 68.81
Felix Kuehling writes:
> Am 2022-05-25 um 00:11 schrieb Alistair Popple:
>> Alex Sierra writes:
>>
>>> With DEVICE_COHERENT, we'll soon have vm_normal_pages() return
>>> device-managed anonymous pages that are not LRU pages. Although they
>>> behave like normal pages for purposes of mapping in
This reverts commit bcefacd359f07dee18795dd80f834acb47fd21eb.
IGT conversion is ready, so these execptions can already be removed.
Once CI is clean, this commit will actually be removed from
topic/core-for-CI.
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21
To discover support for new DMA-BUF IOCTLs, user-space has no
choice but to try to perform the IOCTL on an existing DMA-BUF.
However, user-space may want to figure out whether or not the
IOCTL is available before it has a DMA-BUF at hand, e.g. at
initialization time in a Wayland compositor.
Add a
From: Tvrtko Ursulin
We have long standing customer complaints that pressing Ctrl-C (or to the
effect of) causes engine resets with otherwise well behaving programs.
Not only is logging engine resets during normal operation not desirable
since it creates support incidents, but more fundamentally
[2022-05-26 21:47:52] Javier Martinez Canillas:
Commit b3c9a924aab6 ("fbdev: vesafb: Cleanup fb_info in .fb_destroy rather
than .remove") fixed a use-after-free error due the vesafb driver freeing
the fb_info in the .remove handler instead of doing it in .fb_destroy.
This can happen if the .fb_d
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