Hi Dave & Daniel,
Here's a batch of -next-fixes from drm-intel-next/drm-intel-gt-next.
On GT side just a fix to relax GGTT alignment down 64K from 2M.
Addition of missing "name" attribute for GVT mdev device.
On display side async flip fixes and a static checker fix.
CI results had some display
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
v2: fix white space errors
Cc: Ashutosh D
I have no objection :)
Huacai
On Thu, Mar 10, 2022 at 12:29 AM Bjorn Helgaas wrote:
>
> On Fri, Feb 25, 2022 at 04:15:23PM -0600, Bjorn Helgaas wrote:
> > On Thu, Feb 24, 2022 at 04:47:42PM -0600, Bjorn Helgaas wrote:
> > > From: Bjorn Helgaas
> > >
> > > Current default VGA device selection fa
On Thu, Mar 10, 2022 at 11:33 AM xinlei.lee wrote:
>
> On Tue, 2022-03-08 at 11:00 +0100, Benjamin Gaignard wrote:
> > Le 08/03/2022 à 10:12, Hsin-Yi Wang a écrit :
> > > On Fri, Mar 4, 2022 at 7:25 PM Benjamin Gaignard
> > > wrote:
> > > >
> > > > Le 04/03/2022 à 11:15, xinlei@mediatek.com a
On Sun, Mar 06, 2022 at 09:19:10AM -0500, Theodore Ts'o wrote:
> On Sun, Mar 06, 2022 at 07:51:42PM +0900, Byungchul Park wrote:
> > >
> > > Users of DEPT must not have to understand how DEPT works in order to
> >
> > Users must not have to understand how Dept works for sure, and haters
> > must
On Wed, Mar 9, 2022 at 1:11 PM Jagan Teki wrote:
>
> or a Hi All,
>
> On Thu, Oct 14, 2021 at 6:45 PM Jagan Teki wrote:
> >
> > Hi Laurent,
> >
> > On Fri, Oct 8, 2021 at 7:07 PM Laurent Pinchart
> > wrote:
> > >
> > > Hello,
> > >
> > > On Fri, Oct 08, 2021 at 03:27:43PM +0200, Andrzej Hajda w
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
Cc: Ashutosh Dixit
Cc: Matt Roper
UMD (m
m: kworker/u8:5 Not tainted 5.17.0-rc7-next-20220309+
#158
Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS
rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
Workqueue: events_unbound commit_work
Call Trace:
dump_stack_lvl+0x49/0x5e
print_report.cold+
Hi Dave, Daniel,
Same PR from last week with fixed Fixes tag, clang warning fix, and
a CS rework regression fix.
The following changes since commit 38a15ad9488e21cad8f42d3befca20f91e5b2874:
Merge tag 'amd-drm-next-5.18-2022-02-25' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2
On 3/10/22 00:51, Rob Clark wrote:
> On Wed, Mar 9, 2022 at 12:06 PM Dmitry Osipenko
> wrote:
>>
>> On 3/9/22 03:56, Rob Clark wrote:
If we really can't track madvise state in the guest for dealing with
host memory pressure, I think the better option is to introduce
MADV:WILLNEED_RE
On 3/9/22 22:28, Thomas Zimmermann wrote:
> Hi
>
> Am 09.03.22 um 12:55 schrieb Dmitry Osipenko:
>> Hello,
>>
>> On 3/9/22 11:59, Thomas Zimmermann wrote:
>>> Hi
>>>
>>> Am 08.03.22 um 14:17 schrieb Dmitry Osipenko:
Hello,
This patchset introduces memory shrinker for the VirtIO-GPU
On Thu, 10 Mar 2022 at 08:16, Alex Deucher wrote:
>
> On Wed, Mar 9, 2022 at 5:12 PM Dave Airlie wrote:
> >
> > On Tue, 8 Mar 2022 at 06:08, Alex Deucher wrote:
> > >
> > > Hi Dave, Daniel,
> > >
> > > Same PR as last week, just fixed up a bad Fixes tag.
> > >
> > > The following changes since c
On Wed, Mar 9, 2022 at 5:12 PM Dave Airlie wrote:
>
> On Tue, 8 Mar 2022 at 06:08, Alex Deucher wrote:
> >
> > Hi Dave, Daniel,
> >
> > Same PR as last week, just fixed up a bad Fixes tag.
> >
> > The following changes since commit 38a15ad9488e21cad8f42d3befca20f91e5b2874:
> >
> > Merge tag 'am
On Tue, 8 Mar 2022 at 06:08, Alex Deucher wrote:
>
> Hi Dave, Daniel,
>
> Same PR as last week, just fixed up a bad Fixes tag.
>
> The following changes since commit 38a15ad9488e21cad8f42d3befca20f91e5b2874:
>
> Merge tag 'amd-drm-next-5.18-2022-02-25' of
> https://gitlab.freedesktop.org/agd5f/
On Wed, Mar 9, 2022 at 12:06 PM Dmitry Osipenko
wrote:
>
> On 3/9/22 03:56, Rob Clark wrote:
> >> If we really can't track madvise state in the guest for dealing with
> >> host memory pressure, I think the better option is to introduce
> >> MADV:WILLNEED_REPLACE, ie. something to tell the host ker
No problem. squashed in:
https://gitlab.freedesktop.org/agd5f/linux/-/commit/74041e46982cd627e7b52f9c3ed37d23a4973b5f
Alex
Alex
On Wed, Mar 9, 2022 at 4:23 PM Felix Kuehling wrote:
>
> On 2022-03-09 16:20, David Yat Sin wrote:
> > Signed-off-by: David Yat Sin
>
> Please add the commit descri
On 3/9/22 9:52 AM, T.J. Mercier wrote:
This test verifies that the cgroup GPU memory charge is transferred
correctly when a dmabuf is passed between processes in two different
cgroups and the sender specifies BINDER_BUFFER_FLAG_SENDER_NO_NEED in the
binder transaction data containing the dmabuf f
On Wed, Mar 9, 2022 at 4:21 PM Alex Deucher wrote:
>
> On Wed, Mar 9, 2022 at 4:10 PM Felix Kuehling wrote:
> >
> > On 2022-03-09 12:41, David Yat Sin wrote:
> > > Set dmabuf handle to invalid for BOs that cannot be accessed using SDMA
> > > during checkpoint/restore.
> > >
> > > Signed-off-by: D
On 2022-03-09 16:20, David Yat Sin wrote:
Signed-off-by: David Yat Sin
Please add the commit description back. And let's wait for Alex to
confirm that the fixup-method is OK. With that fixed, the patch is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 +++
On Wed, Mar 9, 2022 at 4:10 PM Felix Kuehling wrote:
>
> On 2022-03-09 12:41, David Yat Sin wrote:
> > Set dmabuf handle to invalid for BOs that cannot be accessed using SDMA
> > during checkpoint/restore.
> >
> > Signed-off-by: David Yat Sin
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ++
include/uapi/linux/kfd_ioctl.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index e1e2362841f8..607f65ab39
On 3/8/2022 01:41, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat wi
On 3/8/2022 01:43, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst
On 2022-03-09 12:41, David Yat Sin wrote:
Set dmabuf handle to invalid for BOs that cannot be accessed using SDMA
during checkpoint/restore.
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++--
include/uapi/linux/kfd_ioctl.h | 2 ++
2 files chang
Hi,
On Wed, Mar 9, 2022 at 9:05 AM Kieran Bingham
wrote:
>
> >> I think it was done for DRM purpose, to prevent signals meant for a
> >> panel to be connected to a device that could capture video from a DP
> >> source.
>
> Is this better:
>
> /*
> * Only eDP pannels which support
Hi Sean,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip
drm-exynos/exynos-drm-next next-20220309]
[cannot apply to tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc7]
[If your
Hello Geert,
On 3/9/22 21:04, Geert Uytterhoeven wrote:
[snip]
>> +
>> + /* Last page may be partial */
>> + if (8 * (i + 1) > ssd130x->height)
>> + m = ssd130x->height % 8;
>> + for (j = x; j < x + width; j++) {
>> +
On 3/9/22 03:56, Rob Clark wrote:
>> If we really can't track madvise state in the guest for dealing with
>> host memory pressure, I think the better option is to introduce
>> MADV:WILLNEED_REPLACE, ie. something to tell the host kernel that the
>> buffer is needed but the previous contents are not
Hi Javier,
On Mon, Feb 14, 2022 at 2:37 PM Javier Martinez Canillas
wrote:
> This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon
> OLED display controllers.
>
> It's only the core part of the driver and a bus specific driver is needed
> for each transport interface supported
Hi
Am 09.03.22 um 12:55 schrieb Dmitry Osipenko:
Hello,
On 3/9/22 11:59, Thomas Zimmermann wrote:
Hi
Am 08.03.22 um 14:17 schrieb Dmitry Osipenko:
Hello,
This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
During OOM, the shrinker will release BOs that are marked as "not
Hi,
On Tue, Mar 8, 2022 at 8:55 AM Vinod Polimera wrote:
>
> use max clock during probe/bind sequence from the opp table.
> The clock will be scaled down when framework sends an update.
>
> Signed-off-by: Vinod Polimera
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
> 1 file changed,
or a Hi All,
On Thu, Oct 14, 2021 at 6:45 PM Jagan Teki wrote:
>
> Hi Laurent,
>
> On Fri, Oct 8, 2021 at 7:07 PM Laurent Pinchart
> wrote:
> >
> > Hello,
> >
> > On Fri, Oct 08, 2021 at 03:27:43PM +0200, Andrzej Hajda wrote:
> > > Hi,
> > >
> > > Removed my invalid email (I will update files n
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
>
> From: Shashank Sharma
>
> This patch adds a new sysfs event, which will indicate
> the userland about a GPU reset, and can also provide
> some information like:
> - process ID of the process involved with the GPU reset
> - process name of
On Wed, Mar 9, 2022 at 12:54 PM Rajat Jain wrote:
>
> On Wed, Mar 9, 2022 at 7:06 AM Sean Paul wrote:
> >
> > From: Sean Paul
> >
> > This patch adds the necessary hooks to make amdgpu aware of privacy
> > screens. On devices with privacy screen drivers (such as thinkpad-acpi),
> > the amdgpu dr
Set dmabuf handle to invalid for BOs that cannot be accessed using SDMA
during checkpoint/restore.
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++--
include/uapi/linux/kfd_ioctl.h | 2 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git
Quoting Doug Anderson (2022-03-07 23:22:00)
> Hi,
>
> On Mon, Mar 7, 2022 at 10:00 AM Kieran Bingham
> wrote:
> >
> > From: Laurent Pinchart
> >
> > Despite the SN65DSI86 being an eDP bridge, on some systems its output is
> > routed to a DisplayPort connector. Enable DisplayPort mode when the ne
Hi Sam,
Quoting Sam Ravnborg (2022-02-06 15:44:02)
> From: Rob Clark
>
> Slightly awkward to fish out the display_info when we aren't creating
> own connector. But I don't see an obvious better way.
>
> v3:
> - Rebased and dropped the ti_sn_bridge_get_bpp() patch
>as this was solved in a
On Fri, Feb 25, 2022 at 04:15:23PM -0600, Bjorn Helgaas wrote:
> On Thu, Feb 24, 2022 at 04:47:42PM -0600, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas
> >
> > Current default VGA device selection fails in some cases because part of it
> > is done in the vga_arb_device_init() subsys_initcall, and
From: Manasi Navare
[ Upstream commit 62929726ef0ec72cbbe9440c5d125d4278b99894 ]
VRR capable property is not attached by default to the connector
It is attached only if VRR is supported.
So if the driver tries to call drm core set prop function without
it being attached that causes NULL derefere
From: Manasi Navare
[ Upstream commit 62929726ef0ec72cbbe9440c5d125d4278b99894 ]
VRR capable property is not attached by default to the connector
It is attached only if VRR is supported.
So if the driver tries to call drm core set prop function without
it being attached that causes NULL derefere
From: Manasi Navare
[ Upstream commit 62929726ef0ec72cbbe9440c5d125d4278b99894 ]
VRR capable property is not attached by default to the connector
It is attached only if VRR is supported.
So if the driver tries to call drm core set prop function without
it being attached that causes NULL derefere
From: Manasi Navare
[ Upstream commit 62929726ef0ec72cbbe9440c5d125d4278b99894 ]
VRR capable property is not attached by default to the connector
It is attached only if VRR is supported.
So if the driver tries to call drm core set prop function without
it being attached that causes NULL derefere
Hi,
On Thu, Mar 3, 2022 at 3:02 PM Doug Anderson wrote:
>
> Hi,
>
> On Tue, Mar 1, 2022 at 6:11 PM Brian Norris wrote:
> >
> > DP AUX transactions can consist of many short operations. There's no
> > need to power things up/down in short intervals.
> >
> > I pick an arbitrary 100ms; for the syst
On Mon, Mar 7, 2022 at 3:30 PM Niranjana Vishwanathapura
wrote:
>
> VM_BIND design document with description of intended use cases.
>
> Signed-off-by: Niranjana Vishwanathapura
> ---
> Documentation/gpu/rfc/i915_vm_bind.rst | 210 +
> Documentation/gpu/rfc/index.rst
Hi,
On Tue, Mar 8, 2022 at 11:07 AM Douglas Anderson wrote:
>
> The bindings for bridge chips should also get the same maintainers
> entry so the right people get notified about bindings changes.
>
> Signed-off-by: Douglas Anderson
> ---
>
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
Hi,
On 3/9/22 16:06, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds the necessary hooks to make amdgpu aware of privacy
> screens. On devices with privacy screen drivers (such as thinkpad-acpi),
> the amdgpu driver will defer probe until it's ready and then sync the sw
> and hw state on
On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at
lower frequencies causes display instability. On such platforms, it
is better to avoid switching lanes from 4 to 3 as it needs different
set of PLL parameter constraints to make the display stable with 3
lanes.
This patch adds an
On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at
lower frequencies causes display instability. On such platforms, it
is better to avoid switching lanes from 4 to 3 as it needs different
set of PLL parameter constraints to make the display stable with 3
lanes.
This patch introduc
From: Sean Paul
This patch adds the necessary hooks to make amdgpu aware of privacy
screens. On devices with privacy screen drivers (such as thinkpad-acpi),
the amdgpu driver will defer probe until it's ready and then sync the sw
and hw state on each commit the connector is involved and enabled.
On Mon, 21 Feb 2022 at 09:55, Maxime Ripard wrote:
>
> On Mon, Feb 21, 2022 at 08:28:35AM +0100, José Expósito wrote:
> > The function "drm_of_find_panel_or_bridge" has been deprecated in
> > favor of "devm_drm_of_get_bridge".
> >
> > Switch to the new function and reduce boilerplate.
> >
> > Sign
https://bugzilla.kernel.org/show_bug.cgi?id=205089
--- Comment #33 from Alex Deucher (alexdeuc...@gmail.com) ---
Please try newer or older mesa drivers if you can repro this with a particular
game like dota2. The kernel driver is just the messenger.
--
You may reply to this email to add a comme
Quoting Doug Anderson (2022-03-07 23:22:17)
> Hi,
>
> On Mon, Mar 7, 2022 at 10:00 AM Kieran Bingham
> wrote:
> >
> > @@ -1264,6 +1321,14 @@ static int ti_sn_bridge_probe(struct
> > auxiliary_device *adev,
> > return PTR_ERR(pdata->next_bridge);
> > }
> >
> > + pdat
This is the link to the user mode change:
https://github.com/checkpoint-restore/criu/pull/1709
Regards,
David
> -Original Message-
> From: Kuehling, Felix
> Sent: Tuesday, March 8, 2022 4:20 PM
> To: Yat Sin, David ; amd-...@lists.freedesktop.org;
> dri-devel@lists.freedesktop.org
> Subj
Hi
This patch seems to be causing me problems
https://gitlab.freedesktop.org/drm/amd/-/issues/1927
There are 3 issues I'm experiencing, two kernel bugs and a mesa bug
Cheers
Mike
On Mon, 14 Feb 2022 at 09:34, Christian König
wrote:
>
> This is provided by TTM now.
>
> Also switch man->size t
[AMD Official Use Only]
Please ignore the previous email, that was sent in error. This one is with the
minor version bump so this looks good.
Reviewed-by : Rajneesh Bhardwaj
-Original Message-
From: amd-gfx On Behalf Of David Yat Sin
Sent: Tuesday, March 8, 2022 4:08 PM
To: amd-...@li
Hi Frieder,
On Wed, Mar 9, 2022 at 6:54 PM Frieder Schrempf
wrote:
>
> Hi Jagan,
>
> Am 03.03.22 um 17:36 schrieb Jagan Teki:
> > Updated series about drm bridge conversion of exynos dsi.
> >
> > Previous version can be accessible, here [1].
> >
> > Patch 1: tc358764 panel_bridge API
> >
> > Patc
[AMD Official Use Only]
Reviewed-by: Rajneesh Bhardwaj
-Original Message-
From: amd-gfx On Behalf Of David Yat Sin
Sent: Tuesday, March 8, 2022 2:12 PM
To: amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
Cc: Kuehling, Felix ; Yat Sin, David
Subject: [PATCH] drm/amdkfd:
On 3/9/22 13:56, Geert Uytterhoeven wrote:
> On Wed, Mar 9, 2022 at 2:57 AM Chen-Yu Tsai wrote:
>> From: Chen-Yu Tsai
>>
>> The SSD130x's command to toggle COM scan direction uses bit 3 and only
>> bit 3 to set the direction of the scanout. The driver has an incorrect
>> GENMASK(3, 2), causing th
On Fri, 4 Mar 2022 at 13:12, Kieran Bingham
wrote:
>
> Hi José
>
> Quoting Kieran Bingham (2022-03-03 21:59:26)
> > Quoting José Expósito (2022-03-03 18:37:20)
> > > On Mon, Feb 28, 2022 at 11:24:36PM +, Kieran Bingham wrote:
> > > > Hi José
> > > >
> > > > Quoting José Expósito (2022-02-28 18
On Wed, 9 Mar 2022 at 02:45, Tom Rix wrote:
>
>
> On 3/8/22 2:57 PM, Nick Desaulniers wrote:
> > On Thu, Mar 3, 2022 at 12:19 PM wrote:
> >> From: Tom Rix
> >>
> >> Clang static analysis reports this issue
> >> anx7625.c:876:13: warning: The left operand of '&' is
> >>a garbage value
> >>
Hello Geert,
On 3/9/22 13:56, Geert Uytterhoeven wrote:
> Hi Javier,
>
> On Wed, Mar 9, 2022 at 1:14 PM Javier Martinez Canillas
> wrote:
>> On 3/8/22 17:30, Geert Uytterhoeven wrote:
>>> Unfortunately a regression was introduced since your v3: printed
>>> text is mirrored upside-down. I.e. "E"
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> As Rn is light-on-dark, and Cn can be any colors, there are currently
> no fourcc codes to describe dark-on-light displays.
>
> Introduce fourcc codes for a single-channel dark-on-light frame buffer
> format with two, four, sixteen, or 256 darkness leve
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Introduce fourcc codes for single-channel light-on-dark frame buffer
> formats with two, four, and sixteen intensity levels.
>
> As the number of bits per pixel is less than eight, these rely on proper
> block handling for the calculation of bits per pi
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Traditionally, the first channel has been called the "red" channel, but
> the fourcc values for single-channel "red" formats can also be used for
> other light-on-dark displays, like grayscale.
>
> Signed-off-by: Geert Uytterhoeven
> ---
Yes, I learne
Hi Jagan,
Am 03.03.22 um 17:36 schrieb Jagan Teki:
> Updated series about drm bridge conversion of exynos dsi.
>
> Previous version can be accessible, here [1].
>
> Patch 1: tc358764 panel_bridge API
>
> Patch 2: connector reset
>
> Patch 3: bridge attach in MIC
>
> Patch 4: panel_bridge API
On Tue, 8 Mar 2022 at 20:07, Douglas Anderson wrote:
>
> Though the parade bridge chip is a little bit of a black box, I'm at
> least interested in hearing about changes to the driver since this
> bridge chip is used on some Chromebooks that I'm involved with.
>
> Signed-off-by: Douglas Anderson
On Tue, 8 Mar 2022 at 20:07, Douglas Anderson wrote:
>
> I've spent quite a bit of time poking at this driver and it's used on
> several Chromebooks I'm involved with. I'd like to get notified about
> patches. Add myself as a reviewer. It's expected that changes will
> still be landed through drm-
On Wed, 9 Mar 2022 at 08:36, Rex-BC Chen wrote:
>
> Resend v11:
> - Resend this series for reviewing.
> - Rebase to 5.17-rc7.
>
> Changes since v10:
> - Rebase to 5.17-rc3.
> - Add more maintainers.
>
> Changes since v9:
> - Change description of "MIPI_DSI_HS_PKT_END_ALIGNED".
> - Use mode_f
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> The AFBC helpers derive the number of bits per pixel from the deprecated
> drm_format_info.cpp[] field, which does not take into account block
> sizes.
>
> Fix this by using the actual number of bits per pixel instead.
>
> Signed-off-by: Geert Uytterho
Hi Javier,
On Wed, Mar 9, 2022 at 2:10 PM Javier Martinez Canillas
wrote:
> On 3/7/22 21:52, Geert Uytterhoeven wrote:
> > Add support for color-indexed frame buffer formats with two, four, and
> > sixteen colors to the DRM framebuffer helper functions:
> > 1. Add support for 1, 2, and 4 bits p
On Wed, 9 Mar 2022 at 09:04, Neil Armstrong wrote:
>
> On 08/03/2022 20:06, Douglas Anderson wrote:
> > The bindings for bridge chips should also get the same maintainers
> > entry so the right people get notified about bindings changes.
> >
> > Signed-off-by: Douglas Anderson
> > ---
> >
> > M
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Add support for color-indexed frame buffer formats with two, four, and
> sixteen colors to the DRM framebuffer helper functions:
> 1. Add support for 1, 2, and 4 bits per pixel to the damage helper,
> 2. For color-indexed modes, the length of the col
Hi Javier,
On Wed, Mar 9, 2022 at 1:14 PM Javier Martinez Canillas
wrote:
> On 3/8/22 17:30, Geert Uytterhoeven wrote:
> > Unfortunately a regression was introduced since your v3: printed
> > text is mirrored upside-down. I.e. "E" is rendered correctly, but "L"
> > turns into "Γ" (Greek Gamma).
>
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen colors, and provide a mapping from bit per pixel and
> depth to fourcc codes.
>
> As the number of bits per pixel is less than eight, these rely on proper
> bloc
On Wed, Mar 9, 2022 at 2:57 AM Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> The SSD130x's command to toggle COM scan direction uses bit 3 and only
> bit 3 to set the direction of the scanout. The driver has an incorrect
> GENMASK(3, 2), causing the setting to be set on bit 2, rendering it
> ineff
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> When userspace queries the properties of a frame buffer, the number of
> bits per pixel is derived from the deprecated drm_format_info.cpp[]
> field, which does not take into account block sizes.
>
> Fix this by using the actual number of bits per pixel
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> When allocating a frame buffer, the number of bits per pixel needed is
> derived from the deprecated drm_format_info.cpp[] field. While this
> works for formats using less than 8 bits per pixel, it does lead to a
> large overallocation.
>
> Reduce memo
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Add a flag to struct drm_format_info to indicate if a format is
> color-indexed, similar to the existing .is_yuv flag.
>
> This way generic code and drivers can just check this flag, instead of
> checking against a list of fourcc formats.
>
> Signed-of
Hello Geert,
On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Add a helper to retrieve the actual number of bits per pixel for a
> plane, taking into account the number of characters and pixels per
> block for tiled formats.
>
> Signed-off-by: Geert Uytterhoeven
> ---
Patch looks good to me.
Revie
On Tue, Mar 8, 2022 at 8:52 PM Thomas Zimmermann wrote:
>
> Move the code for enabling and disabling the GTT into helpers and call
> the functions in psb_gtt_init(), psb_gtt_fini() and psb_gtt_resume().
> Removes code duplication.
That makes it much more readable. Thanks.
Acked-by: Patrik Jakobs
On Tue, Mar 8, 2022 at 8:52 PM Thomas Zimmermann wrote:
>
> Move the setup code for GTT/GATT memory ranges into a new helper and
> call the function from psb_gtt_init() and psb_gtt_resume(). Removes
> code duplication.
LGTM
Acked-by: Patrik Jakobsson
>
> Signed-off-by: Thomas Zimmermann
> ---
On 3/8/22 17:30, Geert Uytterhoeven wrote:
> Hi Javier,
>
> On Mon, Feb 14, 2022 at 2:37 PM Javier Martinez Canillas
> wrote:
>> This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon
>> OLED display controllers.
>>
>> It's only the core part of the driver and a bus specific dri
On 2022-02-25 07:51, Sascha Hauer wrote:
The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.
Further to the clarification of the underlying pu
On 2022-03-09 08:37, elaine.zhang wrote:
hi,
在 2022/3/9 下午4:18, Sascha Hauer 写道:
Hi Elaine,
On Wed, Mar 09, 2022 at 09:41:39AM +0800, zhangq...@rock-chips.com wrote:
hi，all：
Let me explain the clock dependency：
From the clock tree, pclk_vo0 and hclk_vo0 are completely
independen
Hello Geert,
Thanks a lot for your feedback.
On 3/8/22 17:13, Geert Uytterhoeven wrote:
[snip]
>> +
>> +static void drm_fb_gray8_to_mono_reversed_line(u8 *dst, const u8 *src,
>> unsigned int pixels,
>
> "pixels" is not the number of pixels to process, but the number of
> bytes in the monochro
On 3/9/22 04:12, Rob Clark wrote:
>> +static unsigned long
>> +virtio_gpu_gem_shrinker_count_objects(struct shrinker *shrinker,
>> + struct shrink_control *sc)
>> +{
>> + struct drm_gem_shmem_object *shmem;
>> + struct virtio_gpu_device *vgdev;
>> +
Hello,
On 3/9/22 11:59, Thomas Zimmermann wrote:
> Hi
>
> Am 08.03.22 um 14:17 schrieb Dmitry Osipenko:
>> Hello,
>>
>> This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
>> During OOM, the shrinker will release BOs that are marked as "not needed"
>> by userspace using the ne
me-related-improvements/20220303-013028
base: git://anongit.freedesktop.org/drm/drm drm-next
config: s390-randconfig-m031-20220307
(https://download.01.org/0day-ci/archive/20220309/202203091923.2rd2ech3-...@intel.com/config)
compiler: s390-linux-gcc (GCC) 11.2.0
If you fix the issue, kindly add follow
On 3/9/22 09:52, Thomas Zimmermann wrote:
[snip]
>>> +struct drm_gem_object *virtio_gpu_create_object_fbdev(struct drm_device
>>> *dev,
>>> + size_t size)
>>> +{
>>> + return ERR_PTR(-ENOSYS);
>>> +}
>>
>> As mentioned, I believe this should be E
On 3/9/22 09:47, Thomas Zimmermann wrote:
[snip]
>>>
>>> +static const struct drm_gem_object_funcs drm_gem_shmem_funcs_fbdev = {
>>> + .free = drm_gem_shmem_object_free,
>>> + .print_info = drm_gem_shmem_object_print_info,
>>> + .pin = drm_gem_shmem_object_pin,
>>> + .unpin = drm_gem_s
Hello Thomas,
On 3/9/22 09:36, Thomas Zimmermann wrote:
[snip]
>
> I thought about using pageref->offset in fbdev drivers as well. It would
> be more correct, but didn't want to add unnecessary churn. Especially
> since I cannot test most of the fbdev drivers. If you think it's worth
> it, I
On 3/9/2022 8:47 AM, Simon Ser wrote:
Hi,
Maybe it would be a good idea to state the intended use-case in the
commit message?
It was added in the second patch, but yeah, it makes more sense to add a
cover-letter probably.
And explain why the current (driver-specific IIRC) APIs
aren't e
Hi Marek,
On Wed, Mar 9, 2022 at 10:22 AM Marek Szyprowski
wrote:
> On 09.03.2022 09:22, Thomas Zimmermann wrote:
> > Am 08.03.22 um 23:52 schrieb Marek Szyprowski:
> >> On 23.02.2022 20:38, Thomas Zimmermann wrote:
> >>> Improve the performance of cfb_imageblit() by manually unrolling
> >>> the
Den 24.11.2021 16.07, skrev Noralf Trønnes:
> Hi,
>
> This patchset adds a missing piece for decommissioning the
> staging/fbtft/fb_st7735r.c driver namely a way to configure the
> controller from Device Tree.
>
> All fbtft drivers have builtin support for one display panel and all
> other pan
On 09/03/2022 11:24, Christian König wrote:
> Am 09.03.22 um 11:10 schrieb Simon Ser:
>> On Wednesday, March 9th, 2022 at 10:56, Pierre-Eric Pelloux-Prayer
>> wrote:
>>
>>> Would it be possible to include the app parameters as well?
>> Can all processes read sysfs events?
>
> No, but applicat
On Wednesday, March 9th, 2022 at 11:24, Christian König
wrote:
> Am 09.03.22 um 11:10 schrieb Simon Ser:
> > On Wednesday, March 9th, 2022 at 10:56, Pierre-Eric Pelloux-Prayer
> > wrote:
> >
> >> Would it be possible to include the app parameters as well?
> > Can all processes read sysfs event
Am 09.03.22 um 11:10 schrieb Simon Ser:
On Wednesday, March 9th, 2022 at 10:56, Pierre-Eric Pelloux-Prayer
wrote:
Would it be possible to include the app parameters as well?
Can all processes read sysfs events?
No, but application parameters are usually not secret.
There might be securit
On Wednesday, March 9th, 2022 at 10:56, Pierre-Eric Pelloux-Prayer
wrote:
> Would it be possible to include the app parameters as well?
Can all processes read sysfs events?
There might be security implications here. The app parameters might
contain sensitive information, like passwords or toke
Hi Shashank,
On 08/03/2022 19:04, Shashank Sharma wrote:
> From: Shashank Sharma
>
> This patch adds a new sysfs event, which will indicate
> the userland about a GPU reset, and can also provide
> some information like:
> - process ID of the process involved with the GPU reset
> - process name o
On Mon, 07 Mar 2022, Colin Ian King wrote:
> Don't populate the read-only array div1_vals on the stack but
> instead make it static const. Also makes the object code a little
> smaller.
Thanks, but this was just fixed in commit fe70b262e781 ("drm/i915: Move
a bunch of stuff into rodata from the s
1 - 100 of 114 matches
Mail list logo
