Hi Sascha:
On 2/18/22 16:00, Sascha Hauer wrote:
On Fri, Feb 18, 2022 at 11:50:32AM +0800, Andy Yan wrote:
Hi Sascha:
On 2/17/22 22:06, Heiko Stübner wrote:
Am Donnerstag, 17. Februar 2022, 14:58:23 CET schrieb Sascha Hauer:
Hi Andy,
Please trim the context in your answers to the relevant p
On Thu, Feb 17, 2022 at 06:09:53PM +, Matthew Auld wrote:
On Thu, 17 Feb 2022 at 17:55, Lucas De Marchi wrote:
This was useful for early development of lmem, but it's not used
anymore, so remove it.
v2: Remove unneeded fields from struct intel_memory_region
Cc: Chris Wilson
Cc: Matthew
Signed-off-by: Paul Menzel
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 63a089992645..430e56583751 100644
--- a/drivers/gpu/drm/amd/amdgpu/am
On 2/18/22 19:38, Lucas Stach wrote:
[...]
@@ -502,8 +548,10 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk,
u32 pixelclock)
/*
* refclk * mul / (ext_pre_div * pre_div)
* should be in
Am 2022-02-18 um 21:34 schrieb Tom Rix:
On 2/18/22 10:35 AM, Felix Kuehling wrote:
Am 2022-02-18 um 12:39 schrieb t...@redhat.com:
From: Tom Rix
Clang static analysis reports this problem
kfd_chardev.c:2327:2: warning: 1st function call argument
is an uninitialized value
kvfree(bo_pr
Quoting Kuogee Hsieh (2022-02-17 13:36:28)
> Widebus feature will transmit two pixel data per pixel clock to interface.
> This feature now is required to be enabled to easy migrant to higher
s/migrant/migrate/?
> resolution applications in future. However since some legacy chipsets
s/in/in the/
Quoting Kuogee Hsieh (2022-02-17 13:36:27)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 0d315b4..0c22839 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -217,6
Quoting Kuogee Hsieh (2022-02-17 13:36:26)
> To improve code readability, this patch replace BIT(x) with
> correspond register bit define string
>
> Signed-off-by: Kuogee Hsieh
> ---
Reviewed-by: Stephen Boyd
Quoting Kuogee Hsieh (2022-02-17 13:36:25)
> The “DP timing” requires the active region to be defined in the
> bottom-right corner of the frame dimensions which is different
> with DSI. Therefore both display_h_end and display_v_end need
> to be adjusted accordingly. However current implementation
On 2/18/22 18:49, Lucas Stach wrote:
Am Freitag, dem 18.02.2022 um 02:00 +0100 schrieb Marek Vasut:
The TC358767/TC358867/TC9595 are all capable of operating either from
attached Xtal or from DSI clock lane clock. In case the later is used,
all I2C accesses will fail until the DSI clock lane is
On 2/18/22 10:35 AM, Felix Kuehling wrote:
Am 2022-02-18 um 12:39 schrieb t...@redhat.com:
From: Tom Rix
Clang static analysis reports this problem
kfd_chardev.c:2327:2: warning: 1st function call argument
is an uninitialized value
kvfree(bo_privs);
^~~~
If the copy_fro
On 19/02/2022 02:56, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-02-11 14:40:02)
In commit 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display
enable and disable") the DP driver received a drm_bridge instance, which
is always attached to the encoder as a root bridge. However it
On 2/18/22 18:34, Lucas Stach wrote:
Hi
[...]
drivers/gpu/drm/bridge/tc358767.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm/bridge/tc358767.c
index 522c2c4d8514f..01d11adee6c74 100644
--- a/drivers/gpu/
Quoting Maxime Ripard (2022-02-10 02:19:16)
> Hi Stephen,
>
> On Tue, Jan 25, 2022 at 03:15:39PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > This is a follow-up of the discussion here:
> > https://lore.kernel.org/linux-clk/20210319150355.xzw7ikwdaga2dwhv@gilmour/
> >
> > and here:
> > https://lo
Quoting Laurent Pinchart (2022-02-14 01:45:56)
> Hi Maxime and Stephen,
>
> We have recently posted a driver for the BCM2711 Unicam CSI-2 receiver
> (see [1]) which is a perfect candidate for this API, as it needs a
> minimum rate for the VPU clock. Any chance we can get this series merged
> ? :-)
On Sat, 19 Feb 2022 at 03:55, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-02-18 14:32:53)
> > On 19/02/2022 00:31, Kuogee Hsieh wrote:
> > >
> > > On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
> > >> There is little point in having both connector and root bridge
> > >> implementation in
Quoting Maxime Ripard (2022-01-25 06:15:44)
> index 266e8de3cb51..f365dac7be17 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -1005,6 +1005,17 @@ static inline struct clk *clk_get_optional(struct
> device *dev, const char *id)
> return clk;
> }
>
> +/**
> + * clk_dr
Quoting Maxime Ripard (2022-01-25 06:15:40)
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 6a98291350b6..2664aaab8068 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -2,6 +2,7 @@
> # common clock types
> obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-
On Sat, Feb 19, 2022 at 12:17:52AM +0530, Ramalingam C wrote:
> From: Ayaz A Siddiqui
>
> Xe-HP and latest devices support Flat CCS which reserved a portion of
> the device memory to store compression metadata, during the clearing of
> device memory buffer object we also need to clear the associa
On Sat, Jan 29, 2022 at 2:26 AM Linus Walleij wrote:
> On Mon, Jan 3, 2022 at 12:40 PM Linus Walleij
> wrote:
>
> > A code drop from Sony Mobile reveals that the ACX424 panels are
> > built around the Novatek NT35560 panel controllers so just bite
> > the bullet and rename the driver and all bas
Quoting Dmitry Baryshkov (2022-02-18 14:32:53)
> On 19/02/2022 00:31, Kuogee Hsieh wrote:
> >
> > On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
> >> There is little point in having both connector and root bridge
> >> implementation in the same driver. Move connector's functionality to the
> >> brid
On 2/14/2022 17:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
safe to call the GuC context clean
On Thu, Jan 06, 2022 at 04:55:36PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for i915.
Example of the
Hi,
On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
wrote:
>
> Add support in the DP driver to utilize the custom eDP panels
> from drm/panels.
>
> An eDP panel is always connected to the platform. So, the eDP
> connector can be reported as always connected. The display mode
> will be source
Quoting Dmitry Baryshkov (2022-02-11 14:40:04)
> It is possible to supply display-connector (bridge) to the DP interface,
> add support for parsing it too.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Add new .atomic_get_input_bus_cfgs callback into struct drm_bridge_funcs {}.
This is an extended version of .atomic_get_input_bus_fmts callback which
only returns list of bus formats supported by a bridge and provides no way
to e.g. limit clock frequency required between neighboring bridges.
The n
Pass the entire struct drm_bus_cfg {} to select_bus_fmt_recursive()
instead of only u32 out_bus_fmt which contains only the pixel format.
This would permit passing more bus format data around during the
bridge-to-bridge format negotiation.
Signed-off-by: Marek Vasut
Cc: Laurent Pinchart
Cc: Maxi
The bridge clock configuration should happen in atomic_enable
instead of mode_set callback, since that is where the current
state of the bridge is available. Move the clock configuration
into atomic_enable callback.
Signed-off-by: Marek Vasut
Cc: Laurent Pinchart
Cc: Maxime Ripard
Cc: Neil Arms
The bridge_state now contains clock frequency required by the next bridge.
This information is optional, since very few drivers pass this information
now. In case the required clock frequency is part of bridge state, use it
for the DSI bus clock frequency, otherwise fall back to the old guesswork.
The TC358767/TC358867/TC9595 are all capable of operating without RefClk
Xtal in DSI-to-DPI mode. In this mode of operation, the chip PLLs are fed
with clock derived from the DSI HS clock.
The SYSPLL is fed from DSI HS clock divided by 2*7 and the resulting clock
must match the allowed RefClk supp
Extend struct drm_bus_cfg with a clock field. This makes it possible for an
upstream bridge (further from scanout engine) to indicate to a downstream
bridge which frequency it expects on a link. This is particularly useful in
case of DSI bridges which derive their own internal clock from the DSI HS
Pass negotiated bridge state, which now optionally contains required DSI bus
clock, into dw_mipi_dsi_get_lane_mbps(). The dw_mipi_dsi_get_lane_mbps() is
a misnomer, it is also responsible for configuration of the bridge PLL and
thus also configuration of the clock the bridge outputs on the DSI bus.
This patch series attempts to address a problem of missing support for DSI
bridge-to-bridge or panel-to-bridge clock frequency negotiation. The problem
has two variants.
First, a DSI->to->x bridge derives its own internal clock from DSI HS clock,
but the DSI HS clock cannot be set to arbitrary val
On Fri, 18 Feb 2022 14:38:53 -0800, Lucas De Marchi wrote:
>
> The move to softpin in igt is ongoing and should land soon.
> Meanwhile, like was done for ADL and RKL, add an exception to allow
> running the igt display tests before that conversion is complete
> so we can unblock CI.
One example fa
Quoting Dmitry Baryshkov (2022-02-11 14:40:02)
> In commit 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display
> enable and disable") the DP driver received a drm_bridge instance, which
> is always attached to the encoder as a root bridge. However it conflicts
> with the panel_bridge sup
Quoting Dmitry Baryshkov (2022-02-11 14:40:03)
> Currently DP driver will allocate panel bridge for eDP panels. This
> supports only the following topology:
>
> - eDP encoder ⇒ eDP panel (wrapped using panel-bridge)
>
> Simplify this code to just check if there is any next bridge in the
> chain (be
Am 2022-02-18 um 18:08 schrieb David Yat Sin:
Fix for possible integer overflow when doing addition.
Reported-by: Dan Carpenter
Signed-off-by: David Yat Sin
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
1 file changed, 1 insertion(+), 1
Quoting Maxime Ripard (2022-01-25 06:15:41)
> The current core while setting the min and max rate properly in the
> clk_request structure will not make sure that the requested rate is
> within these boundaries, leaving it to each and every driver to make
> sure it is.
It would be good to describe
Fix for possible integer overflow when doing addition.
Reported-by: Dan Carpenter
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
b
The move to softpin in igt is ongoing and should land soon.
Meanwhile, like was done for ADL and RKL, add an exception to allow
running the igt display tests before that conversion is complete
so we can unblock CI.
Cc: Zbigniew Kempczynski
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Jason Ekstrand
C
Quoting Maxime Ripard (2022-01-25 06:15:42)
> The code in clk_set_rate_range() will, if the current rate is outside of
> the new range, will force it to the minimum or maximum. This is
> equivalent to using clamp, while being less readable. Let's switch to
> using clamp instead.
>
> Signed-off-by:
On Thu, Feb 17, 2022 at 05:40:51PM +0800, kernel test robot wrote:
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: b56d8d7bad86a9badc1d1b9ea2d1730fa1d3978b
commit: b56d8d7bad86a9badc1d1b9ea2d1730fa1d3978b [1/1] drm/i915: Add DG2 PCI IDs
config: x86_64-randconfig-a011
(h
On 19/02/2022 00:31, Kuogee Hsieh wrote:
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
There is little point in having both connector and root bridge
implementation in the same driver. Move connector's functionality to the
bridge to let next bridge in chain to override it.
Signed-off-by: Dmitr
+Daniele, +Rodrigo
On Tue, Feb 08, 2022 at 11:14:57PM -0800, Lucas De Marchi wrote:
On Mon, Feb 07, 2022 at 12:36:42PM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Cera
On Wed, Feb 16, 2022 at 09:41:41AM -0800, Lucas De Marchi wrote:
> Use the saved ads_map to prepare the golden context. One difference from
> the init context is that this function can be called before there is a
> gem object (and thus the guc->ads_map) to calculare the size of the
> golden context
On 19/02/2022 00:31, Kuogee Hsieh wrote:
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
There is little point in having both connector and root bridge
implementation in the same driver. Move connector's functionality to the
bridge to let next bridge in chain to override it.
Signed-off-by: Dmitr
On 19/02/2022 00:29, Abhinav Kumar wrote:
On 2/18/2022 1:21 PM, Dmitry Baryshkov wrote:
On 18/02/2022 23:46, Abhinav Kumar wrote:
On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
On 17/02/2022 09:33, Abhinav Kumar wrote:
On 2/16/2022 10:10 PM, Vinod Koul wrote:
On 16-02-22, 19:11, Abhina
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst case scenario is approximately
110 seconds. Rather than allowing the user to set higher values and
From: John Harrison
Compute workloads are inherantly not pre-emptible for long periods on
current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was disabled. This is undesirable with GuC
submission as it prevents per engine reset of hung contexts. Hence t
From: John Harrison
Compute workloads are inherently not pre-emptible on current hardware.
Thus the pre-emption timeout was disabled as a workaround to prevent
unwanted resets. Instead, the hang detection was left to the heartbeat
and its (longer) timeout. This is undesirable with GuC submission
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat will kick in eventually
and cause a reset of the hung engine.
However, this does not work well in G
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
There is little point in having both connector and root bridge
implementation in the same driver. Move connector's functionality to the
bridge to let next bridge in chain to override it.
Signed-off-by: Dmitry Baryshkov
This patch break primary (
On 19/02/2022 00:28, Kuogee Hsieh wrote:
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
Currently DP driver will allocate panel bridge for eDP panels. This
supports only the following topology:
- eDP encoder ⇒ eDP panel (wrapped using panel-bridge)
Simplify this code to just check if there is
On 2/18/2022 1:21 PM, Dmitry Baryshkov wrote:
On 18/02/2022 23:46, Abhinav Kumar wrote:
On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
On 17/02/2022 09:33, Abhinav Kumar wrote:
On 2/16/2022 10:10 PM, Vinod Koul wrote:
On 16-02-22, 19:11, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vi
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
It is possible to supply display-connector (bridge) to the DP interface,
add support for parsing it too.
Signed-off-by: Dmitry Baryshkov
Tested-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 19 ---
1 file changed,
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
Currently DP driver will allocate panel bridge for eDP panels. This
supports only the following topology:
- eDP encoder ⇒ eDP panel (wrapped using panel-bridge)
Simplify this code to just check if there is any next bridge in the
chain (be it a pan
On 18/02/2022 23:46, Abhinav Kumar wrote:
On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
On 17/02/2022 09:33, Abhinav Kumar wrote:
On 2/16/2022 10:10 PM, Vinod Koul wrote:
On 16-02-22, 19:11, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We cannot enable mode_3d when we
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
grep confirmed those are the only places we use the pool that wa
On Wed, Feb 16, 2022 at 09:41:47AM -0800, Lucas De Marchi wrote:
> Now we have the access to content of GuC ADS either using iosys_map
> API or using a temporary buffer. Remove guc->ads_blob as there shouldn't
> be updates using the bare pointer anymore.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
In commit 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display
enable and disable") the DP driver received a drm_bridge instance, which
is always attached to the encoder as a root bridge. However it conflicts
with the panel_bridge support
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query help
On Wed, Feb 16, 2022 at 09:41:46AM -0800, Lucas De Marchi wrote:
> Now that all the called functions from __guc_ads_init() are converted to
> use ads_map, stop using ads_blob in __guc_ads_init().
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Br
On Wed, Feb 16, 2022 at 09:41:45AM -0800, Lucas De Marchi wrote:
> Now that the regset list is prepared, convert guc_mmio_reg_state_init()
> to use iosys_map to copy the array to the final location and
> initialize additional fields in ads.reg_state_list.
>
> v2: Just use an offset instead of temp
On Wed, Feb 16, 2022 at 09:41:44AM -0800, Lucas De Marchi wrote:
> Use iosys_map to write the fields ads.capture_*.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Lucas De Marchi
Reviewed-b
On Wed, Feb 16, 2022 at 09:41:43AM -0800, Lucas De Marchi wrote:
> Use iosys_map to write the fields system_info.mapping_table[][].
> Since we already have the info_map around where needed, just use it
> instead of going through guc->ads_map.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Danie
On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
On 17/02/2022 09:33, Abhinav Kumar wrote:
On 2/16/2022 10:10 PM, Vinod Koul wrote:
On 16-02-22, 19:11, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration t
On Wed, Feb 16, 2022 at 09:41:42AM -0800, Lucas De Marchi wrote:
> In the other places in this function, guc->ads_map is being protected
> from access when it's not yet set. However the last check is actually
> about guc->ads_golden_ctxt_size been set before. These checks should
> always match as
On Wed, Feb 16, 2022 at 09:41:40AM -0800, Lucas De Marchi wrote:
> Use iosys_map_memset() to zero the private data as ADS may be either
> on system or IO memory.
>
> Cc: Matt Roper
> Cc: Thomas Hellström
> Cc: Daniel Vetter
> Cc: John Harrison
> Cc: Matthew Brost
> Cc: Daniele Ceraolo Spurio
18.02.2022 17:16, Dmitry Osipenko пишет:
> 18.02.2022 00:37, Thierry Reding пишет:
>> On Thu, Feb 17, 2022 at 11:02:53PM +0300, Dmitry Osipenko wrote:
>>> 17.02.2022 22:16, Thierry Reding пишет:
From: Thierry Reding
Hi all,
this is the userspace part of the kernel patches
Ramalingam C writes:
> On 2022-02-18 at 18:06:00 +, Robert Beckett wrote:
>>
>> If desired, we can make the wording clearer, maybe something like:
>>
>> "To keep things simple for userland, we mandate that any GTT mappings
>> must be aligned to 2MB. The kernel will internally pad them out t
Am 2022-02-18 um 14:26 schrieb Jason Gunthorpe:
On Fri, Feb 18, 2022 at 02:20:45PM -0500, Felix Kuehling wrote:
Am 2022-02-17 um 19:19 schrieb Jason Gunthorpe:
On Thu, Feb 17, 2022 at 04:12:20PM -0500, Felix Kuehling wrote:
I'm thinking of a more theoretical approach: Instead of auditing all
On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote:
Add a function that returns whether the requested CTL is active or not:
this will be used in a later commit to fix command mode panel issues.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/dr
On Fri, Feb 18, 2022 at 02:20:45PM -0500, Felix Kuehling wrote:
> Am 2022-02-17 um 19:19 schrieb Jason Gunthorpe:
> > On Thu, Feb 17, 2022 at 04:12:20PM -0500, Felix Kuehling wrote:
> >
> > > I'm thinking of a more theoretical approach: Instead of auditing all
> > > users,
> > > I'd ask, what are
Am 2022-02-17 um 19:19 schrieb Jason Gunthorpe:
On Thu, Feb 17, 2022 at 04:12:20PM -0500, Felix Kuehling wrote:
I'm thinking of a more theoretical approach: Instead of auditing all users,
I'd ask, what are the invariants that a vm_normal_page should have. Then
check, whether our DEVICE_COHERENT
On 2/18/2022 10:47 AM, Ramalingam C wrote:
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
Just a note here. To enable the dg2 with basic support sooner on CI we
have taken a subset of this series separtely at
https://patchwork.freedesktop.org/series/100419/
Remaining patches will be pursued on top the above series. Thanks for
the review comments. We will fix them working with reviewers
On 2022-02-18 at 18:06:00 +, Robert Beckett wrote:
>
>
> On 18/02/2022 13:47, Ramalingam C wrote:
> > On 2022-02-17 at 20:57:35 -0800, Jordan Justen wrote:
> > > Robert Beckett writes:
> > >
> > > > From: Matthew Auld
> > > >
> > > > On discrete platforms like DG2, we need to support a mi
From: "Souptick Joarder (HPE)"
Kernel test robot reported warning ->
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2129:2: warning: Undefined
or garbage value returned to caller [clang-analyzer-core.
uninitialized.UndefReturn]
Initialize r inside amdgpu_fill_buffer().
Reported-by: kernel test robot
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Ad
From: CQ Tang
Platforms of XeHP and beyond support 3D surface (buffer) compression and
various compression formats. This is accomplished by an additional
compression control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
v4: Kdoc modification.
v3: fix typos and less emphasis
v2: Fixed su
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
From: Robert Beckett
add test to check handling of misaligned offsets and sizes
v4:
* remove spurious blank lines
* explicitly cast intel_region_id to intel_memory_type in misaligned_pin
Reported-by: kernel test robot
v6:
* use NEEDS_COMPACT_PT instead of hard coding for
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
From: Matthew Auld
This is all kinds of awkward since we now have to contend with using 64K
GTT pages when mapping anything in LMEM(including the page-tables
themselves).
v2(Ram)
- Document the ppGTT layout and add a better description for the
different windows.
Signed-off-by: Matthew Aul
From: Matthew Auld
On some platforms we have alignment restrictions when accessing LMEM
from the GTT. In the next few patches we need to be able to modify the
page-tables directly via the GTT itself.
Suggested-by: Ramalingam C
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
From: Matthew Auld
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
Reviewed
From: Matthew Auld
discrete cards optimise 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no long
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
ICP/TGP
Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.
With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.
v6:
* minor doc formatting
S
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Si
From: Jouni Högander
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E.
The PORT_TC1 port is not yet enabled properly in the driver, but
intel_phy_snps.c is relying on intel_phy_is_snps() to filter out
unavailable phys. That function was already considering the last phy as
availa
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/g
Enabling the Dg2 on drm/i915.
This series adds support for 64k pagesize and documents the uapi
impacts. And also adds basic flat-ccs enabling patches to
support the local memory initialization and object creation. Kdoc is
added to document the Flat-ccs support.
Flat-ccs modifiers will be enabled
Am Freitag, dem 18.02.2022 um 02:00 +0100 schrieb Marek Vasut:
> The TC358767/TC358867/TC9595 are all capable of operating in multiple
> modes, DPI-to-(e)DP, DSI-to-(e)DP, DSI-to-DPI. Add support for the
> DSI-to-DPI mode.
>
> This requires skipping most of the (e)DP initialization code, which is
Am 2022-02-18 um 12:39 schrieb t...@redhat.com:
From: Tom Rix
Clang static analysis reports this problem
kfd_chardev.c:2327:2: warning: 1st function call argument
is an uninitialized value
kvfree(bo_privs);
^~~~
If the copy_from_users(bo_buckets, ...) fails, there is a jum
On Fri, Feb 18, 2022 at 11:22:41AM +, Matthew Auld wrote:
We already completed the steps for this.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
I was indeed wondering why
Am Freitag, dem 18.02.2022 um 02:00 +0100 schrieb Marek Vasut:
> The tc_set_video_mode() sets up both common and (e)DP video mode settings of
> the bridge chip. Split the function into tc_set_common_video_mode() to set
> the common settings and tc_set_edp_video_mode() to set the (e)DP specific
> se
Hi Dave, Daniel,
More new stuff for 5.18.
The following changes since commit b9c7babe2c2e37a50aa42401b38d597ea78f506e:
Backmerge tag 'v5.17-rc4' of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
(2022-02-14 10:52:27 +1000)
are available in the Git repository at:
Am Freitag, dem 18.02.2022 um 02:00 +0100 schrieb Marek Vasut:
> The TC358767/TC358867/TC9595 are all capable of operating in multiple
> modes, DPI-to-(e)DP, DSI-to-(e)DP, DSI-to-DPI. Only the first mode is
> currently supported. It is possible to find out the mode in which the
> bridge should be o
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