[AMD Official Use Only]
ttm_range_man_init/fini are exported. Someone else might use it by find_symbol.
I just want to not break things.
Developer usually compile the whole kernel. So add a checked version of
ttm_range_man_init/fini by the wrappers.
发件人:
Am 13.09.21 um 05:36 schrieb xinhui pan:
Allow TTM know if vendor set new ttm mananger out of bounds by adding
build_bug_on.
I really like the part in the inline functions, but the wrappers around
the ttm_range_man_init/fini look a bit awkward of hand.
Christian.
Signed-off-by: xinhui
W dniu 10.09.2021 o 12:11, Maxime Ripard pisze:
> Interactions between bridges, panels, MIPI-DSI host and the component
> framework are not trivial and can lead to probing issues when
> implementing a display driver. Let's document the various cases we need
> too consider, and the solution to sup
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
>
> Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp:
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
>
> Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/edp:
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
>
> Subject: [PATCH v2 4/6] drm/edid: parse the Displa
Well it will crash later on when accessing the invalid offset, so not
much gained.
But either way works for me.
Christian.
Am 13.09.21 um 04:35 schrieb Chen, Guchun:
[Public]
Thanks for your suggestion, Robin. Do you agree with this as well, Christian
and Xinhui?
Regards,
Guchun
-Orig
On 10/09/21 10:21 pm, Rob Herring wrote:
> 'enum' is equivalent to 'oneOf' with a list of 'const' entries, but 'enum'
> is more concise and yields better error messages.
>
> Fix a couple more cases which have appeared.
>
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: Mark Brown
> Cc: Wim Van Sebroeck
Hello,
When using Healer to fuzz the Linux kernel, the following crash was triggered.
HEAD commit: ac08b1c68d1b Merge tag 'pci-v5.15-changes'
git tree: upstream
console output:
https://drive.google.com/file/d/1Vvyiebkb1BAbgnM8QXg4XeotLYE7Xrk6/view?usp=sharing
kernel config:
https://drive.google.
Hi Adam,
On Sonntag, 12. September 2021 23:29:35 CEST Adam Borowski wrote:
> Signed-off-by: Adam Borowski
> ---
> With Linus suddenly loving -Werror, let's get clean.
>
> drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/rockchip
Am 11.09.21 um 08:07 schrieb Thomas Hellström:
On Fri, 2021-09-10 at 19:03 +0200, Christian König wrote:
Am 10.09.21 um 17:30 schrieb Thomas Hellström:
On Fri, 2021-09-10 at 16:40 +0200, Christian König wrote:
Am 10.09.21 um 15:15 schrieb Thomas Hellström:
Both the provider (resource manager)
On 9/10/2021 11:04 PM, Caleb Connolly wrote:
On 10/09/2021 18:18, Rob Clark wrote:
On Tue, Sep 7, 2021 at 7:20 PM Bjorn Andersson
wrote:
On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote:
On 8/9/2021 9:48 PM, Caleb Connolly wrote:
On 09/08/2021 17:12, Rob Clark wrote:
On Mon, Aug 9,
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
>
> Subject: [PATCH v2 3/6] drm/edid: abstract OUI con
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
>
> Subject: [Intel-gfx] [PATCH v2 2/6] drm/displayid:
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
>
> Subject: [PATCH v2 1/6] drm/displayid: re-align da
Allow TTM know if vendor set new ttm mananger out of bounds by adding
build_bug_on.
Signed-off-by: xinhui pan
---
drivers/gpu/drm/ttm/ttm_range_manager.c | 2 ++
include/drm/ttm/ttm_device.h| 3 +++
include/drm/ttm/ttm_range_manager.h | 10 ++
3 files changed, 15 insert
[Public]
Thanks for your suggestion, Robin. Do you agree with this as well, Christian
and Xinhui?
Regards,
Guchun
-Original Message-
From: Robin Murphy
Sent: Saturday, September 11, 2021 2:25 AM
To: Chen, Guchun ; amd-...@lists.freedesktop.org;
dri-devel@lists.freedesktop.org; Koenig
Signed-off-by: Adam Borowski
---
With Linus suddenly loving -Werror, let's get clean.
drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index 8ab3247dbc4a..bee0f2d2a9be 10
A subfeature of a built-in can't depend on a module.
Signed-off-by: Adam Borowski
---
drivers/gpu/drm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index cea777ae7fb9..75a5a9359d4b 100644
--- a/drivers/gpu/drm/Kconfi
MPE, VI, EPP and ISP were never used and we don't have drivers for them.
Since these modules are enabled by default in a device-tree, a device is
created for them, blocking voltage scaling because there is no driver to
bind, and thus, state of PMC driver is never synced. Disable them.
Signed-off-b
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by:
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry O
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 1 +
arch/arm/boot/dts/tegra
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
.../tegra30-asus-nexus7-grouper-common.dtsi |1 +
arch/arm/boot/dts/tegra30-beav
All device drivers got runtime PM and OPP support. Flip the core domain
support status for Tegra20 and Tegra30 SoCs.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.
CORE power domain uses name of device-tree node, which is inconsistent with
the names of PMC domains. Set the name to "core" to make it consistent.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/pmc
Depending on hardware version, Tegra SoC may require a higher voltages
during resume from system suspend, otherwise hardware will crash. Set
SoC voltages to a nominal levels during suspend.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/regulators-tegra20.c | 99
driv
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 32 ++
drivers/soc/tegra/fuse/fuse-tegra20.c | 33 +++
Currently driver supports legacy power domain API, this patch adds generic
power domain support. This allows us to utilize a modern GENPD API for
newer device-trees.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-b
The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 25 +
drivers/soc/tegra/fuse/fuse.h | 1 +
2 files changed, 26 inserti
Document new OPP table and power domain properties of the video decoder
hardware.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/
The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
performance
The NAND on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now NAND must be resumed using
runtime PM API in order to initialize the NAND power state. Add runtime PM
and OPP support to the NAND driver.
Acked-by: Miquel Raynal
Signed-off-by: Dmit
Convert NVIDIA Tegra video decoder binding to schema.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../bindings/media/nvidia,tegra-vde.txt | 64 ---
.../bindings/media/nvidia,tegra-vde.yaml | 107 ++
2 files changed, 107 insertions(+), 64 delet
The SDHCI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SDHCI must be resumed using
runtime PM API in order to initialize the SDHCI power state. The SDHCI
clock rate must be changed using OPP API that will reconfigure the power
domain per
The SPI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SPI driver must use OPP
API for driving the controller's clock rate because OPP API takes care
of reconfiguring the domain's performance state in accordance to the
rate. Add OPP suppor
The GMI bus on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now GMI must be resumed using
runtime PM API in order to initialize the GMI power state. Add runtime PM
and OPP support to the GMI driver.
Signed-off-by: Dmitry Osipenko
---
drivers
The Tegra USB controller belongs to the core power domain and we're going
to enable GENPD support for the core domain. Now USB controller must be
resumed using runtime PM API in order to initialize the USB power state.
We already support runtime PM for the CI device, but CI's PM is separated
from t
Add runtime power management and support generic power domains.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 388 +++
Hardware must be stopped before system is suspended. Add suspend-resume
callbacks.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/vic.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index c02010ff2b7f..359dd77f8b85 100
The HDMI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now HDMI driver must use
OPP API for driving the controller's clock rate because OPP API takes
care of reconfiguring the domain's performance state based on HDMI clock
rate. Add OPP suppo
Add runtime power management and support generic power domains.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 155 +++
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar #
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before client enters into suspend.
Tested-by
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handling and we're going to remove some of these paths in the future.
Tes
Memory Client should be blocked before hardware reset is asserted in order
to prevent memory corruption and hanging of memory controller.
Document Memory Client resets of Host1x, GR2D and GR3D hardware units.
Signed-off-by: Dmitry Osipenko
---
.../bindings/display/tegra/nvidia,tegra20-host1x.tx
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
a/Documenta
The Clock-and-Reset controller resides in a core power domain on NVIDIA
Tegra SoCs. In order to support voltage scaling of the core power domain,
we hook up DVFS-capable clocks to the core GENPD for managing of the
GENPD's performance state based on the clock changes.
Some clocks don't have any s
Previously we assumed that devm_tegra_core_dev_init_opp_table() will
be used only by drivers that will always have device with OPP table,
but this is not true anymore. For example now Tegra30 will have OPP table
for PWM, but Tegra20 not and both use the same driver. Hence let's not
print the error
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to t
Disable PMC state syncing in order to ensure that we won't break older
kernels once device-trees will be updated with the addition of the power
domains. This also allows to apply device-tree PM patches independently
from the driver patches.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pm
Only couple drivers need to get the -ENODEV error code and majority of
drivers need to explicitly initialize the performance state. Add new
common helper which sets up OPP table for these drivers.
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/common.h | 24
1 file
Elements of the 'names' array are not changed by the code, constify them
for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 6 +++---
include/linux/pm_opp.h | 8
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp/cor
This series adds runtime PM support to Tegra drivers and enables core
voltage scaling for Tegra20/30 SoCs, resolving overheating troubles.
All patches in this series are interdependent and should go via Tegra tree.
Changelog:
v11: - Added acks and r-b from Rob Herring, Mark Brown and Miquel Rayn
On Fri, Sep 10, 2021 at 03:09:39PM +0200, Maxime Ripard wrote:
> Display drivers so far need to have a lot of boilerplate to first
> retrieve either the panel or bridge that they are connected to using
> drm_of_find_panel_or_bridge(), and then either deal with each with ad-hoc
> functions or create
On Fri, Sep 10, 2021 at 03:09:41PM +0200, Maxime Ripard wrote:
> The new devm_drm_of_get_bridge removes most of the boilerplate we
> have to deal with. Let's switch to it.
>
> Signed-off-by: Maxime Ripard
With the includes updated:
Acked-by: Sam Ravnborg
Sam
> ---
> drivers/gpu/drm/
On Fri, Sep 10, 2021 at 03:09:40PM +0200, Maxime Ripard wrote:
> The new devm_drm_of_get_bridge removes most of the boilerplate we
> have to deal with. Let's switch to it.
>
> Signed-off-by: Maxime Ripard
Acked-by: Sam Ravnborg
> ---
> drivers/gpu/drm/vc4/vc4_dpi.c | 15 ---
> 1 fil
Hi Maxime,
On Fri, Sep 10, 2021 at 03:09:39PM +0200, Maxime Ripard wrote:
> Display drivers so far need to have a lot of boilerplate to first
> retrieve either the panel or bridge that they are connected to using
> drm_of_find_panel_or_bridge(), and then either deal with each with ad-hoc
> function
On Sun, 12 Sept 2021 at 23:55, Greg Kroah-Hartman
wrote:
>
> On Fri, Sep 10, 2021 at 06:10:27PM +0200, Daniel Vetter wrote:
> > Forgot to add dri-devel.
> >
> > On Fri, Sep 10, 2021 at 6:09 PM Daniel Vetter
> > wrote:
> > >
> > > On Fri, Sep 10, 2021 at 9:58 AM Greg Kroah-Hartman
> > > wrote:
>
https://bugzilla.kernel.org/show_bug.cgi?id=214375
Bug ID: 214375
Summary: 5.14 Regression: Null pointer dereference in
radeon_agp_head_init
Product: Drivers
Version: 2.5
Kernel Version: 5.14.2
Hardware: All
From: Tomer Tayar
Implement the calls to the dma-buf kernel api to create a dma-buf
object backed by FD.
We block the option to mmap the DMA-BUF object because we don't support
DIRECT_IO and implicit P2P. We only implement support for explicit P2P
through importing the FD of the DMA-BUF.
In the
User process might want to share the device memory with another
driver/device, and to allow it to access it over PCIe (P2P).
To enable this, we utilize the dma-buf mechanism and add a dma-buf
exporter support, so the other driver can import the device memory and
access it.
The device memory is al
Hi,
Re-sending this patch-set following the release of our user-space TPC
compiler and runtime library.
I would appreciate a review on this.
Thanks,
Oded
Oded Gabbay (1):
habanalabs: define uAPI to export FD for DMA-BUF
Tomer Tayar (1):
habanalabs: add support for dma-buf exporter
drivers
Thanks for the fixup and the quick review!
> > > - move drivers/misc/habanalabs under drivers/gpu/habanalabs and
> > > review/discussions on dri-devel
>
> Wait, why move into gpu? Are we going to do that for all hardware
> accelerators that we currently have in the kernel tree?
>
> These things are not GPUs in the sense of them being "do s
On Fri, Sep 10, 2021 at 06:10:27PM +0200, Daniel Vetter wrote:
> Forgot to add dri-devel.
>
> On Fri, Sep 10, 2021 at 6:09 PM Daniel Vetter wrote:
> >
> > On Fri, Sep 10, 2021 at 9:58 AM Greg Kroah-Hartman
> > wrote:
> > > On Fri, Sep 10, 2021 at 10:26:56AM +0300, Oded Gabbay wrote:
> > > > Hi G
Hi,
On 9/9/21 5:50 PM, Thierry Reding wrote:
> On Sun, Sep 05, 2021 at 03:05:01PM +0200, Hans de Goede wrote:
>> The Chuwi HiBook uses a panel which has been mounted
>> 90 degrees rotated. Add a quirk for this.
>>
>> Signed-off-by: Hans de Goede
>> ---
>> drivers/gpu/drm/drm_panel_orientation_qu
Hi,
On 9/11/21 8:54 PM, Sam Ravnborg wrote:
> Hi Simon,
> On Sat, Sep 11, 2021 at 10:24:40AM +, Simon Ser wrote:
>> Valve's Steam Deck has a 800x1280 LCD screen.
>>
>> Signed-off-by: Simon Ser
>> Cc: Jared Baldridge
>> Cc: Emil Velikov
>> Cc: Daniel Vetter
>> Cc: Hans de Goede
>
>
> The
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