On Mon, Jul 26, 2021 at 06:13:10AM -0400, Rodrigo Vivi wrote:
On Fri, Jul 23, 2021 at 05:11:14PM -0700, Lucas De Marchi wrote:
The numbers of scalers and sprites depend on the display version, so use
it instead of GRAPHICS_VER. We were mixing both, which let me confused
while removing CNL and GR
Am 27.07.21 um 02:52 schrieb Rodrigo Siqueira:
DC invokes DC_FPU_START/END in multiple parts of the code; this can
create a situation where we invoke this FPU operation in a nested way or
exit too early. For avoiding this situation, this commit adds a
mechanism where dc_fpu_begin/end manages the
Am 27.07.21 um 02:52 schrieb Rodrigo Siqueira:
The display core files rely on FPU, which requires to be compiled with
special flags. Ideally, we don't want these FPU operations spread around
the DC code; nevertheless, it happens in the current source. This commit
introduces a new directory inside
On Sat, Jul 24, 2021 at 11:12:07AM -0700, Matt Roper wrote:
On Fri, Jul 23, 2021 at 05:10:48PM -0700, Lucas De Marchi wrote:
The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. Remove code and rename
functions/macros accordingly.
Signed
On Tue, Jul 27, 2021 at 01:53:13AM +, tcs_kernel(腾讯云内核开发者) wrote:
> yres and vyres can be controlled by user mode paramaters, and cause p->vrows
> to become a negative value. While this value be passed to real_y function,
> the ypos will be out of screen range.
> This is an out-of-bounds writ
Remove including that don't need it.
Signed-off-by: Cai Huoqing
---
drivers/gpu/drm/pl111/pl111_display.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/pl111/pl111_display.c
b/drivers/gpu/drm/pl111/pl111_display.c
index b5a885
/sysfb_efi.c |2 ++
1 file changed, 2 insertions(+)
--- linext-20210726.orig/drivers/firmware/efi/sysfb_efi.c
+++ linext-20210726/drivers/firmware/efi/sysfb_efi.c
@@ -332,6 +332,7 @@ static const struct fwnode_operations ef
.add_links = efifb_add_links,
};
+#ifdef CONFIG_EFI
static struct
On Wed 07 Jul 11:01 PDT 2021, Rob Clark wrote:
> From: Rob Clark
>
> It turns out that when the display is enabled by the bootloader, we can
> get some transient iommu faults from the display. Which doesn't go over
> too well when we install a fault handler that is gpu specific. To avoid
> thi
Patch says it all. Seeing a failure in CI [1] and locally on certain TGL
machines with GuC submission enabled. Let's fix this so we can enable CI
on TGL with GuC submission.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/92984/#rev4
Matthew Brost (1):
drm/i915/selft
Like in the case of several other selftests, generating lots of requests
in a loop takes a bit longer with GuC submission. Increase a timeout in
i915_gem_contexts selftest to take this into account.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
1
Hi Enric,
On Mon, 2021-07-26 at 12:08 +0200, Enric Balletbo Serra wrote:
> Hi Jason,
>
> Missatge de Jason-JH Lin del dia dl., 26
> de jul. 2021 a les 9:02:
> >
> > On Fri, 2021-07-23 at 13:13 +0200, Enric Balletbo Serra wrote:
> > > Hi Jason,
> > >
> > > Thank you for your patch.
> > >
> > >
From: Rodrigo Vivi
GuC contains a consolidated table with a bunch of information about the
current device.
Previously, this information was spread and hardcoded to all the components
including GuC, i915 and various UMDs. The goal here is to consolidate
the data into GuC in a way that all interes
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be retrieved from the GuC.
Test-with: 20210727002812.43469-2-john.c.harri...@intel.com
UMD: https://github.com/intel/comput
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
yres and vyres can be controlled by user mode paramaters, and cause p->vrows to
become a negative value. While this value be passed to real_y function, the
ypos will be out of screen range.
This is an out-of-bounds write bug.
I think updatescrollmode is the right place to validate values supplied
Many of the DSI flags have names opposite to their actual effects,
e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
be disabled. Fix this by including _NO_ in the flag names, e.g.
MIPI_DSI_MODE_NO_EOT_PACKET.
Signed-off-by: Nicolas Boichat
Reviewed-by: Linus Walleij
Reviewed-by
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
From: Rodrigo Vivi
GuC contains a consolidated table with a bunch of information about the
current device.
Previously, this information was spread and hardcoded to all the components
including GuC, i915 and various UMDs. The goal here is to consolidate
the data into GuC in a way that all interes
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be retrieved from the GuC.
Test-with: 20210727002812.43469-2-john.c.harri...@intel.com
UMD: https://github.com/intel/comput
DC invokes DC_FPU_START/END in multiple parts of the code; this can
create a situation where we invoke this FPU operation in a nested way or
exit too early. For avoiding this situation, this commit adds a
mechanism where dc_fpu_begin/end manages the access to
kernel_fpu_begin/end.
Change since V3:
The display core files rely on FPU, which requires to be compiled with
special flags. Ideally, we don't want these FPU operations spread around
the DC code; nevertheless, it happens in the current source. This commit
introduces a new directory inside DML for centralizing shared DCN
functions that r
To fully isolate FPU operations in a single place, we must avoid
situations where compilers spill FP values to registers due to FP enable
in a specific C file. Note that even if we isolate all FPU functions in
a single file and call its interface from other files, the compiler
might enable the use
DC invokes DC_FPU_START/END in multiple parts of the code; this can
create a situation where we invoke this FPU operation in a nested way or
exit too early. For avoiding this situation, this commit adds a
mechanism where dc_fpu_begin/end manages the access to
kernel_fpu_begin/end.
Change since V3:
Hi,
In the display core, we utilize floats and doubles units for calculating
modesetting parameters. One side effect of our approach to use double-precision
is the fact that we spread multiple FPU access across our driver, which means
that we can accidentally clobber user space FPU state.
# Chal
On 07/21, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds a new module parameter called drm.trace which accepts
> the same mask as drm.debug. When a debug category is enabled, log
> messages will be put in a new tracefs instance called drm for
> consumption.
>
> Using the new tracefs inst
Thank you Stephen for reviewing.
On 2021-07-26 14:31, Stephen Boyd wrote:
Quoting maitreye (2021-07-26 10:36:26)
@@ -509,6 +515,7 @@ static int dp_display_usbpd_attention_cb(struct
device *dev)
DRM_ERROR("invalid dev\n");
return -EINVAL;
}
+ DRM_DE
From: Maitreyee Rao
Add trace points across the MSM DP driver to help debug
interop issues.
Changes in v2:
- Got rid of redundant log messages.
- Added %#x instead of 0x%x wherever required.
- Got rid of __func__ calls in debug messages.
- Added newline wherever missing.
Changes in v3:
- G
Quoting Akhil P Oommen (2021-07-24 10:29:00)
> Add the necessary dt nodes for gpu support in sc7280.
>
> Signed-off-by: Akhil P Oommen
> ---
> This patch has dependency on the GPUCC bindings patch here:
> https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-t..
From: John Harrison
It is impossible to seal all race conditions of resets occurring
concurrent to other operations. At least, not without introducing
excesive mutex locking. Instead, don't complain if it occurs. In
particular, don't complain if trying to send a H2G during a reset.
Whatever the H
From: John Harrison
In the case of a full GPU reset (e.g. because GuC has died or because
GuC's hang detection has been disabled), the driver can't rely on GuC
reporting the guilty context. Instead, the driver needs to scan all
active contexts and find one that is currently executing, as per the
From: Daniele Ceraolo Spurio
Unblock GuC submission on Gen11+ platforms.
v2:
(Martin Peres / John H)
- Delete debug message when GuC is disabled by default on certain
platforms
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
Reviewed-
Requests may take slightly longer with GuC submission, let's increase
the timeouts in live_requests.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.
From: Rahul Kumar Singh
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
Signed-off-by: Matth
We receive notification of an engine reset from GuC at its
completion. Meaning GuC has potentially cleared any HW state
we may have been interested in capturing. GuC resumes scheduling
on the engine post-reset, as the resets are meant to be transparent,
further muddling our error state.
There is o
From: John Harrison
The media watchdog mechanism involves GuC doing a silent reset and
continue of the hung context. This requires the i915 driver provide a
golden context to GuC in the ADS.
v2:
(Matthew Brost):
- Fix memory corruption in shmem_read
(John H)
- Use locals rather than define
The new GuC interface introduces an MMIO H2G command,
INTEL_GUC_ACTION_RESET_CLIENT, which is used to implement suspend. This
MMIO tears down any active contexts generating a context reset G2H CTB
for each. Once that step completes the GuC tears down the CTB
channels. It is safe to suspend once thi
If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 62 +++
Hold a reference to the intel_context over life of an i915_request.
Without this an i915_request can exist after the context has been
destroyed (e.g. request retired, context closed, but user space holds a
reference to the request from an out fence). In the case of GuC
submission + virtual engine,
From: John Harrison
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Conversely, one of the tests specifically sends hanging batches to the
engines but wants
From: John Harrison
There are many ways in which the hangcheck selftest can fail. Very few
of them actually printed an error message to say what happened. So,
fill in the missing messages.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: Daniele Ceraolo
Implement a simple static mapping algorithm of the i915 priority levels
(int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as
follows:
i915 level < 0 -> GuC low level (3)
i915 level == 0 -> GuC normal level (2)
i915 level < INT_MAX-> GuC high level(1)
i9
From: John Harrison
Use the official driver default scheduling policies for configuring
the GuC scheduler rather than a bunch of hardcoded values.
v2:
(Matthew Brost)
- Move I915_ENGINE_WANT_FORCED_PREEMPTION to later patch
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed
From: Rahul Kumar Singh
When GuC submission is enabled, the GuC controls engine resets. Rather
than explicitly triggering a reset, the driver must submit a hanging
context to GuC and wait for the reset to occur.
Signed-off-by: Rahul Kumar Singh
Signed-off-by: John Harrison
Signed-off-by: Matth
From: John Harrison
The serial number tracking of engines happens at the backend of
request submission and was expecting to only be given physical
engines. However, in GuC submission mode, the decomposition of virtual
to physical engines does not happen in i915. Instead, requests are
submitted to
GuC will notify the driver, via G2H, if it fails to
reset an engine. We recover by resorting to a full GPU
reset.
v2:
(John Harrison):
- s/drm_dbg/drm_err
Signed-off-by: Matthew Brost
Signed-off-by: Fernando Pacheco
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h
From: John Harrison
Changing the reset module parameter has no effect on a running GuC.
The corresponding entry in the ADS must be updated and then the GuC
informed via a Host2GuC message.
The new debugfs interface to module parameters allows this to happen.
However, connecting the parameter dat
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This implementation makes use of fence while there are likely simplier
options. A fence was chosen because of another feature coming soon
which requires a user to block on a context u
From: John Harrison
Clear the 'disable resets' flag to allow GuC to reset hung contexts
(detected via pre-emption timeout).
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +--
1 file changed, 1 insertion
The GuC can implement execution qunatums, detect hung contexts and
other such things but it requires the timer expired interrupt to do so.
Signed-off-by: Matthew Brost
CC: John Harrison
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4
1 file changed, 4 insertions(+)
From: John Harrison
Added the scheduling policy parameters to the 'guc_info' debugfs state
dump.
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_a
From: John Harrison
Some testing environments and some heavier tests are slower than
previous limits allowed for. For example, it can take multiple seconds
for the 'context has been reset' notification handler to reach the
'kill the requests' code in the 'active' version of the 'reset
engines' te
From: John Harrison
The driver must provide GuC with a list of mmio registers
that should be saved/restored during a GuC-based engine reset.
Unfortunately, the list must be dynamically allocated as its size is
variable. That means the driver must generate the list twice - once to
work out the siz
When using GuC submission, if a context gets banned disable scheduling
and mark all inflight requests as complete.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h
GuC will issue a reset on detecting an engine hang and will notify
the driver via a G2H message. The driver will service the notification
by resetting the guilty context to a simple state or banning it
completely.
v2:
(John Harrison)
- Move msg[0] lookup after length check
v3:
(John Harrison)
Add disable GuC interrupts to intel_guc_sanitize(). Part of this
requires moving the guc_*_interrupt wrapper function into header file
intel_guc.h.
Signed-off-by: Matthew Brost
Cc: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 16 +++
This is required to allow backend specific cleanup
v2:
(John H)
- Rework commit message
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_scheduler.c | 3 ++-
drivers/gpu/drm/i915/i915_scheduler.h | 4 +---
drivers/gpu/drm/i915/i915_scheduler_
Move active request tracking to a backend vfunc rather than assuming all
backends want to do this in the manner. In the of case execlists /
ring submission the tracking is on the physical engine while with GuC
submission it is on the context.
Signed-off-by: Matthew Brost
Reviewed-by: John Harriso
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to that of all the siblings.
v2: Update to work wit
Reset implementation for new GuC interface. This is the legacy reset
implementation which is called when the i915 owns the engine hang check.
Future patches will offload the engine hang check to GuC but we will
continue to maintain this legacy path as a fallback and this code path
is also required
With GuC virtual engines the physical engine which a request executes
and completes on isn't known to the i915. Therefore we can't attach a
request to a physical engines breadcrumbs. To work around this we create
a single breadcrumbs per engine class when using GuC submission and
direct all physica
The remaining patches for basic GuC submission [1]. Need 1 more RB and
CI results to get this merged.
v2:
(Checkpatch)
- Fix checkpatch warning (1 remaining overrulled)
(Daniele)
- Use an outer lock in guc_context_block / unblock
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesk
Update the bonding extension to return -ENODEV when using GuC submission
as this extension fundamentally will not work with the GuC submission
interface.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
1 file changed, 5 insertio
Quoting Bjorn Andersson (2021-07-24 21:24:32)
> Functions in the DisplayPort code that relates to individual instances
> (encoders) are passed both the struct msm_dp and the struct drm_encoder. But
> in a situation where multiple DP instances would exist this means that
> the caller need to resolve
Quoting Bjorn Andersson (2021-07-24 21:24:36)
> The sc8180x has 2 DP and 1 eDP controllers, add support for these to the
> DP driver.
>
> Link:
> https://lore.kernel.org/linux-arm-msm/20210511042043.592802-5-bjorn.anders...@linaro.org/
> Signed-off-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm
Quoting Bjorn Andersson (2021-07-24 21:24:35)
> The Qualcomm SC8180x has 2 DP controllers and 1 eDP controller, add
> compatibles for these to the msm/dp binding.
>
> Signed-off-by: Bjorn Andersson
> ---
Reviewed-by: Stephen Boyd
On Mon, Jul 26, 2021 at 4:34 PM Rob Clark wrote:
>
> From: Rob Clark
>
> Based on discussion from a previous series[1] to add a "boost" mechanism
> when, for example, vblank deadlines are missed. Instead of a boost
> callback, this approach adds a way to set a deadline on the fence, by
> which t
Quoting Bjorn Andersson (2021-07-24 21:24:33)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 59ffd6c8f41f..92b7646a1bb7 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -238,8 +251,11 @@ static i
From: Rob Clark
As the finished fence is the one that is exposed to userspace, and
therefore the one that other operations, like atomic update, would
block on, we need to propagate the deadline from from the finished
fence to the actual hw fence.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/sc
From: Rob Clark
For an atomic commit updating a single CRTC (ie. a pageflip) calculate
the next vblank time, and inform the fence(s) of that deadline.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_atomic_helper.c | 36 +
1 file changed, 36 insertions(+)
diff --g
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_vblank.c | 31 +++
include/drm/drm_vblank.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 3417e1ac7918..88c824c294dc 10064
From: Rob Clark
Add a way to hint to the fence signaler of an upcoming deadline, such as
vblank, which the fence waiter would prefer not to miss. This is to aid
the fence signaler in making power management decisions, like boosting
frequency as the deadline approaches and awareness of missing de
From: Rob Clark
Based on discussion from a previous series[1] to add a "boost" mechanism
when, for example, vblank deadlines are missed. Instead of a boost
callback, this approach adds a way to set a deadline on the fence, by
which the waiter would like to see the fence signalled.
I've not yet
On Mon, Jul 26, 2021 at 11:02:49PM +0200, Marek Vasut wrote:
> Decoder input LVDS format is a property of the decoder chip or even
> its strapping. Add DT property data-mapping the same way lvds-panel
> does, to define the LVDS data mapping.
>
> Signed-off-by: Marek Vasut
> Cc: Laurent Pinchart
On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:
> Remove DMC firmware for CNL.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/di
On Fri, Jul 23, 2021 at 05:11:07PM -0700, Lucas De Marchi wrote:
> CNL is the only platform with GRAPHICS_VER == 10. With its removal we
> don't need to handle that version anymore.
>
> Also we can now reduce the max number of slices: the call to
> intel_sseu_set_info() with the highest number of
eDP panels might need some power sequencing and backlight management,
so make it possible to associate a drm_panel with a DP instance and
prepare and enable the panel accordingly.
Signed-off-by: Bjorn Andersson
---
This solves my immediate problem on my 8cx laptops, of indirectly controlling
the
Quoting Bjorn Andersson (2021-07-24 21:24:31)
> As the Qualcomm DisplayPort driver only supports a single instance of
> the driver the commonly used struct dp_display is kept in a global
> variable. As we introduce additional instances this obviously doesn't
> work.
>
> Replace this with a combinat
On 7/22/2021 16:54, Matthew Brost wrote:
Reset implementation for new GuC interface. This is the legacy reset
implementation which is called when the i915 owns the engine hang check.
Future patches will offload the engine hang check to GuC but we will
continue to maintain this legacy path as a fa
On Mon, Jul 26, 2021 at 01:15:26AM +0300, Artjom Vejsel wrote:
> Add DT bindings for QiShenglong Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel.
>
> Signed-off-by: Artjom Vejsel
> ---
> .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff
On Mon, 26 Jul 2021 01:15:25 +0300, Artjom Vejsel wrote:
> Add vendor prefix for Shenzhen QiShenglong Industrialist Co., Ltd.
> QiShenglong is a Chinese manufacturer of handheld gaming consoles, most of
> which run (very old) versions of Linux.
> QiShenglong is known as Hamy.
>
> Signed-off-by: Ar
On Thu, Jul 15, 2021 at 10:36:51AM +0100, Tvrtko Ursulin wrote:
>
> On 24/06/2021 08:05, Matthew Brost wrote:
> > Reset implementation for new GuC interface. This is the legacy reset
> > implementation which is called when the i915 owns the engine hang check.
> > Future patches will offload the en
Quoting Kuogee Hsieh (2021-07-23 09:55:39)
> There is a scenario that dp cable is unplugged from DUT during system
> suspended will cause audio option state does not match real connection
> state. Fix this problem by Signaling audio plugged change with realtime
> connection status at dp_pm_resume(
On Thu, Jul 22, 2021 at 01:46:08PM +0100, Tvrtko Ursulin wrote:
>
> On 16/07/2021 21:16, Matthew Brost wrote:
> > With GuC virtual engines the physical engine which a request executes
> > and completes on isn't known to the i915. Therefore we can't attach a
> > request to a physical engines breadc
Hello Mark,
On 7/26/21 11:36 PM, Mark Brown wrote:
> Hi all,
>
> Today's -next fails to build an arm64 allnoconfig:
>
> aarch64-none-linux-gnu-ld: drivers/firmware/sysfb.o: in function `sysfb_init':
> sysfb.c:(.init.text+0xc): undefined reference to `screen_info'
> aarch64-none-linux-gnu-ld: dri
Hi all,
Today's -next fails to build an arm64 allnoconfig:
aarch64-none-linux-gnu-ld: drivers/firmware/sysfb.o: in function `sysfb_init':
sysfb.c:(.init.text+0xc): undefined reference to `screen_info'
aarch64-none-linux-gnu-ld: drivers/firmware/sysfb.o: relocation
R_AARCH64_ADR_PREL_PG_HI21 agai
Quoting maitreye (2021-07-26 10:36:26)
> @@ -509,6 +515,7 @@ static int dp_display_usbpd_attention_cb(struct device
> *dev)
> DRM_ERROR("invalid dev\n");
> return -EINVAL;
> }
> + DRM_DEBUG_DP("sink_request: %d\n", sink_request);
This one is bad. sink
On 07/25, Thomas Zimmermann wrote:
> Abstract the framebuffer details by mappings its BOs with a call
> to drm_gem_fb_vmap(). Unmap with drm_gem_fb_vunamp().
>
> Before, the output address with stored as raw pointer in the priv
> field of struct drm_writeback_job. Introduce the new type
> struct v
Decoder input LVDS format is a property of the decoder chip or even
its strapping. Handle data-mapping the same way lvds-panel does. In
case data-mapping is not present, do nothing, since there are still
legacy bindings which do not specify this property.
Signed-off-by: Marek Vasut
Cc: Laurent Pi
Decoder input LVDS format is a property of the decoder chip or even
its strapping. Add DT property data-mapping the same way lvds-panel
does, to define the LVDS data mapping.
Signed-off-by: Marek Vasut
Cc: Laurent Pinchart
Cc: Rob Herring
Cc: Sam Ravnborg
Cc: devicet...@vger.kernel.org
To: dri
Quoting Kuogee Hsieh (2021-07-23 09:55:39)
> There is a scenario that dp cable is unplugged from DUT during system
> suspended will cause audio option state does not match real connection
> state. Fix this problem by Signaling audio plugged change with realtime
> connection status at dp_pm_resume(
Quoting maitreye (2021-07-26 10:36:26)
> From: Maitreyee Rao
>
> Add trace points across the MSM DP driver to help debug
> interop issues.
>
> Changes in v2:
> - Got rid of redundant log messages.
> - Added %#x instead of 0x%x wherever required.
> - Got rid of __func__ calls in debug messages.
https://bugzilla.kernel.org/show_bug.cgi?id=205089
jes...@jnsn.dev changed:
What|Removed |Added
CC||jes...@jnsn.dev
--- Comment #14 from je
Decoder input LVDS format is a property of the decoder chip or even
its strapping. Handle data-mapping the same way lvds-panel does. In
case data-mapping is not present, do nothing, since there are still
legacy bindings which do not specify this property.
Signed-off-by: Marek Vasut
Cc: Laurent Pi
Decoder input LVDS format is a property of the decoder chip or even
its strapping. Add DT property data-mapping the same way lvds-panel
does, to define the LVDS data mapping.
Signed-off-by: Marek Vasut
Cc: Laurent Pinchart
Cc: Rob Herring
Cc: Sam Ravnborg
Cc: devicet...@vger.kernel.org
To: dri
Hi Nikita,
On Mon, Jul 26, 2021 at 04:59:52PM +0300, Nikita Shubin wrote:
> From: Alexander Sverdlin
>
> Use clk_prepare_enable()/clk_disable_unprepare() in preparation for switch
> to Common Clock Framework.
>
> Signed-off-by: Alexander Sverdlin
> Signed-off-by: Nikita Shubin
Thanks, applied
Hi Simon,
On Mon, Jul 26, 2021 at 07:49:06AM +, Simon Ser wrote:
> We already have logging for ADDFB2. Add some logging for RMFB as
> well.
>
> This can be handy when trying to find out why a CRTC gets magically
> disabled.
>
> v2: make log message more explicit, add log messages to
> drm_fr
On Tue, 27 Jul 2021 at 05:35, Christian König
wrote:
>
> Am 26.07.21 um 02:03 schrieb Dave Airlie:
> > [SNIP]
> >> But you know, normal human: Only equipped with one head and two hands
> >> and not cloneable.
> > I'm the same, but I'm not seeing where this problem happens at all, do
> > we have an
Hi Paul,
On Mon, Jul 26, 2021 at 10:02:08AM +0100, Paul Cercueil wrote:
> Hi Artjom,
>
> Le lun., juil. 26 2021 at 01:15:27 +0300, Artjom Vejsel
> a écrit :
> > The Gopher 2b LCD panel is used in Gopher 2b handhelds.
> > It's simple panel with NewVision NV3047 driver, but SPI lines are not
> > co
Hi Björn,
On Mon, Jul 26, 2021 at 10:32:59AM -0700, Bjorn Andersson wrote:
> Add bindings for the two AUO panels B133HAN05 and B140HAN06, both
> 1920x1080 panels with 16.7M colors, first being 13.3" and the latter
> 14.0".
>
> Signed-off-by: Bjorn Andersson
Thanks, both patches applied to drm-mi
In case there is a bridge connected to the LCDIF, use bus_format
from the bridge, otherwise behave as before and use bus_format
from the connector. This way, even if there are multiple bridges
in the display pipeline, the LCDIF will use the correct format.
Reviewed-by: Lucas Stach
Signed-off-by:
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