On Sat, Jul 17, 2021 at 10:52 PM Marek Vasut wrote:
>
> On 7/17/21 4:21 PM, Qiang Yu wrote:
> > On Sat, Jul 17, 2021 at 9:08 PM Marek Vasut wrote:
> >>
> >> On 7/17/21 2:34 PM, Qiang Yu wrote:
> >>> On Sat, Jul 17, 2021 at 2:20 AM Marek Vasut wrote:
>
> Instead of requesting two separa
Hi Dillon,
thanks for your patch!
On Fri, Jul 16, 2021 at 12:20 PM wrote:
> From: Dillon Min
>
> This driver combine tiny/ili9341.c mipi_dbi_interface driver
> with mipi_dpi_interface driver, can support ili9341 with serial
> mode or parallel rgb interface mode by register configuration.
>
> S
Hi Dillon,
thanks for your patch!
On Fri, Jul 16, 2021 at 12:20 PM wrote:
> From: Dillon Min
>
> Add documentation for "ilitek,ili9341" panel.
>
> Signed-off-by: Dillon Min
> + dc-gpios:
> +maxItems: 1
> +description: Display data/command selection (D/CX)
This is a DBI feature so m
Am Sonntag, 4. Juli 2021, 16:03:09 CEST schrieb Jagan Teki:
> Finding panel_or_bridge might vary based on associated
> DSI devices like DSI panel, bridge, and I2C based DSI
> bridge.
>
> 1. DSI panels and bridges will invoke the host attach
>from probe in order to find the panel_or_bridge.
>
Am Donnerstag, 24. Juni 2021, 11:55:02 CEST schrieb Thomas Zimmermann:
> Moving the driver-specific mmap code into a GEM object function allows
> for using DRM helpers for various mmap callbacks.
>
> The respective rockchip functions are being removed. The file_operations
> structure fops is now b
On Fri, Jul 16, 2021 at 01:41:18PM +1000, Dave Airlie wrote:
> Hi Linus,
>
> Regular rc2 fixes though a bit more than usual at rc2 stage, people
> must have been testing early or else some fixes from last week got a
> bit laggy. There is one larger change in the amd fixes to amalgamate
> some powe
From: Rob Clark
The drm/scheduler provides additional prioritization on top of that
provided by however many number of ringbuffers (each with their own
priority level) is supported on a given generation. Expose the
additional levels of priority to userspace and map the userspace
priority back to
From: Rob Clark
It is sufficient to serialize on the submit queue now.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem_submit.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
From: Rob Clark
In the next patch, we start having more than a single potential failure
reason.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem_submit.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/d
From: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/4
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_gem.c | 35 --
drivers/gpu/drm/msm/msm_gem.h | 24 -
drivers/gpu/drm/msm/msm_gem_submit.c | 14
From: Rob Clark
Previously the (non-fd) fence returned from submit ioctl was a raw
seqno, which is scoped to the ring. But from UABI standpoint, the
ioctls related to seqno fences all specify a submitqueue. We can
take advantage of that to replace the seqno fences with a cyclic idr
handle.
Thi
From: Rob Clark
Move all the locked/active/pinned state handling to msm_gem_submit.c.
In particular, for drm/scheduler, we'll need to do all this before
pushing the submit job to the scheduler. But while we're at it we can
get rid of the dupicate pin and refcnt.
Signed-off-by: Rob Clark
---
d
From: Rob Clark
No need for this to be split in two parts.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index e789f68
From: Rob Clark
Now that no one is using it, remove it.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_gem.c | 22 --
include/drm/drm_gem.h | 2 --
2 files changed, 24 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 9989425e9875
From: Rob Clark
No idea why we were still using this. It certainly hasn't been needed
for some time. So drop the pointless twin codepaths.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 +--
drivers/gpu/drm/m
From: Rob Clark
If we don't have a gpu, there is no need to create a submitqueue, which
lets us simplify the error handling and submitqueue creation.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_submitqueue.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff
From: Rob Clark
Fix a couple incorrect or misspelt comments, and add submitqueue doc
comment.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.h | 3 +--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 15 +++
drivers/gpu/drm/m
From: Rob Clark
Conversion to gpu_scheduler, and bonus removal of
drm_gem_object_put_locked()
Rob Clark (11):
drm/msm: Docs and misc cleanup
drm/msm: Small submitqueue creation cleanup
drm/msm: drop drm_gem_object_put_locked()
drm: Drop drm_gem_object_put_locked()
drm/msm/submit: Simpl
On 7/16/2021 5:14 PM, Felix Kuehling wrote:
Am 2021-07-16 um 11:07 a.m. schrieb Theodore Y. Ts'o:
On Wed, Jun 23, 2021 at 05:49:55PM -0400, Felix Kuehling wrote:
I can think of two ways to test the changes for MEMORY_DEVICE_GENERIC in
this patch series in a way that is reproducible without sp
On 7/10/2021 11:15 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into slpc structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. Thes
Add two more parameters to set spm_addr_dev0 & spm_addr_dev1
addresses. These two parameters configure the start SP
addresses for each device in test_hmm driver.
Consequently, this configures zone device type as generic.
Signed-off-by: Alex Sierra
---
tools/testing/selftests/vm/test_hmm.sh | 20
Device Generic type uses device memory that is coherently
accesible by the CPU. Usually, this is shown as SP
(special purpose) memory range at the BIOS-e820 memory
enumeration. If no SP memory is supported in system,
this could be faked by setting CONFIG_EFI_FAKE_MEMMAP.
Currently, test_hmm only s
Test cases such as migrate_fault and migrate_multiple,
were modified to explicit migrate from device to sys memory
without the need of page faults, when using device generic
type.
Snapshot test case updated to read memory device type
first and based on that, get the proper returned results
migrate
Two helpers added. One checks if zone device page is generic
type. The other if page is either private or generic type.
Signed-off-by: Alex Sierra
---
include/linux/mm.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index d8d79bb94be8..f5b247
In order to configure device generic in test_hmm, two
module parameters should be passed, which correspon to the
SP start address of each device (2) spm_addr_dev0 &
spm_addr_dev1. If no parameters are passed, private device
type is configured.
Signed-off-by: Alex Sierra
---
lib/test_hmm.c |
Add MEMORY_DEVICE_GENERIC case to free_zone_device_page
callback.
Device generic type memory case is now able to free its
pages properly.
Signed-off-by: Alex Sierra
---
mm/memremap.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/mm/memremap.c b/mm/memremap.c
index 614b
Generic device type memory on VRAM to RAM migration,
has similar access as System RAM from the CPU. This flag sets
the source from the sender. Which in Generic type case,
should be set as SYSTEM.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
When CPU is connected throug XGMI, it has coherent
access to VRAM resource. In this case that resource
is taken from a table in the device gmc aperture base.
This resource is used along with the device type, which could
be DEVICE_PRIVATE or DEVICE_GENERIC to create the device
page map region.
Sign
new ioctl cmd added to query zone device type. This will be
used once the test_hmm adds zone device generic type.
Signed-off-by: Alex Sierra
---
lib/test_hmm.c | 15 ++-
lib/test_hmm_uapi.h | 7 +++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/lib/test_hmm
From: Ralph Campbell
There are several places where ZONE_DEVICE struct pages assume a reference
count == 1 means the page is idle and free. Instead of open coding this,
add a helper function to hide this detail.
v3:
[AS]: rename dax_layout_is_idle_page func to dax_page_unused
v4:
[AS]: This ref
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that complicates the
code for put_page() and several places in the kernel that need to check the
reference count to see that a page is not being used (gup, compaction,
migration, etc.). Clean up the code so the reference
Device generic type case added for migrate_vma_pages and
migrate_vma_check_page helpers.
Both, generic and private device types have the same
conditions to decide to migrate pages from/to device
memory.
Signed-off-by: Alex Sierra
---
mm/migrate.c | 20 +---
1 file changed, 9 inse
v1:
AMD is building a system architecture for the Frontier supercomputer with a
coherent interconnect between CPUs and GPUs. This hardware architecture allows
the CPUs to coherently access GPU device memory. We have hardware in our labs
and we are working with our partner HPE on the BIOS, firmware
The AMD architecture for the Frontier supercomputer will
have device memory which can be coherently accessed by
the CPU. The system BIOS advertises this memory as SPM
(special purpose memory) in the UEFI system address map.
The AMDGPU driver needs to be able to lookup this resource
in order to cla
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 +++
1 file changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..5dc9bf6edda0
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm devic
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 83 --
drivers/soc/mediatek/mtk-mmsys.c | 10
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files ch
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mutex
The hardware path of vdosys1 with DPTx output need to go through
by several modules, such as, PSEUDO_OVL, ETHDR, and MERGE.
Add DRM and these modules support by the patches below:
Signed-off-by: Nancy.Lin
---
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 a
1. Add pseudo-ovl definition file for mt8195 display.
2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++
2 files chang
On 7/17/21 4:21 PM, Qiang Yu wrote:
On Sat, Jul 17, 2021 at 9:08 PM Marek Vasut wrote:
On 7/17/21 2:34 PM, Qiang Yu wrote:
On Sat, Jul 17, 2021 at 2:20 AM Marek Vasut wrote:
Instead of requesting two separate clock and then handling them
separately in various places of the driver, use clk_
On Sat, Jul 17, 2021 at 9:08 PM Marek Vasut wrote:
>
> On 7/17/21 2:34 PM, Qiang Yu wrote:
> > On Sat, Jul 17, 2021 at 2:20 AM Marek Vasut wrote:
> >>
> >> Instead of requesting two separate clock and then handling them
> >> separately in various places of the driver, use clk_bulk_*() API.
> >> T
On 7/17/21 2:34 PM, Qiang Yu wrote:
On Sat, Jul 17, 2021 at 2:20 AM Marek Vasut wrote:
Instead of requesting two separate clock and then handling them
separately in various places of the driver, use clk_bulk_*() API.
This permits handling devices with more than "bus"/"core" clock,
like ZynqMP,
Move a call to mdp5_encoder_set_intf_mode() after
msm_dsi_modeset_init(), removing set_encoder_mode callback.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/d
set_encoder_mode callback is completely unused now. Drop it from
msm_kms_func().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_kms.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/
Move setting up encoders from set_encoder_mode to
_dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This
allows us to support not only "single DSI" and "bonded DSI" but also "two
independent DSI" configurations. In future this would also help adding
support for multiple DP connectors.
None of the display drivers now implement set_encoder_mode callback.
Stop calling it from the modeset init code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 2 --
drivers/gpu/drm/msm/dsi/dsi.h | 1 -
drivers/gpu/drm/msm/dsi/ds
Add three helper functions to be used by display drivers for setting up
encoders.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 7 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 19 +++
drivers/gpu/drm/msm/msm_drv.h
We are preparing to support two independent DSI hosts in the DSI/DPU
code. To remove possible confusion (as both configurations can be
referenced as dual DSI) let's rename old "dual DSI" (two DSI hosts
driving single device, with clocks being locked) to "bonded DSI".
Signed-off-by: Dmitry Baryshko
This patchseries adds support for independent DSI config to DPU1 display
subdriver. Also drop one of msm_kms_funcs callbacks, made unnecessary
now.
Tested on RB5 (dpu, dsi). Previous iteration was tested by Alexey
Minnekhanov.
Changes since v3:
- Fix missing semicolon in the msm_dsi_is_master_ds
On 13/07/2021 00:15, abhin...@codeaurora.org wrote:
On 2021-07-10 15:20, Dmitry Baryshkov wrote:
Move setting up encoders from set_encoder_mode to
_dpu_kms_initialize_dsi() / _dpu_kms_initialize_displayport(). This
allows us to support not only "single DSI" and "bonded DSI" but also "two
indepen
On Sat, Jul 17, 2021 at 2:20 AM Marek Vasut wrote:
>
> Instead of requesting two separate clock and then handling them
> separately in various places of the driver, use clk_bulk_*() API.
> This permits handling devices with more than "bus"/"core" clock,
> like ZynqMP, which has "gpu"/"gpu_pp0"/"gp
https://bugzilla.kernel.org/show_bug.cgi?id=213569
Martin (martin...@gmx.com) changed:
What|Removed |Added
Kernel Version|5.12, 5.11 |5.13
--
You may reply to th
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++
2 files changed, 142 inserti
refcount_t type and corresponding API can protect refcounters from
accidental underflow and overflow and further use-after-free situations
Signed-off-by: Xiyu Yang
Signed-off-by: Xin Tan
---
drivers/gpu/drm/i915/gvt/gtt.c | 11 ++-
drivers/gpu/drm/i915/gvt/gtt.h | 3 ++-
2 files change
From: "Ainux.Wang"
There is should a status when do not get edid.
Signed-off-by: Ainux.Wang
---
drivers/gpu/drm/ast/ast_mode.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index e5996ae03c49..05df48b3d223
Thomas Zimmermann 于2021年7月16日周五 下午2:29写道：
>
> Hi
>
> Am 16.07.21 um 03:56 schrieb ainux.w...@gmail.com:
> > From: "Ainux.Wang"
> >
> > The function ast_get_modes() will also return 0, when it try to get the
> > edid, but it also do not get the edid.
> >
> > Signed-off-by: Ainux.Wang
> > ---
> >
Hi
The attached patch fixes a problem where non-drm ioctls are incorrectly
handled by drm drivers.
This causes problems when isatty() is called on a file descriptor which
was opened on a drm device node. Glibc implements isatty() by invoking
the TCGETS ioctl on the fd. TCGETS is 0x5401, so this
Thomas Zimmermann 于2021年7月16日周五 下午8:00写道：
>
> Hi
>
> Am 16.07.21 um 11:55 schrieb ainux.w...@gmail.com:
> > From: "Ainux.Wang"
> >
> > There is should a status when do not get edid.
>
> Well, not really.
>
> So, the problem is that VGA is not hotplug-able. It's supposed to be
> connected when the
This adds support for the iTE IT6505.
This device can convert DPI signal to DP output.
From: Allen Chen
Tested-by: Hsin-yi Wang
Signed-off-by: Hermes Wu
Signed-off-by: Allen Chen
---
drivers/gpu/drm/bridge/Kconfig |7 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/br
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
Two RDMAs merge into one layer, so this module support 4
layers. The four layers are blending at the EHTDR module next to it.
Signed-off-
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subseque
Add merge vblank support.
The vdosys1 go through the following component:
pseudo_ovl -> ethdr -> merge5 -> dp_intf1
The first comp is pseudo_ovl. This comp doesn't
have the whole CRTC timing vblank but only has vblank for each layer.
Merge5 comp gets all the mixed layers after the ETHDR module.
Use
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