Hi Liu,
On Tue, Dec 22, 2020 at 09:36:37AM +0200, Laurent Pinchart wrote:
> On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
> >
> > Signed-off-by: Liu Ying
> > ---
> > .../bindings/display/bridge/fsl,imx8qxp-ldb.ya
Hi Liu,
Thank you for the patch.
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
>
> Signed-off-by: Liu Ying
> ---
> .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185
> +
> 1 file change
Hi Liu,
Thank you for the patch.
On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp display pixel link.
>
> Signed-off-by: Liu Ying
> ---
> .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128
> +
> 1 file changed, 128
https://bugzilla.kernel.org/show_bug.cgi?id=210841
--- Comment #1 from Neil Shepperd (nshepp...@gmail.com) ---
The laptop was unresponsive, but I could ssh in to read dmesg and attempt
reboot (which seemingly failed, requiring hard reset).
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You may reply to this email to add a comment.
You ar
https://bugzilla.kernel.org/show_bug.cgi?id=210841
Bug ID: 210841
Summary: divide error in Calculate256BBlockSizes
Product: Drivers
Version: 2.5
Kernel Version: 5.9.14
Hardware: x86-64
OS: Linux
Tree: Mainline
Hi Rob,
Thank you for the patch.
On Mon, Dec 21, 2020 at 04:46:59PM -0700, Rob Herring wrote:
> *-supply properties are always a single phandle, so binding schemas
> don't need a type $ref nor 'maxItems'.
>
> A meta-schema check for this is pending once these existing cases are
> fixed.
>
> Cc:
Hi Rob,
Thank you for the patch.
On Mon, Dec 21, 2020 at 09:06:45PM -0700, Rob Herring wrote:
> 'maxItems' equal to the 'items' list length is redundant. 'maxItems' is
> preferred for a single entry while greater than 1 should have an 'items'
> list.
>
> A meta-schema check for this is pending o
Hi Rob,
On Mon, Dec 21, 2020 at 09:06:45PM -0700, Rob Herring wrote:
> 'maxItems' equal to the 'items' list length is redundant. 'maxItems' is
> preferred for a single entry while greater than 1 should have an 'items'
> list.
>
> A meta-schema check for this is pending once these existing cases a
Hi Rob
On Mon, Dec 21, 2020 at 04:46:59PM -0700, Rob Herring wrote:
> *-supply properties are always a single phandle, so binding schemas
> don't need a type $ref nor 'maxItems'.
>
> A meta-schema check for this is pending once these existing cases are
> fixed.
>
> Cc: Jonathan Cameron
> Cc: Dm
https://bugzilla.kernel.org/show_bug.cgi?id=210467
cpl (catchker...@interwebs.at) changed:
What|Removed |Added
CC||catchker...@interwebs.at
https://bugzilla.kernel.org/show_bug.cgi?id=210787
--- Comment #6 from Janpieter Sollie (janpieter.sol...@edpnet.be) ---
No, I rebooted with no options (aside from IPmask, it is required to bring up
the gpu) and it doesn't work either
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'maxItems' equal to the 'items' list length is redundant. 'maxItems' is
preferred for a single entry while greater than 1 should have an 'items'
list.
A meta-schema check for this is pending once these existing cases are
fixed.
Cc: Laurent Pinchart
Cc: Vinod Koul
Cc: Mark Brown
Cc: Greg Kroah-
https://bugzilla.kernel.org/show_bug.cgi?id=205675
--- Comment #43 from wrenrte (raidon.lo...@auweek.net) ---
https://www.bkreader.com/events/streamswatchsteelers-vs-bengals-live-stream-reddit-13/
https://www.bkreader.com/events/nfl-stream-steelers-vs-bengals-live-streamreddit/
https://www.bkreade
On Thu, Dec 17, 2020 at 09:05:56PM +0300, Dmitry Osipenko wrote:
> Document "clocks" sub-node which describes Tegra SoC clocks that require
> a higher voltage of the core power domain in order to operate properly on
> a higher rates.
Seems like an odd reason to have a bunch of child nodes. It very
On Thu, 17 Dec 2020 21:05:55 +0300, Dmitry Osipenko wrote:
> Document new DVFS OPP table and power domain properties of the video
> decoder engine.
>
> Signed-off-by: Dmitry Osipenko
> ---
> .../devicetree/bindings/media/nvidia,tegra-vde.txt | 12
> 1 file changed, 12 insertions(+
On Thu, 17 Dec 2020 21:05:54 +0300, Dmitry Osipenko wrote:
> Document new DVFS OPP table and power domain properties of the Host1x bus
> and devices sitting on the bus.
>
> Signed-off-by: Dmitry Osipenko
> ---
> .../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
> 1 file cha
https://bugzilla.kernel.org/show_bug.cgi?id=205675
wrenrte (raidon.lo...@auweek.net) changed:
What|Removed |Added
CC||raidon.lo...@auweek.ne
*-supply properties are always a single phandle, so binding schemas
don't need a type $ref nor 'maxItems'.
A meta-schema check for this is pending once these existing cases are
fixed.
Cc: Jonathan Cameron
Cc: Dmitry Torokhov
Cc: Laurent Pinchart
Cc: Mauro Carvalho Chehab
Cc: Sakari Ailus
Cc:
On Thu, Dec 17, 2020 at 09:05:52PM +0300, Dmitry Osipenko wrote:
> Power domain fits much better than a voltage regulator in regards to
> a proper hardware description and from a software perspective as well.
> Hence replace the core regulator with the power domain. Note that this
> doesn't affect
On Thu, 17 Dec 2020 21:05:51 +0300, Dmitry Osipenko wrote:
> Power domain fits much better than a voltage regulator in regards to
> a proper hardware description and from a software perspective as well.
> Hence replace the core regulator with the power domain. Note that this
> doesn't affect any ex
On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
>
> Signed-off-by: Liu Ying
> ---
> .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185
> +
> 1 file changed, 185 insertions(+)
> create mode
On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp display pixel link.
>
> Signed-off-by: Liu Ying
> ---
> .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 128
> +
> 1 file changed, 128 insertions(+)
> create mode 10064
On Thu, Dec 17, 2020 at 05:59:26PM +0800, Liu Ying wrote:
> This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
> The pixel link forms a standard asynchronous linkage between
> pixel sources(display controller or camera module) and pixel
> consumers(imaging or displays). It con
On Fri, Dec 18, 2020 at 05:16:56PM -0800, John Stultz wrote:
> On Fri, Dec 18, 2020 at 6:36 AM Daniel Vetter wrote:
> > On Thu, Dec 17, 2020 at 11:06:11PM +, John Stultz wrote:
> > > Reuse/abuse the pagepool code from the network code to speed
> > > up allocation performance.
> > >
> > > This
On Thu, Dec 17, 2020 at 05:59:23PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp pixel combiner.
>
> Signed-off-by: Liu Ying
> ---
> .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160
> +
> 1 file changed, 160 insertions(+)
> create mode 100644
>
On Wed, Dec 2, 2020 at 10:02 AM Thomas Zimmermann wrote:
>
>
>
> Am 02.12.20 um 09:47 schrieb Tian Tao:
> > Use the devm_drm_dev_alloc provided by the drm framework to alloc
> > a structure hibmc_drm_private.
> >
> > Signed-off-by: Tian Tao
>
> This looks good now. Thanks for sticking to it.
>
>
On Mon, Dec 21, 2020 at 08:45:22AM +0800, Tian Tao wrote:
> Using the managed function simplifies the error handling. After
> unloading the driver, the PCI device should now get disabled as
> well.
>
> Signed-off-by: Tian Tao
> ---
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 6 ++
>
On Mon, Dec 21, 2020 at 08:38:44PM +0200, Laurent Pinchart wrote:
> Hi Daniel,
>
> On Mon, Dec 21, 2020 at 07:36:22PM +0100, Daniel Vetter wrote:
> > On Mon, Dec 21, 2020 at 2:57 AM Laurent Pinchart wrote:
> > >
> > > From: Kieran Bingham
> > >
> > > Extend the existing color management propertie
On Wed, Dec 16, 2020 at 05:30:11PM +0800, Chunfeng Yun wrote:
> Convert mediatek,mtu3.txt to YAML schema mediatek,mtu3.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v4:
> 1. refer to usb-drd.yaml insstead of usb/generic.txt
> the following ones suggested by Rob:
> 2. add the number of phys s
On Wed, Dec 16, 2020 at 05:30:10PM +0800, Chunfeng Yun wrote:
> Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v4: update it according to Rob's suggestion
> 1. modify dictionary of phys
> 2. fix endentation in "mediatek,syscon-wakeu
On Wed, 16 Dec 2020 17:30:08 +0800, Chunfeng Yun wrote:
> Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml
>
> Cc: Chun-Kuang Hu
> Cc: Philipp Zabel
> Signed-off-by: Chunfeng Yun
> ---
> v4:
> 1. add maintainer Philipp add support mt8183 suggested by Chun-Kuang
> 2. use key
On Wed, 16 Dec 2020 17:30:03 +0800, Chunfeng Yun wrote:
> Due to usb-device.txt is converted into usb-device.yaml,
> so modify reference file names at the same time.
>
> Signed-off-by: Chunfeng Yun
> ---
> v2~v4: no changes
> ---
> Documentation/devicetree/bindings/net/btusb.txt | 2 +-
> 1 file
On Wed, Dec 16, 2020 at 05:30:02PM +0800, Chunfeng Yun wrote:
> Convert usb-device.txt to YAML schema usb-device.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v4: no changes, update dependent series:
> https://patchwork.kernel.org/project/linux-usb/list/?series=399561
> [v6,00/19] dt-bindi
Hi Daniel,
On Mon, Dec 21, 2020 at 07:36:22PM +0100, Daniel Vetter wrote:
> On Mon, Dec 21, 2020 at 2:57 AM Laurent Pinchart wrote:
> >
> > From: Kieran Bingham
> >
> > Extend the existing color management properties to support provision
> > of a 3D cubic look up table, allowing for color specifi
On Mon, Dec 21, 2020 at 2:57 AM Laurent Pinchart
wrote:
>
> From: Kieran Bingham
>
> Extend the existing color management properties to support provision
> of a 3D cubic look up table, allowing for color specific adjustments.
>
> Signed-off-by: Kieran Bingham
> Co-developed-by: Laurent Pinchart
https://bugzilla.kernel.org/show_bug.cgi?id=209987
--- Comment #7 from youling...@gmail.com ---
(In reply to Alex Deucher from comment #6)
> Does this patch work any better?
> https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg54780.html
nice! test this patch fix my memleak problem.
-
On Fri, Dec 18, 2020 at 9:15 PM Liu Ying wrote:
>
> Hi,
>
> On Fri, 2020-12-18 at 16:42 -0600, Rob Herring wrote:
> > On Thu, Dec 17, 2020 at 7:48 PM Liu Ying wrote:
> > >
> > > Hi,
> > >
> > > On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
> > > > On Thu, 17 Dec 2020 17:59:23 +0800, Liu Y
https://bugzilla.kernel.org/show_bug.cgi?id=209987
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
https://bugzilla.kernel.org/show_bug.cgi?id=210787
--- Comment #5 from Alex Deucher (alexdeuc...@gmail.com) ---
Most of those are not applicable or the default. Does it work properly without
any parameters?
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https://bugzilla.kernel.org/show_bug.cgi?id=209987
--- Comment #5 from youling...@gmail.com ---
(In reply to Lee Starnes from comment #3)
> Created attachment 293577 [details]
> proposed patch
this patch seem no help for me, test on linux 5.10 kernel.
thanks for you point the bad commit,
i can r
https://bugzilla.kernel.org/show_bug.cgi?id=209987
youling...@gmail.com changed:
What|Removed |Added
CC||youling...@gmail.com
--- Comment #
Hi Laurent,
On 14/12/2020 20:52, Laurent Pinchart wrote:
> devm_kzalloc() is the wrong API to allocate encoders, as the lifetime of
> the encoders is tied to the DRM device, not the device to driver
> binding. drmm_kzalloc() isn't a good option either, as it would result
> in the encoder being fre
https://bugzilla.kernel.org/show_bug.cgi?id=210787
--- Comment #4 from Janpieter Sollie (janpieter.sol...@edpnet.be) ---
My amdgpu options:
options amdgpu ip_block_mask=0x7f discovery=1 compute_multipipe=1
gpu_recovery=1 mes=1 abmlevel=4 send_sigterm=1 sched_policy=1 dpm=1 aspm=1
--
You may repl
https://bugzilla.kernel.org/show_bug.cgi?id=210787
--- Comment #3 from Janpieter Sollie (janpieter.sol...@edpnet.be) ---
Disabling UVD + VCE is on purpose... gfx8 video coding is simply too bad to be
useful. Next to that, this issue still apprears:
https://bugzilla.kernel.org/show_bug.cgi?id=20615
https://bugzilla.kernel.org/show_bug.cgi?id=210787
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
Hi Laurent,
On 21/12/2020 01:57, Laurent Pinchart wrote:
> From: Kieran Bingham
>
> Link the DRM 3D-CLU configuration to the CMM setup configuration.
>
> Signed-off-by: Kieran Bingham
> Signed-off-by: Laurent Pinchart
And for the updates from my original patch (variable rename, and
property
Hi Laurent,
On 21/12/2020 01:57, Laurent Pinchart wrote:
> From: Kieran Bingham
>
> Extend the existing color management properties to support provision
> of a 3D cubic look up table, allowing for color specific adjustments.
>
> Signed-off-by: Kieran Bingham
> Co-developed-by: Laurent Pinchart
Hi Laurent,
On 21/12/2020 01:57, Laurent Pinchart wrote:
> From: Kieran Bingham
>
> The CMM module provides a three-dimensional cubic look up table that
> converts three-color-component data into desired three color components
> by use of a lookup table.
>
> While the 1D-LUT can only control ea
Hi Laurent,
On 21/12/2020 01:57, Laurent Pinchart wrote:
> To prepare for CLU support, expend the CMM API exposed to the DU driver
s/expend/extend/ ...?
> to separate the LUT table pointer from the LUT update decision. This
> will be required, as we will need to update the LUT and CLU
> independ
On Fri, 2020-12-18 at 10:46 -0800, José Roberto de Souza wrote:
> Much more clear to read one function call than four lines doing this
> conversion.
>
> v7:
> - function renamed
> - calculating width and height before truncate
> - inlined
>
> Cc: Ville Syrjälä
> Cc: dri-devel@lists.freedesktop.o
19.12.2020 14:02, Krzysztof Kozlowski пишет:
> On Thu, Dec 17, 2020 at 09:06:31PM +0300, Dmitry Osipenko wrote:
>> Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
>> initialization.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> drivers/memory/tegra/tegra20-emc.c | 57 +++
On modern gpus, GTT (system memory) works as well here, and this may
also be a workaround for platforms which cannot map vram correctly.
Signed-off-by: chenli
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/a
19.12.2020 13:57, Krzysztof Kozlowski пишет:
> On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote:
>> All NVIDIA Tegra SoCs have a core power domain where majority of hardware
>> blocks reside. Add binding for the core power domain.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> .../
Using the managed function simplifies the error handling. After
unloading the driver, the PCI device should now get disabled as
well.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/
When using e8860(gcn1) on arm64, the kernel crashed on drm/radeon:
[ 11.240414] pc : __memset+0x4c/0x188
[ 11.244101] lr : radeon_uvd_get_create_msg+0x114/0x1d0 [radeon]
[ 11.249995] sp : 0d7eb700
[ 11.253295] x29: 0d7eb700 x28: 8001f632a868
[ 11.258585] x27:
Hi,
On Monday, December 21st, 2020 at 2:57 AM, Laurent Pinchart
wrote:
> I started having a look at userspace to see how this could be handled,
> searching for color management support in weston, kwin and wlroots/sway.
> All three support setting the gamma table when using the DRM/KMS
> backend
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