On Mon, Dec 21, 2020 at 4:03 AM Laurent Pinchart
wrote:
>
> Replace the reference to the DWC HDMI text DT binding with a reference
> to the YAML equivalent.
>
> Signed-off-by: Laurent Pinchart
> Acked-by: Rob Herring
Acked-by: Chen-Yu Tsai
___
dri-de
From: Kieran Bingham
Extend the existing color management properties to support provision
of a 3D cubic look up table, allowing for color specific adjustments.
Signed-off-by: Kieran Bingham
Co-developed-by: Laurent Pinchart
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/drm_atomic_helpe
From: Kieran Bingham
The CMM module provides a three-dimensional cubic look up table that
converts three-color-component data into desired three color components
by use of a lookup table.
While the 1D-LUT can only control each of three color components
separately, the 3D-CLU can be used for spec
From: Kieran Bingham
Link the DRM 3D-CLU configuration to the CMM setup configuration.
Signed-off-by: Kieran Bingham
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/
To prepare for CLU support, expend the CMM API exposed to the DU driver
to separate the LUT table pointer from the LUT update decision. This
will be required, as we will need to update the LUT and CLU
independently.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_cmm.c | 60
Hello,
This patch series adds cubic (3D) look up table support to the CMM and
DU drivers, and extend the KMS userspace API to expose the cubic LUT to
userspace.
The code is fairly straightforward. Patch 1/4 refactors the CMM (color
management module, the Renesas R-Car IP core that handles 1D and
https://bugzilla.kernel.org/show_bug.cgi?id=210805
--- Comment #1 from John Haverkamp (j...@haverkamp.us) ---
Created attachment 294249
--> https://bugzilla.kernel.org/attachment.cgi?id=294249&action=edit
kern.log
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https://bugzilla.kernel.org/show_bug.cgi?id=210805
Bug ID: 210805
Summary: Sapphire Nitro+ RX6800 momentary graphical corruption
and black screen during startup
Product: Drivers
Version: 2.5
Kernel Version: 5.10.1
Hardw
On Sun, Dec 20, 2020 at 09:49:59PM +0200, Laurent Pinchart wrote:
> Hello,
>
> This patch series attempts a conversion of the DWC HDMI TX DT bindings
> to YAML.
>
> The DWC HDMI TX is an HDMI transmitter IP core from Synopsys, integrated
> in various SoCs with different glue layers. As such, some
dw_hdmi.txt has been replaced with synopsys,dw-hdmi.yaml, and all
references to the old file have been converted. Remove it.
Signed-off-by: Laurent Pinchart
Acked-by: Rob Herring
---
.../bindings/display/bridge/dw_hdmi.txt | 33 ---
1 file changed, 33 deletions(-)
delete
Replace the reference to the DWC HDMI text DT binding with a reference
to the YAML equivalent.
Signed-off-by: Laurent Pinchart
Acked-by: Rob Herring
---
.../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/Documen
Convert the i.MX6 HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart
---
Changes since v1:
- Only specify maxItems for clocks
- Drop reg and interrupts as they're checked in the base schema
- Rebase on top of OF graph schema, dropped redundant properties
- Fix identation for enum entr
Convert the Rockchip HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart
---
Changes since v1:
- Drop pinctrl-0 and pinctrl-1
- Use unevaluatedProperties instead of additionalProperties
- Drop reg and interrupts as they're checked in the base schema
- Rebase on top of OF graph schema,
Convert the Renesas R-Car DWC HDMI TX text binding to YAML.
Signed-off-by: Laurent Pinchart
---
Changes since v1:
- Drop the part numbers in comments, only keep the SoC names
- Use unevaluatedProperties instead of additionalProperties
- Only specify maxItems for clocks and clock-names
- Drop reg
Hello,
This patch series attempts a conversion of the DWC HDMI TX DT bindings
to YAML.
The DWC HDMI TX is an HDMI transmitter IP core from Synopsys, integrated
in various SoCs with different glue layers. As such, some properties are
defined in a common document, but sometimes need to be overridde
Add a .yaml schema containing the common properties for the Synopsys
DesignWare HDMI TX controller. This isn't a full device tree binding
specification, but is meant to be referenced by platform-specific
bindings for the IP core.
Signed-off-by: Laurent Pinchart
---
Changes since v1:
- Add defaul
Hi Xu Wang,
Thank you for the patch.
On Fri, Nov 27, 2020 at 09:18:29AM +, Xu Wang wrote:
> Because clk_disable_unprepare() already checked NULL clock parameter,
> so the additional check is unnecessary, just remove them.
>
> Signed-off-by: Xu Wang
Reviewed-by: Laurent Pinchart
> ---
>
Hi Xu Wang,
Thank you for the patch.
On Fri, Nov 27, 2020 at 09:23:32AM +, Xu Wang wrote:
> Because clk_disable_unprepare() already checked NULL clock parameter,
> so the additional check is unnecessary, just remove them.
>
> Signed-off-by: Xu Wang
Reviewed-by: Laurent Pinchart
> ---
>
Convert the Renesas R-Car DU text binding to YAML.
Signed-off-by: Laurent Pinchart
---
Changes since v2:
- Drop boilerplate for ports node
- Add description for interrupts peroperty
- Use single quoted strings to avoid double backslashes
Changes since v1:
- Use pattern instead of enum for dclk
Hi Rob,
On Thu, Dec 17, 2020 at 05:48:22PM -0600, Rob Herring wrote:
> On Wed, Dec 16, 2020 at 01:06:03AM +0200, Laurent Pinchart wrote:
> > Convert the Renesas R-Car DU text binding to YAML.
>
> I tend to think this should be split up, but up to you.
I wouldn't mind, but I'm not sure how to do
Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
to panel-simple.
The panel spec from Variscite can be found at:
https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
Signed-off-by: Oliver Graute
---
panel-timing {
clock-frequency = <350
From: Markus Elfring
Date: Sat, 19 Dec 2020 18:18:59 +0100
Adjust a jump target so that a bit of exception handling can be better
reused at the end of this function.
Signed-off-by: Markus Elfring
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 ++-
1 file changed, 6 insertions(+)
On Wed, Dec 16, 2020 at 5:16 PM Paul E. McKenney wrote:
> In my experience, lockdep will indeed complain if an interrupt handler
> returns while in an RCU read-side critical section.
Can't we add lock status checks into the beginning and the end of interrupt
handler functions
(e.g. whether "stru
From: Markus Elfring
Date: Sat, 19 Dec 2020 18:30:56 +0100
Two update suggestions were taken into account
from static source code analysis.
Markus Elfring (2):
Return directly after a failed kzalloc()
Use common error handling code
drivers/gpu/drm/amd/display/dc/core/dc.c | 21
Set the flag vblank_disable_immediate = true to turn off vblank irqs
immediately as soon as drm_vblank_put is requested so that there are
no irqs triggered during idle state. This will reduce cpu wakeups
and help in power saving.
To enable vblank_disable_immediate flag the underlying KMS driver
ne
On 12/17/20 9:33 PM, Stephen Rothwell wrote:
> Hi all,
>
> News: there will be no linux-next releases between Dec 24 and Jan
> 3 inclusive.
>
> Please do not add any v5.12 destined code to your linux-next included
> branches until after v5.11-rc1 has been released.
>
> Changes since 20201217:
>
Hi Dave,
On Fri, Dec 18, 2020 at 11:37:50AM +, Dave Stevenson wrote:
> Hi Maxime
>
> On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
> >
> > While the BCM2835 had the CEC clock derived from the HSM clock, the
> > BCM2711 has a dedicated parent clock for it.
> >
> > Let's introduce a separ
The eLCDIF controller is also present on i.MX6UL/i.MX6ULL SoCs so add
them in the Kconfig option description.
Signed-off-by: Sébastien Szymanski
---
drivers/gpu/drm/mxsfb/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/m
Hi,
On Fri, 2020-12-18 at 16:42 -0600, Rob Herring wrote:
> On Thu, Dec 17, 2020 at 7:48 PM Liu Ying wrote:
> >
> > Hi,
> >
> > On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
> > > On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
> > > > This patch adds bindings for i.MX8qm/qxp pixel
irq_hpd event can only be executed at connected state. Therefore
irq_hpd event should be postponed if it happened at connection
pending state. This patch also make sure both link rate and lane
are valid before start link training.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_display
syzbot suspects this issue was fixed by commit:
commit e722a295cf493388dae474745d30e91e1a2ec549
Author: Greg Kroah-Hartman
Date: Thu Aug 27 12:36:27 2020 +
staging: ion: remove from the tree
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=17d4f13750
start commit: ab
i.MX6UL/i.MX6ULL have eLCDIF controller, too.
Signed-off-by: Sébastien Szymanski
---
Documentation/devicetree/bindings/display/mxsfb.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt
b/Documentation/devicetree/bindings/display/mxsfb.txt
syzbot suspects this issue was fixed by commit:
commit a49145acfb975d921464b84fe00279f99827d816
Author: George Kennedy
Date: Tue Jul 7 19:26:03 2020 +
fbmem: add margin check to fb_check_caps()
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=1149f30f50
start commit:
From: Markus Elfring
Date: Sat, 19 Dec 2020 18:04:33 +0100
* Return directly after a call of the function “kzalloc” failed
at the beginning.
* Delete a label which became unnecessary with this refactoring.
Signed-off-by: Markus Elfring
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++
18.12.2020 10:14, Viresh Kumar пишет:
> On 17-12-20, 21:05, Dmitry Osipenko wrote:
>> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
>> power consumption and heating of the Tegra chips. Tegra SoC has multiple
>> hardware units which belong to a core power domain of the SoC
On Fri, 18 Dec 2020 16:10:12 +0800,
Christian König wrote:
>
> Am 18.12.20 um 04:51 schrieb Chen Li:
> > [SNIP]
> If your ARM base board can't do that for some then you can't use the
> hardware
> with that board.
> >>> Good to know, thanks! BTW, have you ever seen or heard boards l
The eLCDIF controller on i.MX6UL/i.MX6ULL supports the alpha plane too.
Enable it on these SoCs.
Signed-off-by: Sébastien Szymanski
---
While testing, I have noticed that the alpha plane works but
sometimes the framebuffer is shiftted to the right.
I tested with the following modetest command:
m
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