They trigger the BUG_ON() in drm_gem_private_object_init otherwise.
Signed-off-by: Chia-I Wu
Cc: Gurchetan Singh
Cc: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_vram.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/virtio/virtgpu_vram.c
b/drivers/gpu/drm/virtio/vir
On Fri, Dec 18, 2020 at 6:36 AM Daniel Vetter wrote:
> On Thu, Dec 17, 2020 at 11:06:11PM +, John Stultz wrote:
> > Reuse/abuse the pagepool code from the network code to speed
> > up allocation performance.
> >
> > This is similar to the ION pagepool usage, but tries to
> > utilize generic co
On Thu, Dec 17, 2020 at 7:48 PM Liu Ying wrote:
>
> Hi,
>
> On Thu, 2020-12-17 at 12:50 -0600, Rob Herring wrote:
> > On Thu, 17 Dec 2020 17:59:23 +0800, Liu Ying wrote:
> > > This patch adds bindings for i.MX8qm/qxp pixel combiner.
> > >
> > > Signed-off-by: Liu Ying
> > > ---
> > > .../display
On Mon, 07 Dec 2020 12:48:30 +0800, Zhen Lei wrote:
> Eliminate the following yamllint warnings:
> ./Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
> :52:9: [warning] wrong indentation: expected 6 but found 8 (indentation)
>
> ./Documentation/devicetree/bindings/display/bri
On Thu, 17 Dec 2020 00:59:45 +, Paul Cercueil wrote:
> The binding should use "unevaluatedProperties" instead of
> "additionalProperties", since it is a SPI device and may have
> SPI-related Device Tree properties, for instance the "spi-max-frequency"
> property that is present in the example.
The pull request you sent on Fri, 18 Dec 2020 17:47:53 +0100:
> git://anongit.freedesktop.org/drm/drm tags/drm-next-2020-12-18
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/c59c7588fc922e27c378a7e2a920b889bd6bf872
Thank you!
--
Deet-doot-dot, I am a bot.
https://ko
Pulled and pushed out.
josh
On Thu, Dec 10, 2020 at 7:46 PM Dmitry Baryshkov
wrote:
>
> Hello linux-firmware maintainers,
>
> The following changes since commit 7455a36066741a6e52fba65e04f6451b4cdfd9c4:
>
> Merge branch 'guc_v49' of git://anongit.freedesktop.org/drm/drm-firmware
> into main (
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
Cc: Ville Syrjälä
Cc: dri-devel@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
include/drm/drm_r
As far as I can tell the buffer_count was never used by an
userspace application.
The number of BOs in the system is far better suited in
debugfs than sysfs and we now should be able to add other
information here as well.
v2: add that additionally to sysfs
Signed-off-by: Christian König
Acked-b
Only initialize the DMA coherent pools if they are used.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_pool.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index 1cdacd5875
Useful for testing.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_pool.c | 50 ++
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index 1d61e8fc0e81..1cdacd58753a 100644
-
Instead of printing this on the per device pool.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_pool.c | 70 --
1 file changed, 50 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index 7b2f60
Hi Linus,
Merge window -fixes pull, but bigger: We've somehow missed one subtree
pull (which also contained the amdgpu multihop fix you cherry-pick, oops).
But that pull was pending for almost 3 weeks on the list and most of it
for even longer in linux-next, so really not seeing a reason why it sh
On Fri, Dec 18, 2020 at 5:10 PM Steven Rostedt wrote:
>
> On Thu, 17 Dec 2020 11:03:20 +0100
> Daniel Vetter wrote:
>
> > I think we're tripping over the might_sleep() all the mutexes have,
> > and that's not as good as yours, but good enough to catch a missing
> > rcu_read_unlock(). That's kinda
On Thu, 17 Dec 2020 11:03:20 +0100
Daniel Vetter wrote:
> I think we're tripping over the might_sleep() all the mutexes have,
> and that's not as good as yours, but good enough to catch a missing
> rcu_read_unlock(). That's kinda why I'm baffled, since like almost
> every 2nd function in the back
On Fri, Dec 18, 2020 at 03:08:12PM +, carsten.haitz...@foss.arm.com wrote:
> From: Carsten Haitzler
>
> KASAN found this problem. find_first_bit() expects to look at a
> pointer pointing to a long, but we look at a u32 - this is going to be
> an issue with endianess but, KSAN already flags th
On Fri, Dec 18, 2020 at 05:04:09PM +0200, Jani Nikula wrote:
>
> Hi Dave & Daniel -
>
> drm-intel-next-fixes-2020-12-18:
> drm/i915 fixes for the merge window
Pulled, thanks a lot.
-Daniel
>
>
> BR,
> Jani.
>
> The following changes since commit efd3043790c6e92f0bbe1fe385db9b544131c59c:
>
>
On 2020-12-18 14:33, Christian König wrote:
Am 18.12.20 um 15:17 schrieb Robin Murphy:
On 2020-12-17 14:02, Christian König wrote:
[SNIP]
Do you have some background why some ARM boards fail with that?
We had a couple of reports that memset/memcpy fail in userspace
(usually system just sponta
From: Carsten Haitzler
KASAN found this problem. find_first_bit() expects to look at a
pointer pointing to a long, but we look at a u32 - this is going to be
an issue with endianess but, KSAN already flags this as out-of-bounds
stack reads. This fixes it by just importing inot a local long.
Sign
Hi Dave & Daniel -
drm-intel-next-fixes-2020-12-18:
drm/i915 fixes for the merge window
BR,
Jani.
The following changes since commit efd3043790c6e92f0bbe1fe385db9b544131c59c:
Merge tag 'amd-drm-fixes-5.11-2020-12-16' of
git://people.freedesktop.org/~agd5f/linux into drm-next (2020-12-16 2
On Fri, 18 Dec 2020 at 14:21, Dave Stevenson
wrote:
>
> Hi Maxime & Dom
>
> On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
> >
> > From: Dom Cobley
> >
> > Currently we call cec_phys_addr_invalidate on a hotplug deassert.
> > That may be due to a TV power cycling, or an AVR being switched
>
On 2020-12-18 06:14, Chen Li wrote:
[...]
No, not performance. See standards like OpenGL, Vulkan as well as VA-API and
VDPAU require that you can mmap() device memory and execute memset/memcpy on
the memory from userspace.
If your ARM base board can't do that for some then you can't use the hard
On Thu, Dec 17, 2020 at 11:06:11PM +, John Stultz wrote:
> Reuse/abuse the pagepool code from the network code to speed
> up allocation performance.
>
> This is similar to the ION pagepool usage, but tries to
> utilize generic code instead of a custom implementation.
>
> Cc: Sumit Semwal
> C
Am 18.12.20 um 15:17 schrieb Robin Murphy:
On 2020-12-17 14:02, Christian König wrote:
[SNIP]
Do you have some background why some ARM boards fail with that?
We had a couple of reports that memset/memcpy fail in userspace
(usually system just spontaneously reboots or becomes unresponsive),
bu
On Thu, Dec 17, 2020 at 04:06:38PM -0500, Andrey Grodzovsky wrote:
>
> On 12/17/20 3:48 PM, Daniel Vetter wrote:
> > On Thu, Dec 17, 2020 at 9:38 PM Andrey Grodzovsky
> > wrote:
> > >
> > > On 12/17/20 3:10 PM, Christian König wrote:
> > > > [SNIP]
> > > > > > > By eliminating such users, and re
Hi Dom & Maxime
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
>
> From: Dom Cobley
>
> Now that our HDMI controller supports CEC for the BCM2711, let's remove
> that flag.
>
> Signed-off-by: Dom Cobley
> Signed-off-by: Maxime Ripard
Reviewed-by: Dave Stevenson
> ---
> drivers/gpu/drm/
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
>
> We introduced the BCM2711 support to the vc4 HDMI controller with 5.10,
> but this was lacking any of the interrupts of the CEC controller so we
> have to deal with the backward compatibility.
>
> Do so by simply ignoring the CEC setup if the
Hi Maxime
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
>
> As part of the enable sequence we might change the HSM clock rate if the
> pixel rate is different than the one we were already dealing with.
>
> On the BCM2835 however, the CEC clock derives from the HSM clock so any
> rate change
Hi Maxime & Dom
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
>
> From: Dom Cobley
>
> Currently we call cec_phys_addr_invalidate on a hotplug deassert.
> That may be due to a TV power cycling, or an AVR being switched
> on (and switching edid).
>
> This makes CEC unusable since our contro
On 2020-12-17 14:02, Christian König wrote:
Am 17.12.20 um 14:45 schrieb Robin Murphy:
On 2020-12-17 10:25, Christian König wrote:
Am 17.12.20 um 02:07 schrieb Chen Li:
On Wed, 16 Dec 2020 22:19:11 +0800,
Christian König wrote:
Am 16.12.20 um 14:48 schrieb Chen Li:
On Wed, 16 Dec 2020 15:59:
On Thu, Dec 17, 2020 at 09:29:03PM +0100, Daniel Vetter wrote:
> On Fri, Dec 18, 2020 at 06:09:43AM +1000, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > As per the radeon/amdgpu fix don't use multihop is hw moves
> > aren't enabled.
> >
> > Reported-by: Mike Galbraith
> > Tested-by: Mike Gal
On Fri, Dec 18, 2020 at 02:42:43PM +0100, Christian König wrote:
> That seems to be unused.
>
> Signed-off-by: Christian König
> Reviewed-by: David Airlie
Dave asked me to pull this into drm-next directly, so I've done that.
For next time around please reference the bug reporter and credit the
That seems to be unused.
Signed-off-by: Christian König
Reviewed-by: David Airlie
---
drivers/gpu/drm/qxl/qxl_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index d8ecfb8b3193..66640f4947bd 100644
--- a/dri
My employment with TI is coming to an end and I will not have access to
the board where this bridge is connected to and I will also loose access to
the manual of the chip.
Add the missing copyright information, author and change the maintainer to
Sam Ravnborg (thank you for volenteering!)
Signed-
On Fri, 18 Dec 2020 at 12:23, Maxime Ripard wrote:
>
> Hi Dave,
>
> On Fri, Dec 18, 2020 at 11:37:50AM +, Dave Stevenson wrote:
> > Hi Maxime
> >
> > On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
> > >
> > > While the BCM2835 had the CEC clock derived from the HSM clock, the
> > > BCM271
Hi Sam,
On 17/12/2020 19.25, Sam Ravnborg wrote:
>>> dtschema/dtc warnings/errors:
>>> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml:
>>> 'maintainers' is a required property
>>> /builds/robherring/linux-dt-review/Documentation/devicetre
Hi Maxime
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
>
> While the BCM2835 had the CEC clock derived from the HSM clock, the
> BCM2711 has a dedicated parent clock for it.
>
> Let's introduce a separate clock for it so that we can handle both
> cases.
>
> Signed-off-by: Maxime Ripard
> -
Hi Maxime
On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
>
> The CEC clock divider needs to output a frequency of 40kHz from the HSM
> rate on the BCM2835. The driver used to have a fixed frequency for it,
> but that changed and we now need to compute it dynamically to maintain
> the proper r
Hi Maxime & Dom
On Thu, 10 Dec 2020 at 13:46, Maxime Ripard wrote:
>
> From: Dom Cobley
>
> The commit 311e305fdb4e ("drm/vc4: hdmi: Implement a register layout
> abstraction") forgot one CEC register, and made a copy and paste mistake
> for another one. Fix those mistakes.
>
> Fixes: 311e305fdb
Use amdgpu_sa_bo instead of amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 17 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 47 -
2 files changed, 31 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_
Hi Maxime & Dom
On Thu, 10 Dec 2020 at 13:46, Maxime Ripard wrote:
>
> From: Dom Cobley
>
> The hdmi reset got moved to a later point in the commit 9045e91a476b
> ("drm/vc4: hdmi: Add reset callback").
>
> However, the reset now occurs after vc4_hdmi_cec_init and so tramples
> the setup of regis
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, December 18, 2020 4:07 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Shar
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, December 18, 2020 4:07 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Sharm
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, December 18, 2020 4:07 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Shar
When a source supporting DSC1.1 is connected to DSC1.2 HDMI2.1 sink
via DP HDMI2.1 PCON, the PCON can be configured to decode the
DSC1.1 compressed stream and encode to DSC1.2. It then sends the
DSC1.2 compressed stream to the HDMI2.1 sink.
This patch configures the PCON for DSC1.1 to DSC1.2 encod
If PCON has capability to convert RGB->YCbCr colorspace and also
to 444->420 downsampling then for any YUV420 only mode, we can
let the PCON do all the conversion. If the PCON supports
RGB->YCbCr conversion for all BT2020, BT709, BT601, choose
the one that is selected by userspace via connector col
This patch adds support to read and store the DSC capabilities of the
HDMI2.1 PCon encoder. It also adds a new field to store these caps,
The caps are read during dfp update and can later be used to get the
PPS parameters for PCON-HDMI2.1 sink pair. Which inturn will be used
to take a call to overr
From: Swati Sharma
In this patch enables support for detecting link failures between
PCON and HDMI sink in i915 driver. HDMI link loss indication to
upstream DP source is indicated via IRQ_HPD. This is followed by
reading of HDMI link configuration status (HDMI_TX_LINK_ACTIVE_STATUS).
If the PCON
The DP-HDMI2.1 PCON spec provides way for a source to set PPS
parameters: slice height, slice width and bits_per_pixel, based on
the HDMI2.1 sink capabilities. The DSC encoder of the PCON will
respect these parameters, while preparing the 128 byte PPS.
This patch adds helper functions to calculate
This patch calls functions to check FRL training requirements
for an HDMI2.1 sink, when connected through PCON.
The call is made before the DP link training. In case FRL is not
required or failure during FRL training, the TMDS mode is selected
for the pcon.
v2: moved check_frl_training() just afte
HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON.
This patch captures this in dfp cap structure in intel_dp and uses
this to prune connector modes that cannot be supported by the PCON
and FRL bandwidth.
v2: Addressed review comments from Uma Shankar:
-tweaked the comparison of targ
This patch adds functions to start FRL training for an HDMI2.1 sink,
connected via a PCON as a DP branch device.
This patch also adds a new structure for storing frl training related
data, when FRL training is completed.
v2: As suggested by Uma Shankar:
-renamed couple of variables for better clar
DP Specification for DP2.0 to HDMI2.1 Pcon specifies support for conversion
of colorspace from RGB to YCbCr.
https://groups.vesa.org/wg/DP/document/previewpdf/15651
This patch adds the relavant registers and helper functions to
get the capability and set the color conversion bits for rgb->ycbcr
co
This patch adds registers for getting DSC encoder capability for
a HDMI2.1 PCon. It also addes helper functions to configure
DSC between the PCON and HDMI2.1 sink.
v2: Corrected offset for DSC encoder bpc and minor changes.
Also added helper functions for getting pcon dsc encoder capabilities
as s
From: Swati Sharma
There are specific DPCDs defined for detecting link failures between
the PCON and HDMI sink and check the link status. In case of link
failure, PCON will communicate the same using an IRQ_HPD to source.
HDMI sink would have indicated the same to PCON using SCDC interrupt
mechan
This patch adds support for configuring a PCON device,
connected as a DP branched device to enable FRL Link training
with a HDMI2.1 + sink.
v2: Fixed typos and addressed other review comments from Uma Shankar.
-changed the commit message for better clarity (Uma Shankar)
-removed unnecessary argume
This patch parses HFVSDB fields for DSC1.2 capabilities of an
HDMI2.1 sink. These fields are required by a source to understand the
DSC capability of the sink, to set appropriate PPS parameters,
before transmitting compressed data stream.
v2: Addressed following issues as suggested by Uma Shankar:
From: Swati Sharma
This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.
v2: Fixed minor bugs, and removed extra wrapper function (Uma Shan
From: Swati Sharma
The HDMI2.1 extends HFVSDB (HDMI Forum Vendor Specific
Data block) to have fields related to newly defined methods of FRL
(Fixed Rate Link) levels, number of lanes supported, DSC Color bit
depth, VRR min/max, FVA (Fast Vactive), ALLM etc.
This patch adds the new HFVSDB fields
This patch series attempts to add support for a DP-HDMI2.1 Protocol
Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
E5 to DisplayPort_v2.0:
https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299
The details are mentioned in:
VESA DP-to-HDMI PCON Speci
Am 18.12.20 um 09:52 schrieb Chen Li:
On Fri, 18 Dec 2020 16:10:12 +0800,
Christian König wrote:
Am 18.12.20 um 04:51 schrieb Chen Li:
[SNIP]
If your ARM base board can't do that for some then you can't use the hardware
with that board.
Good to know, thanks! BTW, have you ever seen or heard b
18.12.2020 00:19, Daniel Lezcano пишет:
> On 17/12/2020 21:28, Dmitry Osipenko wrote:
>> 17.12.2020 22:36, Daniel Lezcano пишет:
>> +type = "critical";
>> +};
>> +};
>> +
>> +
Add new Kconfig SOC_TEGRA_COMMON option which selects configuration
options that are common for all Tegra SoCs. Select PM_OPP by default
since from now on OPPs will be used by Tegra drivers which present on
all SoC generations, like display controller driver for example.
Signed-off-by: Dmitry Osip
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Signed-off-by: Liu Ying
---
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 17b92e6..96e05
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet, an
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a c
A required OPP may not be available, and thus, all OPPs which are using
this required OPP should be unavailable too.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index
This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB).
The LDB has two channels. Each of them supports up to 30bpp parallel
input color format and can map the input to VESA or JEIDA standards.
The two channels can be used simultaneously, either in dual mode or
split mode. In du
Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
levels don't start from 0 in OPP table and zero usually means a minimal
level.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 49 ++
include/linux/pm_opp.h | 8 +++
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
a/Documentation/devicetree/bindings/d
Make regulator_sync_voltage() to re-balance voltage state of a coupled
regulators instead of changing the voltage directly.
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
in
Add dev_pm_opp_set_voltage() which allows OPP table users to set voltage
in accordance to a given OPP. In particular this is needed for driving
voltage of a generic power domain which uses OPPs and doesn't have a
clock.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 52 +
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra20-emc.c
b
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
Note that this depends on the 'two cell binding' clock patch set which has
already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h
won't be found.
v4
Enable CPU voltage scaling and thermal throttling on Tegra30 Cardhu board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
b/arch/arm/bo
The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
On Thu, Dec 17, 2020 at 07:21:18AM -0800, Paul E. McKenney wrote:
> On Thu, Dec 17, 2020 at 11:03:20AM +0100, Daniel Vetter wrote:
> > On Wed, Dec 16, 2020 at 5:16 PM Paul E. McKenney wrote:
> > >
> > > On Wed, Dec 16, 2020 at 10:52:06AM +0100, Daniel Vetter wrote:
> > > > On Wed, Dec 16, 2020 at
Hi,
This patch set introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer. Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of blit engine a
Fix adding OPP entries in a wrong (opposite) order if OPP rate is
unavailable. The OPP comparison is erroneously skipped if OPP rate is
missing, thus OPPs are left unsorted.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 23 ---
drivers/opp/opp.h | 2 +-
2 files ch
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Signed-off-by: Liu Ying
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7b073c4..4b4e40e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5846,6 +5846,16 @@ F: Do
From: ChiYuan Huang
Adds DT binding document for Richtek RT4831 backlight.
Signed-off-by: ChiYuan Huang
---
since v5
- Drop the example in dt-binding. Aready full example in mfd dt-binding.
since v3
- Move inlcude/dt-bindings/leds/rt4831-backlight.h from patch 0004 to here.
- Add dual license
Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm/b
Support set_opp() customization without requiring to use regulators. This
is needed by drivers which want to use dev_pm_opp_set_rate() for changing
rates of a multiple clocks and don't need to touch regulator.
One example is NVIDIA Tegra30/114 SoCs which have two sibling 3D hardware
units which sh
17.12.2020 21:28, Daniel Lezcano пишет:
> On 17/12/2020 19:06, Dmitry Osipenko wrote:
>> Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
>> 1 file cha
Artifically use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.
Acked-by: Daniel Vetter
Signed-off-by: Liu Ying
---
v4->v5:
* No change.
v3->v4:
* Add Daniel's A-b tag.
v2->v3:
* Add a missing blank line.
v1->v2:
Hi Mathieu
For google reference design(mt8183+it6505), the maximum 95000kHz is depends on
mt8183 requirement.
-Original Message-
From: Mathieu Tournier [mailto:mathieutourn...@gmail.com]
Sent: Thursday, December 17, 2020 2:47 AM
To: Allen Chen (陳柏宇)
Cc: Jau-Chih Tseng (曾昭智); Kenneth Hun
Print OPP level in debug message of _opp_add_static_v2(). This helps to
chase GENPD bugs.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 1f2038a4420b..56b153ea5c56 100644
--- a
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color c
17.12.2020 21:45, Dmitry Osipenko пишет:
> 17.12.2020 21:21, Mikko Perttunen пишет:
>> On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
>>> Add suspend/resume and generic power domain support to the Host1x driver.
>>> This is required for enabling system-wide DVFS and supporting dynamic
>>> power manage
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +
1 file changed, 160 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.
Document new DVFS OPP table and power domain properties of the video
decoder engine.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 66 ++
From: siyanteng
When building cma_heap the following error shows up:
drivers/dma-buf/heaps/cma_heap.c:195:10: error: implicit declaration of
function 'vmap'; did you mean 'kmap'? [-Werror=implicit-function-declaration]
195 | vaddr = vmap(buffer->pages, buffer->pagecount, VM_MAP, PAGE_KERNEL);
On Thu, 17 Dec 2020 22:16:59 +0800,
Christian König wrote:
>
> Am 17.12.20 um 14:37 schrieb Chen Li:
> > On Thu, 17 Dec 2020 18:25:11 +0800,
> > Christian König wrote:
> >> Am 17.12.20 um 02:07 schrieb Chen Li:
> >>> On Wed, 16 Dec 2020 22:19:11 +0800,
> >>> Christian König wrote:
> Am 16.12.
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two scre
Allow lower core voltages on Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 32 ---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm/boot/dts/tegra20-ventana.dts
ind
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml| 134 +
1 file changed, 134 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dp
Make set_performance_state() callback optional in order to remove the
need from power domain drivers to implement a dummy callback. If callback
isn't implemented by a GENPD driver, then the performance state is passed
to the parent domain.
Signed-off-by: Dmitry Osipenko
---
drivers/base/power/do
Extend OPP API with dev_pm_opp_sync_regulators() function, which syncs
voltage state of regulators.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 42 ++
include/linux/pm_opp.h | 11 +++
2 files changed, 53 insertions(+)
diff --git a/
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