On Mon, Nov 09 2020 at 20:59, Ira Weiny wrote:
> On Tue, Nov 10, 2020 at 02:13:56AM +0100, Thomas Gleixner wrote:
> Also, we can convert the new memcpy_*_page() calls to kmap_local() as well.
> [For now my patch just uses kmap_atomic().]
>
> I've not looked at all of the patches in your latest vers
10.11.2020 23:32, Mark Brown пишет:
> On Tue, Nov 10, 2020 at 09:29:45PM +0100, Thierry Reding wrote:
>> On Thu, Nov 05, 2020 at 02:44:08AM +0300, Dmitry Osipenko wrote:
>
>>> + /*
>>> +* Voltage scaling is optional and trying to set voltage for a dummy
>>> +* regulator will error out.
>
11.11.2020 08:53, Viresh Kumar пишет:
>> +static int tegra_emc_opp_table_init(struct tegra_emc *emc)
>> +{
>> +struct opp_table *reg_opp_table = NULL, *clk_opp_table, *hw_opp_table;
>> +u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
>> +const char *rname = "core";
>> +int err;
chart
> ; Yuti Suresh Amonkar
>
> Subject: Re: [PATCH v2 6/6] drm/bridge: cdns-mhdp8546: Fix the interrupt
> enable/disable
>
> EXTERNAL MAIL
>
>
> On 14:27-20201110, Tomi Valkeinen wrote:
> > On 10/11/2020 12:27, Nikhil Devshatwar wrote:
> > > On 11:21-202
Fixes coccicheck warning:
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c:255:
36-43: WARNING opportunity for kmemdup
Signed-off-by: Tian Tao
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 27 ++-
1 file changed, 26 insertions(+), 1
Factor out clk initialization and make it resource-managed. This makes
easier to follow code and will help to make further changes cleaner.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 70 --
1 file changed, 47 insertions(+), 23 deletions(-)
10.11.2020 23:47, Thierry Reding пишет:
...
> tegra_soc_for_each_device
>
> I wonder if you copy/pasted this or if you got really lucky to mistype
> this all three times.
Copied of course :)
I added a special spell checking rule for this typo, but it does help
reliably.
...
>> +terga_soc_fo
Previously we were using count-weight of the T124 for T30 in order to
get EMC clock rate that was reasonable for T30. In fact the count-weight
should be x2 times smaller on T30, but then devfreq was producing a bit
too low EMC clock rate for ISO memory clients, like display controller
for example.
On Tue, Nov 10, 2020 at 03:14:45PM +0100, Daniel Vetter wrote:
> On Fri, Nov 06, 2020 at 12:39:53PM -0400, Jason Gunthorpe wrote:
> > On Fri, Nov 06, 2020 at 04:34:07PM +, Xiong, Jianxin wrote:
> >
> > > > The user could specify a length that is beyond the dma buf, can
> > > > the dma buf leng
On 11-11-20, 09:14, Dmitry Osipenko wrote:
> 11.11.2020 08:53, Viresh Kumar пишет:
> >> +static int tegra_emc_opp_table_init(struct tegra_emc *emc)
> >> +{
> >> + struct opp_table *reg_opp_table = NULL, *clk_opp_table, *hw_opp_table;
> >> + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
> >>
On 11-11-20, 04:14, Dmitry Osipenko wrote:
> +static int tegra_emc_opp_table_init(struct tegra_emc *emc)
> +{
> + struct opp_table *reg_opp_table = NULL, *clk_opp_table, *hw_opp_table;
> + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
> + const char *rname = "core";
> + int er
of_parse_phandle and of_find_device_by_node may return NULL
which cannot be checked by IS_ERR.
Signed-off-by: Wang Xiaojun
Reported-by: Hulk Robot
---
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_d
pm_runtime_get_sync will increment pm usage counter even it
failed. Forgetting to pm_runtime_put_noidle will result in
reference leak in hdmi_runtime_get, so we should fix it.
Fixes: ac7674567c620 ("drm: omapdrm: hdmi4: Allocate the omap_hdmi data
structure dynamically")
Signed-off-by: Zhang Qilo
On 2020-11-10 17:48, Will Deacon wrote:
On Fri, Oct 30, 2020 at 02:53:09PM +0530, Sai Prakash Ranjan wrote:
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed
On 2020-11-10 17:48, Will Deacon wrote:
On Fri, Oct 30, 2020 at 02:53:08PM +0530, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pg
11.11.2020 09:18, Viresh Kumar пишет:
> On 11-11-20, 09:14, Dmitry Osipenko wrote:
>> 11.11.2020 08:53, Viresh Kumar пишет:
+static int tegra_emc_opp_table_init(struct tegra_emc *emc)
+{
+ struct opp_table *reg_opp_table = NULL, *clk_opp_table, *hw_opp_table;
+ u32 hw_version
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig
> Am 10.11.2020 um 14:49 schrieb H. Nikolaus Schaller :
>
> Hi Tomi,
>
>> Am 09.11.2020 um 12:33 schrieb Tomi Valkeinen :
>>
>> On 09/11/2020 13:09, H. Nikolaus Schaller wrote:
>>
> I see.
> Anyways there is missing some simple thing which makes the driver not
> prepared/enabled.
11.11.2020 00:22, Dmitry Osipenko пишет:
> I added a special spell checking rule for this typo, but it does help
> reliably.
does *not*
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
The latency allowness is calculated based on buffering capabilities of
memory clients. Add FIFO sizes to the Tegra30 memory clients.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30.c | 66 ++
1 file changed, 66 insertions(+)
diff --git a/drivers/m
On 11-11-20, 04:14, Dmitry Osipenko wrote:
> The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use
> dev_pm_opp_set_clkname() instead.
>
> Suggested-by: Viresh Kumar
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra20-emc.c | 30 +++---
> 1 f
Hi Tomi,
> Am 09.11.2020 um 12:33 schrieb Tomi Valkeinen :
>
> On 09/11/2020 13:09, H. Nikolaus Schaller wrote:
>
I see.
Anyways there is missing some simple thing which makes the driver not
prepared/enabled.
Or is this related to VC?
>>>
>>> No, that's not related to the V
Le mar. 10 nov. 2020 à 9:56, Sam Ravnborg a écrit :
Hi Paul,
On Tue, Nov 10, 2020 at 08:50:22AM +, Paul Cercueil wrote:
Hi,
Le sam. 7 nov. 2020 à 20:33, Sam Ravnborg a
écrit :
> Hi Paul.
>
> On Thu, Nov 05, 2020 at 08:39:05AM +, Paul Cercueil wrote:
> > Increase the scaled
pm_runtime_get_sync will increment pm usage counter even it
failed. Forgetting to pm_runtime_put_noidle will result in
reference leak in hdmi_runtime_get, so we should fix it.
Fixes: c44991ce21bef ("drm: omapdrm: hdmi5: Allocate the omap_hdmi data
structure dynamically")
Signed-off-by: Zhang Qilo
On Thu, Nov 05, 2020 at 08:07:57PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 05.11.20 um 17:45 schrieb Maxime Ripard:
> > Many drivers reference the crtc->pointer in order to get the current CRTC
> > state in their atomic_begin or atomic_flush hooks, which would be the new
> > CRTC state in the
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 26 +-
1 file changed, 25 insertions(+), 1
This patch moves ACTMON driver away from generating OPP table by itself,
transitioning it to use the table which comes from device-tree. This
change breaks compatibility with older device-trees in order to bring
support for the interconnect framework to the driver. This is a mandatory
change which
Add EMC OPP DVFS table that will be used for dynamic scaling of memory
frequency/voltage. Update board device-trees with optional EMC core supply
and remove unsupported OPPs.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 7 ++
arch/arm/boot/dts/tegra20-colib
Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra124.dtsi | 25 +
1 file changed, 25 insertions(+)
di
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
dr
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.
Signed-o
Add devfreq support to the Tegra20 EMC driver. Memory utilization
statistics will be periodically polled from the memory controller and
appropriate minimum clock rate will be selected by the devfreq governor.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 3 +-
drivers/
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
Add modularization support to the Tegra30 EMC driver, which now can be
compiled as a loadable kernel module.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig | 2 +-
drivers/memory/tegra/mc.c | 3 +++
drivers/memory/tegra/tegra30-emc.c | 17 -
3 fi
> Am 11.11.2020 um 07:40 schrieb Tomi Valkeinen :
>
> On 10/11/2020 23:04, H. Nikolaus Schaller wrote:
>>
>>> Am 10.11.2020 um 17:52 schrieb Tomi Valkeinen :
>>>
>>> On 10/11/2020 18:49, H. Nikolaus Schaller wrote:
>>>
>>> I guess you have the same issue. It goes to dsi_bridge_mode_valid, the
On 11-11-20, 11:15, Viresh Kumar wrote:
> On 11-11-20, 04:14, Dmitry Osipenko wrote:
> > The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use
> > dev_pm_opp_set_clkname() instead.
> >
> > Suggested-by: Viresh Kumar
> > Signed-off-by: Dmitry Osipenko
> > ---
> > drivers/memory/tegra/
If mipi_dsi_driver_register() failed, platform_driver_unregister()
need be called.
Fixes: 210fcd9d9cf1 ("drm/panel: Add support for Panasonic VVX10F004B0")
Reported-by: Hulk Robot
Signed-off-by: Yang Yingliang
---
drivers/gpu/drm/panel/panel-simple.c | 4 +++-
1 file changed, 3 insertions(+), 1
10.11.2020 23:29, Thierry Reding пишет:
>> +/* legacy device-trees don't have OPP table */
>> +if (!device_property_present(dc->dev, "operating-points-v2"))
>> +return 0;
> "Legacy" is a bit confusing here. For one, no device trees currently
> have these tables and secondly, for
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory cli
Hi,
Le sam. 7 nov. 2020 à 20:33, Sam Ravnborg a écrit :
Hi Paul.
On Thu, Nov 05, 2020 at 08:39:05AM +, Paul Cercueil wrote:
Increase the scaled image's theorical width/height until we find a
configuration that has valid scaling coefficients, up to 102% of the
screen's resolution. This
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.
Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete ca
Correct typo in a stub of devm_tegra_memory_controller_get() to fix a
non-ARM kernel compile-testing.
Reported-by: Stephen Rothwell
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/mc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/soc/tegra/mc.h b/include/soc/
EMC driver will become mandatory after turning it into interconnect
provider because interconnect users, like display controller driver, will
fail to probe using newer device-trees that have interconnect properties.
Thus make EMC driver to probe even if timings are missing in device-tree.
Signed-o
This series brings initial support for memory interconnect to Tegra20,
Tegra30 and Tegra124 SoCs.
For the starter only display controllers and devfreq devices are getting
interconnect API support, others could be supported later on. The display
controllers have the biggest demand for interconnect
Add nvidia,memory-controller to the Tegra20 External Memory Controller
node. This allows to perform a direct lookup of the Memory Controller
instead of walking up the whole tree. This puts Tegra20 device-tree on
par with Tegra30+.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi
Fix the size of Tegra20 EMC registers, which should be twice bigger.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dts
10.11.2020 23:29, Thierry Reding пишет:
>> +
>> +dc->opp_table = dev_pm_opp_get_opp_table(dc->dev);
>> +if (IS_ERR(dc->opp_table))
>> +return dev_err_probe(dc->dev, PTR_ERR(dc->opp_table),
>> + "failed to prepare OPP table\n");
>> +
>> +if (of
pm_runtime_get_sync() will increment pm usage at first and it
will resume the device later. If runtime of the device has
error or device is in inaccessible state(or other error state),
resume operation will fail. If we do not call put operation to
decrease the reference, it will result in reference
> Am 10.11.2020 um 17:52 schrieb Tomi Valkeinen :
>
> On 10/11/2020 18:49, H. Nikolaus Schaller wrote:
>
> I guess you have the same issue. It goes to dsi_bridge_mode_valid, then
> __dsi_calc_config, and stays
> there finding good clocks.
Yes, I could trace it down to exactly this point.
So
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Remove unsupported EMC OPPs from board device-trees.
Note that ACTMON watches all memory interconnect paths, but we use a
single CPU-READ interconnect p
Remove tegra20-devfreq in order to replace it with a EMC_STAT based
devfreq driver. Previously we were going to use MC_STAT based
tegra20-devfreq driver because EMC_STAT wasn't working properly, but
now that problem is resolved. This resolves complications imposed by
the removed driver since it was
11.11.2020 08:45, Viresh Kumar пишет:
>> +put_reg_table:
>> +if (reg_opp_table)
> This won't be required after my other patchset and yeah it is a
> classic chicken and egg problem we have here :)
>
> Maybe you can fix them separately in 5.11 after everything is applied.
>
I already prepared
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Update board device-trees with optional EMC core supply and remove
unsupported OPPs.
Note that ACTMON watches all memory interconnect paths, but we use
pm_runtime_get_sync() will increment pm usage at first and it
will resume the device later. If runtime of the device has
error or device is in inaccessible state(or other error state),
resume operation will fail. If we do not call put operation to
decrease the reference, it will result in reference
On Fri 30 Oct 05:47 CDT 2020, Akhil P Oommen wrote:
> Add cooling-cells property and the cooling maps for the gpu tzones
> to support GPU cooling.
>
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Matthias Kaehlcke
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 30 +++---
Factor out clk initialization and make it resource-managed. This makes
easier to follow code and will help to make further changes cleaner.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30-emc.c | 70 --
1 file changed, 47 insertions(+), 23 deletions(-)
Remove IRQ number from error message since it doesn't add any useful
information, especially because this number is virtual.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/tegra/tegra20-emc.
This series of patches fixed several usage counter leaks refer to
pm_runtime_get_sync. Many callers forget to call pm_runtime_put_noidle
when pm_runtime_get_sync failed, and we fixed it.
Zhang Qilong (4):
drm: omapdrm: dsi: fix-reference-leak-in dsi_runtime_get.
drm: omapdrm: dss: fix referenc
The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use
dev_pm_opp_set_clkname() instead.
Suggested-by: Viresh Kumar
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git
On Tue, 2020-11-10 at 06:53 +0100, Sam Ravnborg wrote:
> Hi Liu Ying,
> On Tue, Nov 10, 2020 at 10:37:27AM +0800, Liu Ying wrote:
> > Hi Sam,
> >
> > On Wed, 2020-11-04 at 11:47 +0100, Sam Ravnborg wrote:
> > > Hi Liu Ying
> > >
> > > On Wed, Nov 04, 2020 at 04:03:37PM +0800, Liu Ying wrote:
> >
10.11.2020 23:50, Thierry Reding пишет:
> On Thu, Nov 05, 2020 at 02:44:15AM +0300, Dmitry Osipenko wrote:
> [...]
>> +static void tegra_pwm_deinit_opp_table(void *data)
>> +{
>> +struct device *dev = data;
>> +struct opp_table *opp_table;
>> +
>> +opp_table = dev_pm_opp_get_opp_table(d
Hi Yang,
On Wed, Nov 11, 2020 at 02:44:25PM +0800, Yang Yingliang wrote:
> If mipi_dsi_driver_register() failed, platform_driver_unregister()
> need be called.
>
> Fixes: 210fcd9d9cf1 ("drm/panel: Add support for Panasonic VVX10F004B0")
> Reported-by: Hulk Robot
> Signed-off-by: Yang Yingliang
On Tue, 10 Nov 2020, Alex Deucher wrote:
> On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/radeon/evergreen.c: In function ‘evergreen_gpu_init’:
> > drivers/gpu/drm/radeon/evergreen.c:1419: warning: Function param
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
- Added a WARN_ON() instead of drm_err. [Uma]
- Cosmetic changes. [Uma]
v3:
- 's/port_data/hdcp_port_data' [Ram]
- skip redund
This requires for HDCP 2.2 MST check link.
As for DP/HDMI shims check_2_2_link retrieves the connector
from dig_port, this is not sufficient or DP MST connector,
there can be multiple DP MST topology connector associated
with same dig_port.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by
Enable HDCP 2.2 over DP MST.
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once a
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
It is based upon the actual number of MST streams and size
of wired_cmd_repeater_auth_stream_req_in.
Excluding the size of hdcp_cmd_header.
v2:
hdcp_cmd_header size annotation nitpick. [Tomas]
Cc: Tomas Winkler
Cc: Ramalingam C
Ack
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul
Cc: Ramalingam C
Acked-by: Maarten Lankhorst
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
include/drm/drm_hdcp.h | 8 ++
Enable HDCP 1.4 DP MST stream encryption.
Enable stream encryption once encryption is enabled on
the DP transport driving the link for each stream which
has requested encryption.
Disable stream encryption for each stream that no longer
requires encryption before disabling HDCP encryption on
the l
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
Security f/w doesn't have any provision to mark the
stream_type for each stream separately, it just take
single input of stream_type while authentia
This is v5 version to test with IGT
https://patchwork.freedesktop.org/series/82987/
This has addressed the review comments from Ram.
It has been also tested manually with above IGT series.
[PATCH v5 11/17] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
has an Ack from Tomas to merge it via drm
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
v2:
- 's/port_data/hdcp_port_data'. [Ram]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
S
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This i
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving th
Enable HDCP 1.4 over DP MST for Gen12.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/dr
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Hi Michael,
On Mon, 2 Nov 2020 05:19:06 -0500 "Michael S. Tsirkin" wrote:
>
> On Mon, Nov 02, 2020 at 12:43:27PM +1100, Stephen Rothwell wrote:
> >
> > After merging the drm-misc tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> > In file included from drivers/
20. 11. 11. 오후 12:04에 Inki Dae 이(가) 쓴 글:
>
>
> 20. 11. 10. 오후 5:13에 Michael Tretter 이(가) 쓴 글:
>> On Mon, 09 Nov 2020 12:15:39 +0900, Inki Dae wrote:
>>> 20. 9. 11. 오후 10:53에 Michael Tretter 이(가) 쓴 글:
This is v2 of the series to convert the Exynos MIPI DSI driver into a drm
bridge and
20. 11. 10. 오후 5:13에 Michael Tretter 이(가) 쓴 글:
> On Mon, 09 Nov 2020 12:15:39 +0900, Inki Dae wrote:
>> 20. 9. 11. 오후 10:53에 Michael Tretter 이(가) 쓴 글:
>>> This is v2 of the series to convert the Exynos MIPI DSI driver into a drm
>>> bridge and make it usable with other drivers. Although the drive
On 2020.11.04 17:45:32 +0530, Deepak R Varma wrote:
> idr_init() uses base 0 which is an invalid identifier. The new function
> idr_init_base allows IDR to set the ID lookup from base 1. This avoids
> all lookups that otherwise starts from 0 since 0 is always unused.
>
> References: commit 6ce711f
Hi Dmitry,
On 11/11/20 10:14 AM, Dmitry Osipenko wrote:
> Add devfreq support to the Tegra20 EMC driver. Memory utilization
> statistics will be periodically polled from the memory controller and
> appropriate minimum clock rate will be selected by the devfreq governor.
>
> Signed-off-by: Dmitry
Hi,
On Mon, Nov 2, 2020 at 9:08 AM Bjorn Andersson
wrote:
>
> On Fri 02 Oct 15:42 CDT 2020, Doug Anderson wrote:
>
> > Hi,
> >
> > On Wed, Sep 30, 2020 at 3:40 PM Bjorn Andersson
> > wrote:
> > >
> > > While the signal on GPIO4 to drive the backlight controller indeed is
> > > pulse width modula
On Tue, Nov 10, 2020 at 2:32 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/sumo_dpm.c:81:25: warning: no previous prototype for
> ‘sumo_get_pi’ [-Wmissing-prototypes]
> 81 | struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
>
On Tue, Nov 10, 2020 at 2:32 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/ni.c: In function ‘cayman_gpu_init’:
> drivers/gpu/drm/radeon/ni.c:880:6: warning: variable ‘mc_shared_chmap’ set
> but not used [-Wunused-but-set-variable]
>
> Cc: A
On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/evergreen_dma.c:112: warning: Function parameter or
> member 'resv' not described in 'evergreen_copy_dma'
> drivers/gpu/drm/radeon/evergreen_dma.c:112: warning: Exces
On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/evergreen_cs.c:1026: warning: Function parameter or
> member 'p' not described in 'evergreen_cs_packet_parse_vline'
> drivers/gpu/drm/radeon/evergreen_cs.c:1026: warn
On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/cik_sdma.c:949: warning: Function parameter or member
> 'ring' not described in 'cik_dma_vm_flush'
> drivers/gpu/drm/radeon/cik_sdma.c:949: warning: Function paramete
On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/r600_cs.c:793: warning: Function parameter or member
> 'p' not described in 'r600_cs_packet_parse_vline'
> drivers/gpu/drm/radeon/r600_cs.c:793: warning: Excess funct
On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/r100.c:163: warning: Function parameter or member
> 'async' not described in 'r100_page_flip'
> drivers/gpu/drm/radeon/r100.c:848: warning: Function parameter or memb
On Tue, Nov 10, 2020 at 2:31 PM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/radeon/radeon_mn.c:51: warning: Function parameter or member
> 'cur_seq' not described in 'radeon_mn_invalidate'
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Ai
The SPI DCS code was a bit hard to understand as the
device accepts 9-bit transfers packed into 16-bit words
with the most significant bit in bit 9 of the
16-bit word. Add some clarifying comments.
Cc: Stephan Gerhold
Cc: Paweł Chmiel
Signed-off-by: Linus Walleij
---
drivers/gpu/drm/panel/pane
The panel can be connected using 3WIRE, then it is
however necessary that the flag SPI_3WIRE is preserved
on the device, as we set this from generic device tree
parsing code (or similar). Just |= the SPI mode.
Cc: Stephan Gerhold
Cc: Paweł Chmiel
Signed-off-by: Linus Walleij
---
drivers/gpu/dr
Copy over the width/height in millimeters to the
(somewhat redundant) display info, and set up the
bus format and bus flags for the display.
When used as DPI this display requires DE to be
active low and pixel data to be output on the
negative edge. It might be that it was previously
used with a d
These improvements to the Samsung s6e63m0 makes SPI
writing and reading to the panel simpler, and add some
support required by the Samsung GT-I9070.
Tested and working fine on the Samsung GT-I9070 mobile
phone with the MCDE display controller in DPI mode.
Linus Walleij (5):
drm/panel: s6e63m0:
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