Hi Dave, Daniel,
Fixes for 5.9.
The following changes since commit dc100bc8fae59aafd2ea2e1a1a43ef1f65f8a8bc:
Merge tag 'drm-msm-next-2020-07-30' of https://gitlab.freedesktop.org/drm/msm
into drm-next (2020-08-05 08:05:31 +1000)
are available in the Git repository at:
git://people.freedes
On Fri, Aug 7, 2020 at 6:10 AM Kalyan Thota wrote:
>
> In TEST_ONLY commit, rm global_state will duplicate the
> object and request for new reservations, once they pass
> then the new state will be swapped with the old and will
> be available for the Atomic Commit.
>
> This patch fixes some of mis
Since I'm almost certain I didn't get capability checking right for
pre-volta chipsets, let's start logging any caps we find to make things
like this obvious in the future.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 10 ++
1 file changed, 10 insertions(+)
di
Not entirely sure why this never came up when I originally tested this
(maybe some BIOSes already have this setup?) but the ->caps_init vfunc
appears to cause the display engine to throw an exception on driver
init, at least on my ThinkPad P72:
nouveau :01:00.0: disp: chid 0 mthd 008c data 000
The DU driver handles non-visible planes (fully clipped by the display's
boundaries) by considering them as disabled. It thus disables the plane
at the hardware level when the plane if moved off-screen. However, if
the plane was previously disabled and is non-visible when it gets
enabled, the attem
On Tue, Aug 04, 2020 at 11:33:51AM +0200, dan...@ffwll.ch wrote:
> On Sat, Aug 01, 2020 at 04:30:23PM -0300, Melissa Wen wrote:
> > On Wed, Jul 29, 2020 at 12:22 PM Sidong Yang wrote:
> > >
> > > This patch modifies function call sequence in commit tail. This is for
> > > the problem that raised w
Hi Daniel.
On Fri, Aug 07, 2020 at 10:36:34PM +0200, Daniel Vetter wrote:
> On Fri, Aug 7, 2020 at 8:05 PM Sam Ravnborg wrote:
> >
> > When building imgag200 for the alpha architecture it fails like this:
> > mgag200_drv.c:233:9: error: implicit declaration of function ‘vmalloc’
> > 233 | bios
On Fri, Aug 7, 2020 at 8:05 PM Sam Ravnborg wrote:
>
> When building imgag200 for the alpha architecture it fails like this:
> mgag200_drv.c:233:9: error: implicit declaration of function ‘vmalloc’
> 233 | bios = vmalloc(size);
> | ^~~
> | kmalloc
>
> When buildi
On Mon, Aug 3, 2020 at 12:36 PM Jordan Crouse wrote:
>
> Add support for allocating private address space instances. Targets that
> support per-context pagetables should implement their own function to
> allocate private address spaces.
>
> The default will return a pointer to the global address s
On Mon, Aug 3, 2020 at 12:36 PM Jordan Crouse wrote:
>
> Add support to create a io-pgtable for use by targets that support
> per-instance pagetables. In order to support per-instance pagetables the
> GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
> split pagetables enabl
Applied. Thanks!
Alex
On Thu, Aug 6, 2020 at 1:22 PM Sandeep Raghuraman wrote:
>
> This fixes the bug I reported here:
> https://bugzilla.kernel.org/show_bug.cgi?id=208839
>
> Reproducing bug report here:
> After hibernating and resuming, DPM is not enabled. This remains the case
> even if yo
On Thu, Jun 11, 2020 at 2:59 AM Tomeu Vizoso wrote:
>
> Bifrost devices do support the flush reduction feature, so on first job
> submit we were trying to read the register while still powered off.
>
> If the GPU is powered off, the feature doesn't bring any benefit, so
> don't try to read.
>
> Si
On Tue, Aug 4, 2020 at 5:32 PM Bas Nieuwenhuizen
wrote:
> This expose modifier support on GFX9+.
>
> Only modifiers that can be rendered on the current GPU are
> added. This is to reduce the number of modifiers exposed.
>
> The HW could expose more, but the best mechanism to decide
> what to expo
On Mon, Aug 3, 2020 at 11:45 PM Sai Prakash Ranjan
wrote:
>
> MSM bus scaling has moved on to use interconnect framework
> and downstream bus scaling apis are not present anymore.
> Remove them as they are nop anyways in the current code,
> no functional change.
>
thanks, nice cleanup.. I'm pulli
When building imgag200 for the alpha architecture it fails like this:
mgag200_drv.c:233:9: error: implicit declaration of function ‘vmalloc’
233 | bios = vmalloc(size);
| ^~~
| kmalloc
When building for other architectures vmalloc.h is pulled in via some
other he
On Sun, Jun 14, 2020 at 12:36 AM Navid Emamdoost
wrote:
>
> in panfrost_perfcnt_enable_locked, pm_runtime_get_sync is called which
> increments the counter even in case of failure, leading to incorrect
> ref count. In case of failure, decrement the ref count before returning.
>
> Signed-off-by: Na
On Fri, Jul 10, 2020 at 3:54 AM Clément Péron wrote:
>
> Hi,
>
> This serie cleans and adds regulator support to Panfrost devfreq.
> This is mostly based on comment for the freshly introduced lima
> devfreq.
>
> We need to add regulator support because on Allwinner the GPU OPP
> table defines both
On Fri, Aug 7, 2020 at 4:02 PM Thomas Zimmermann wrote:
>
> Hi
>
> Am 07.08.20 um 15:12 schrieb Daniel Vetter:
> > On Fri, Aug 07, 2020 at 01:10:22PM +0200, Thomas Zimmermann wrote:
> >> The malidp driver uses GEM object functions for callbacks. Fix it to
> >> use them internally as well.
> >>
> >
On 2020-08-07 08:27, Randy Dunlap wrote:
On 8/7/20 12:17 AM, Tanmay Shah wrote:
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index ea3c4d094d09..cc1392b29022 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -60,6 +60,7 @@ config DRM_MSM_HDMI
On Fri, Aug 7, 2020 at 8:27 AM Randy Dunlap wrote:
>
> On 8/7/20 12:17 AM, Tanmay Shah wrote:
> > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> > index ea3c4d094d09..cc1392b29022 100644
> > --- a/drivers/gpu/drm/msm/Kconfig
> > +++ b/drivers/gpu/drm/msm/Kconfig
> > @@ -6
On Fri, Aug 7, 2020 at 8:37 AM Randy Dunlap wrote:
>
> On 8/7/20 12:17 AM, Tanmay Shah wrote:
> > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> > index 6deaa7d01654..ea3c4d094d09 100644
> > --- a/drivers/gpu/drm/msm/Kconfig
> > +++ b/drivers/gpu/drm/msm/Kconfig
> > @@ -5
On 2020-08-07 4:52 a.m., dan...@ffwll.ch wrote:
On Thu, Jul 30, 2020 at 04:36:42PM -0400, Nicholas Kazlauskas wrote:
@@ -440,7 +431,7 @@ struct dm_crtc_state {
#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
struct dm_atomic_state {
- struct drm_private_stat
On 2020-08-07 4:30 a.m., dan...@ffwll.ch wrote:
On Thu, Jul 30, 2020 at 04:36:38PM -0400, Nicholas Kazlauskas wrote:
[Why]
We're racing with userspace as the flags could potentially change
from when we acquired and validated them in commit_check.
Uh ... I didn't know these could change. I thin
Hi,
Is it possible to have X handle input events, but not actually unblank
the screen upon input events when dpms is enabled?
Our use case (in Maemo Leste, GNU/Linux+Debian smartphone OS) is
reporting physical volume buttons to X clients when the device is
locked. When the device is locked, the s
On 2020-08-07 4:34 a.m., dan...@ffwll.ch wrote:
On Thu, Jul 30, 2020 at 04:36:40PM -0400, Nicholas Kazlauskas wrote:
[Why]
MEDIUM or FULL updates can require global validation or affect
bandwidth. By treating these all simply as surface updates we aren't
actually passing this through DC global v
https://bugzilla.kernel.org/show_bug.cgi?id=208835
--- Comment #2 from sevenever (sevene...@gmail.com) ---
(In reply to Alex Deucher from comment #1)
> Does it work without the external display connected?
Tried several times, Looks like no problem without the external display
connected.
btw, I h
Hi
Am 07.08.20 um 15:12 schrieb Daniel Vetter:
> On Fri, Aug 07, 2020 at 01:10:22PM +0200, Thomas Zimmermann wrote:
>> The malidp driver uses GEM object functions for callbacks. Fix it to
>> use them internally as well.
>>
>> Signed-off-by: Thomas Zimmermann
>> Fixes: ecdd6474644f ("drm/malidp: U
Hi Swapnil,
On 06/08/2020 14:34, Swapnil Jakhade wrote:
> Add a new DRM bridge driver for Cadence MHDP DPTX IP used in TI J721e SoC.
> MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
> embedded Display Port (eDP) standards. It integrates uCPU running the
> embedded Firmw
Hi everybody,
in amdgpu we got the following issue which I'm seeking advise how to cleanly
handle it.
We have a bunch of trace points which are related to the VM subsystem and
executed in either a work item, kthread or foreign process context.
Now tracing the pid of the context which we are ex
Trace something useful instead of the pid of a kernel thread here.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 5da20fc
On Fri, Aug 07, 2020 at 01:10:22PM +0200, Thomas Zimmermann wrote:
> The malidp driver uses GEM object functions for callbacks. Fix it to
> use them internally as well.
>
> Signed-off-by: Thomas Zimmermann
> Fixes: ecdd6474644f ("drm/malidp: Use GEM CMA object functions")
> Cc: Thomas Zimmermann
On Fri, Aug 07, 2020 at 12:55:01PM +0200, Gerd Hoffmann wrote:
> qemu 5.0 introduces a new qxl hardware revision 5. Unlike revision 4
> (and below) the device doesn't switch back into vga compatibility mode
> when someone touches the vga ports. So we don't have to reserve the
> vga ports any more
On Fri, Aug 07, 2020 at 12:54:29PM +0200, Gerd Hoffmann wrote:
> When going through a disable/enable cycle without changing the
> framebuffer the optimization added by commit 3954ff10e06e ("drm/virtio:
> skip set_scanout if framebuffer didn't change") causes the screen stay
> blank. Add a bool to
On Fri, Aug 07, 2020 at 12:38:02PM +0300, Pekka Paalanen wrote:
> On Fri, 7 Aug 2020 11:07:06 +0200
> Daniel Vetter wrote:
>
> > On Thu, Aug 06, 2020 at 10:33:31AM +, Simon Ser wrote:
> > > Some drivers may expose primary planes compatible with multiple CRTCs.
> > > Make this clear in the doc
On Fri, Aug 07, 2020 at 09:33:16AM +, Simon Ser wrote:
> On Friday, August 7, 2020 11:07 AM, Daniel Vetter wrote:
> > On Thu, Aug 06, 2020 at 10:33:31AM +, Simon Ser wrote:
> > > Some drivers may expose primary planes compatible with multiple CRTCs.
> > > Make this clear in the docs: the c
On Wed, Jul 22, 2020 at 01:18:51PM +0800, Xin He wrote:
> Before setting shmem->pages to NULL, kfree() should
> be called.
> sg_free_table(shmem->pages);
> + kfree(shmem->pages);
> shmem->pages = NULL;
Pushed to drm-misc-fixes.
than
> On Aug 6, 2020, at 9:30 PM, Dave Airlie wrote:
>
> On Fri, 7 Aug 2020 at 14:03, Dave Airlie wrote:
>>
>> On Fri, 7 Aug 2020 at 11:13, Rodrigo Vivi wrote:
>>>
>>> From: Rodrigo Vivi
>>>
>>> These are missed cases that I just identified with allyesconfig build.
>>>
>>
>> Is this agains
Am 07.08.20 um 01:34 schrieb Dave Airlie:
From: Dave Airlie
This moves the io lru tracking into the driver allocated structure.
Probably need to consider if we can move more stuff in there around the
nouveau only io_lru functionality.
I think we can even go much further than this. The whole
On Tue, Jul 21, 2020 at 06:16:47PM +0800, Xin He wrote:
> From: Qi Liu
>
> We should put the reference count of the fence after calling
> virtio_gpu_cmd_submit(). So add the missing dma_fence_put().
> virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
> vfpriv->ctx_
On Fri, Aug 07, 2020 at 12:33:30PM +0100, Mark Brown wrote:
> On Thu, Aug 06, 2020 at 08:19:32PM +0200, Krzysztof Kozlowski wrote:
>
> > I intend to take it through Samsung SoC tree so all Acks are welcomed.
>
> Any issue with me applying the ASoC bits and sending you a branch? This
> seems like
On Thu, Aug 06, 2020 at 08:19:32PM +0200, Krzysztof Kozlowski wrote:
> I intend to take it through Samsung SoC tree so all Acks are welcomed.
Any issue with me applying the ASoC bits and sending you a branch? This
seems like it might run into some of the subsystem wide cleanups we've
got going o
Em Fri, 7 Aug 2020 10:59:43 +0200
Sam Ravnborg escreveu:
> Hi Mauro.
>
> >
> > I know. What can be done is to send a diff at patch 00/xx with
> > the entire history for each driver folded, in order to easy
> > for reviewers.
> Personnaly this would be preferred as I assume the history is a lo
On Wed, Aug 05, 2020 at 09:43:42AM -0400, Michael S. Tsirkin wrote:
> Since gpu is a modern-only device,
> tag config space fields as having little endian-ness.
>
> Signed-off-by: Michael S. Tsirkin
> Reviewed-by: Cornelia Huck
Reviewed-by: Gerd Hoffmann
__
On Wed, Aug 05, 2020 at 09:44:48AM -0400, Michael S. Tsirkin wrote:
> Virtgpu is modern-only. Use LE accessors for config space.
>
> Signed-off-by: Michael S. Tsirkin
Reviewed-by: Gerd Hoffmann
___
dri-devel mailing list
dri-devel@lists.freedesktop.o
The malidp driver uses GEM object functions for callbacks. Fix it to
use them internally as well.
Signed-off-by: Thomas Zimmermann
Fixes: ecdd6474644f ("drm/malidp: Use GEM CMA object functions")
Cc: Thomas Zimmermann
Cc: Emil Velikov
Cc: Liviu Dudau
Cc: Brian Starkey
---
drivers/gpu/drm/arm
qemu 5.0 introduces a new qxl hardware revision 5. Unlike revision 4
(and below) the device doesn't switch back into vga compatibility mode
when someone touches the vga ports. So we don't have to reserve the
vga ports any more to avoid that happening.
Signed-off-by: Gerd Hoffmann
---
drivers/g
When going through a disable/enable cycle without changing the
framebuffer the optimization added by commit 3954ff10e06e ("drm/virtio:
skip set_scanout if framebuffer didn't change") causes the screen stay
blank. Add a bool to force an update to fix that.
Cc: 1882...@bugs.launchpad.net
Fixes: 395
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
F
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the serires (Paulo)
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
Signed-off-by: Karthik B S
Signed-off-by: Vandita Kulkarni
---
drivers/gpu
Add the details of the implementation of asynchronous flips for i915.
Signed-off-by: Karthik B S
Signed-off-by: Vandita Kulkarni
---
Documentation/gpu/i915.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 33cc6ddf8f64..8
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add check for changes in OFFSET, FBC, RC(Paulo)
v3: -Remov
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
Signed-off-by: Karthik B S
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/intel_sprite.c | 25 ++
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
v4: -Add separate plane hook for async flip case (Ville)
v5: -Rebased.
v6: -Move the plane hook to separate patch. (Paulo)
-Remov
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: -Few patches have been squashed and patches have been
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once
On Fri, 7 Aug 2020 11:07:06 +0200
Daniel Vetter wrote:
> On Thu, Aug 06, 2020 at 10:33:31AM +, Simon Ser wrote:
> > Some drivers may expose primary planes compatible with multiple CRTCs.
> > Make this clear in the docs: the current wording may be misunderstood as
> > "exactly one primary plan
Den 31.07.2020 14.51, skrev Oleksandr Andrushchenko:
> From: Oleksandr Andrushchenko
>
> Add YUYV to supported formats, so the frontend can work with the
> formats used by cameras and other HW.
>
> Signed-off-by: Oleksandr Andrushchenko
> ---
Acked-by: Noralf Trønnes
___
Den 31.07.2020 14.51, skrev Oleksandr Andrushchenko:
> From: Oleksandr Andrushchenko
>
> While importing a dmabuf it is possible that the data of the buffer
> is put with offset which is indicated by the SGT offset.
> Respect the offset value and forward it to the backend.
>
> Signed-off-by: O
On Friday, August 7, 2020 11:07 AM, Daniel Vetter wrote:
> On Thu, Aug 06, 2020 at 10:33:31AM +, Simon Ser wrote:
> > Some drivers may expose primary planes compatible with multiple CRTCs.
> > Make this clear in the docs: the current wording may be misunderstood as
> > "exactly one primary pla
Am 07.08.20 um 01:34 schrieb Dave Airlie:
From: Dave Airlie
This is a bit more involved that it looked, the range manager
needs accessors adding and amdgpu needs a bit of a refactor.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 21 ---
drivers/gpu/drm/amd/amdgpu/amdgpu
Am 07.08.20 um 01:34 schrieb Dave Airlie:
From: Dave Airlie
There is no need for that now since it's embedded.
Signed-off-by: Dave Airlie
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 11 +++
Am 07.08.20 um 01:34 schrieb Dave Airlie:
From: Dave Airlie
Christian suggested this and it makes sense.
Signed-off-by: Dave Airlie
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 21 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 19 +
On Thu, Aug 06, 2020 at 08:17:05AM -0300, Melissa Wen wrote:
> VKMS needs vblank interrupts enabled to capture CRC. When vblank is
> disabled, tests like kms_cursor_crc and kms_pipe_crc_basic getting stuck
> waiting for a capture that will not occur until vkms wakes up. This patch
> adds a helper t
On Thu, Aug 06, 2020 at 10:33:31AM +, Simon Ser wrote:
> Some drivers may expose primary planes compatible with multiple CRTCs.
> Make this clear in the docs: the current wording may be misunderstood as
> "exactly one primary plane per CRTC".
>
> Signed-off-by: Simon Ser
> Cc: Daniel Vetter
Hi Mauro.
>
> I know. What can be done is to send a diff at patch 00/xx with
> the entire history for each driver folded, in order to easy
> for reviewers.
Personnaly this would be preferred as I assume the history is a lot of
forth and back rather than incremental logical changes.
No promises o
On Wed, Aug 05, 2020 at 08:48:34AM -0700, Rob Clark wrote:
> On Wed, Aug 5, 2020 at 6:34 AM Kalyan Thota wrote:
> >
> > In TEST_ONLY commit, rm global_state will duplicate the
> > object and request for new reservations, once they pass
> > then the new state will be swapped with the old and will
>
On Wed, Aug 05, 2020 at 01:42:27PM +0100, Colin King wrote:
> From: Colin Ian King
>
> There a handful of spelling mistakes. fix them.
>
> Signed-off-by: Colin Ian King
Queued up for 5.10, should show up in linux-next right after the merge
window closes.
-Daniel
> ---
> drivers/gpu/drm/gma50
On Thu, Jul 30, 2020 at 04:36:42PM -0400, Nicholas Kazlauskas wrote:
> @@ -440,7 +431,7 @@ struct dm_crtc_state {
> #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
>
> struct dm_atomic_state {
> - struct drm_private_state base;
> + struct drm_atomic_state base;
>
On Wed, Aug 05, 2020 at 12:54:28PM +0200, Thomas Zimmermann wrote:
> The ast HW cursor requires the primary plane and CRTC to display at
> a valid mode and format. This is not the case while switching
> display modes, which can lead to the screen turing permanently dark.
>
> As a workaround, the a
On Thu, Jul 30, 2020 at 04:36:42PM -0400, Nicholas Kazlauskas wrote:
> [Why]
> DM atomic check was structured in a way that we required old DC state
> in order to dynamically add and remove planes and streams from the
> context to build the DC state context for validation.
>
> DRM private objects
On Thu, Jul 30, 2020 at 04:36:40PM -0400, Nicholas Kazlauskas wrote:
> [Why]
> MEDIUM or FULL updates can require global validation or affect
> bandwidth. By treating these all simply as surface updates we aren't
> actually passing this through DC global validation.
>
> [How]
> There's currently n
On Thu, Jul 30, 2020 at 04:36:38PM -0400, Nicholas Kazlauskas wrote:
> [Why]
> We're racing with userspace as the flags could potentially change
> from when we acquired and validated them in commit_check.
Uh ... I didn't know these could change. I think my comments on Bas'
series are even more rel
On Thu, Jul 30, 2020 at 04:36:35PM -0400, Nicholas Kazlauskas wrote:
> Based on the analysis of the bug from [1] the best course of action seems
> to be swapping off of DRM private objects back to subclassing DRM atomic
> state instead.
>
> This patch series implements this change, but not yet the
On Thu, Jul 30, 2020 at 04:36:36PM -0400, Nicholas Kazlauskas wrote:
> [Why]
> Store these in advance so we can reuse them later in commit_tail without
> having to reserve the fbo again.
>
> These will also be used for checking for tiling changes when deciding
> to reset the plane or not.
I've al
On Mon, Jul 20, 2020 at 09:25:21PM -0700, Alexandru Stan wrote:
> Some displays need the low end of the curve cropped in order to make
> them happy. In that case we still want to have the 0% point, even though
> anything between 0% and 5%(example) would be skipped.
>
> Signed-off-by: Alexandru Sta
Add DP device node on sc7180.
Changes in v2:
- Add assigned-clocks and assigned-clock-parents
- Remove cell-index and pixel_rcg
- Change compatible to qcom,sc7180-dp
Changes in v3:
- Update commit text
- Make DP child node of MDSS
- Remove data-lanes property from SOC dts
- Disable DP node in SO
Add a new DRM bridge driver for Cadence MHDP DPTX IP used in TI J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes a DP
On 2020-08-05 21:18, Rob Clark wrote:
On Wed, Aug 5, 2020 at 6:34 AM Kalyan Thota
wrote:
In TEST_ONLY commit, rm global_state will duplicate the
object and request for new reservations, once they pass
then the new state will be swapped with the old and will
be available for the Atomic Commit.
Xin He 于2020年7月21日周二 下午6:17写道：
>
> From: Qi Liu
>
> We should put the reference count of the fence after calling
> virtio_gpu_cmd_submit(). So add the missing dma_fence_put().
>
> Fixes: 2cd7b6f08bc4 ("drm/virtio: add in/out fence support for explicit
> synchronization")
> Co-developed-by: Xin H
Hello.
Commit 2ddef17678bc2ea1 ("drm/ttm: make TT creation purely optional v3") broke
vmwgfx .
At first I suspected it is "drm/atomic-helper: reset vblank on crtc reset" or
around that,
but bisection said it is not. I have no idea what is going on. Please have a
look.
--- Crash pattern 1 ---
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/Kconfig | 13 +
drivers/gpu/drm/bridge/M
On 2020/08/07 0:39, Daniel Vetter wrote:
> On Thu, Aug 6, 2020 at 5:28 PM Christian König
> wrote:
>>
>> My best guess is that you are facing two separate bugs here.
>>
>> Crash #1 is somehow related to CRTCs and might even be cause by the
>> atomic-helper change you noted below.
>
> Yeah, and I
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../bindings/display/bridge/cdns,mhdp.yaml| 139 ++
1 fi
This patch series adds new DRM bridge driver for Cadence MHDP DPI/DP
bridge. The Cadence Display Port IP is also referred as MHDP (Mobile High
Definition Link, High-Definition Multimedia Interface, Display Port).
Cadence Display Port complies with VESA DisplayPort (DP) and embedded
Display Port (eD
Em Thu, 6 Aug 2020 12:24:40 -0700
John Stultz escreveu:
> On Wed, Aug 5, 2020 at 1:51 AM Mauro Carvalho Chehab
> wrote:
> > I've been working to get upstream support for the DRM driver on HiKey 970.
> >
> > While the patches are not ready yet for upstream merge, I'm placing
> > what I've sone so
, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Dave-Airlie/drm-amdgpu-ttm-move-vram-gtt-mgr-allocations-to-mman/20200807-083526
b
From: Chandan Uddaraju
Add the needed DP PLL specific files to support
display port interface on msm targets.
The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.
Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DE
From: Chandan Uddaraju
The constant N value (0x8000) is used by i915 DP
driver. Define this value in dp helper header file
to use in multiple Display Port drivers. Change
i915 driver accordingly.
Change in v6: Change commit message
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Sig
From: Jeykumar Sankaran
Add display port support in DPU by creating hooks
for DP encoder enumeration and encoder mode
initialization.
changes in v2:
- rebase on [2] (Sean Paul)
- remove unwanted error checks and
switch cases (Jordan Crouse)
[1] https://lwn.net/Articles
These patches add Display-Port driver on SnapDragon/msm hardware.
This series also contains device-tree bindings for msm DP driver.
It also contains Makefile and Kconfig changes to compile msm DP driver.
The block diagram of DP driver is shown below:
+-+
Configure HPD registers in DP controller and
enable HPD interrupt.
Add interrupt to handle HPD connect and disconnect events.
Changes in v8: None
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18
drivers/gpu/drm/msm/dp/dp_catalog.c | 63 --
dri
Am 06.08.20 um 20:50 schrieb Roland Scheidegger:
Am 06.08.20 um 17:28 schrieb Christian König:
My best guess is that you are facing two separate bugs here.
Crash #1 is somehow related to CRTCs and might even be cause by the
atomic-helper change you noted below.
Crash #2 is caused because vmw_b
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