On 04.07.2020 11:24, Vinay Simha BN wrote:
> This driver is tested with two panels individually with Apq8016-IFC6309 board
> https://protect2.fireeye.com/url?k=fe87a8ec-a3e0ecca-fe8623a3-0cc47a31384a-ffbc547df1141490&q=1&u=https%3A%2F%2Fwww.inforcecomputing.com%2Fproducts%2Fsingle-board-computers
On Mon, Jul 06, 2020 at 04:21:38PM +0530, Suraj Upadhyay wrote:
> Hii Maintainers,
> I recently came across this list of janatorial tasks
> for starters on DRM subsystem [1]. One of the tasks is replacing
> conventional dmesg macros (like dev_info(), dev_warn() and dev_err())
> with DRM dmesg
On Fri, Jul 03, 2020 at 08:45:43PM +0200, Sam Ravnborg wrote:
> Introduce the backlight_get_brightness() helper in all
> video/backlight/* drivers.
> This simplifies the code and align the implementation of the
> update_status() operation across the different backlight drivers.
>
> Some of the dri
On Fri, Jul 03, 2020 at 08:45:28PM +0200, Sam Ravnborg wrote:
> The backlight support has two properties that express the state:
> - power
> - state
Tiny nit, but please add "fb_blank" here too, commit message doesn't match
the code anymore. With that:
Reviewed-by: Daniel Vetter
>
> It is un-d
On 7/6/2020 9:40 PM, Matthias Kaehlcke wrote:
On Thu, Jul 02, 2020 at 04:39:09PM +0530, Rajendra Nayak wrote:
On SDM845 and SC7180 DSI needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
https://bugzilla.kernel.org/show_bug.cgi?id=207383
Christopher Snowhill (kod...@gmail.com) changed:
What|Removed |Added
CC||kod...@gmail.com
On Tue, Jun 30, 2020 at 1:25 AM Maxime Ripard wrote:
>
> Hi Eric,
>
> On Thu, Jun 11, 2020 at 03:36:45PM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > This is another part of the rpi4 HDMI series that got promoted to a
> > series of its own to try to reduce the main one.
> >
> > This rework is neede
https://bugzilla.kernel.org/show_bug.cgi?id=207383
--- Comment #42 from Duncan (1i5t5.dun...@cox.net) ---
(In reply to Alex Deucher from comment #40)
> Does this patch help?
No. v5.7 with the patch applied gave me the same graphics freeze, with the
usual log trace confirming it's _this_ bug.
Si
https://bugzilla.kernel.org/show_bug.cgi?id=207383
--- Comment #41 from Duncan (1i5t5.dun...@cox.net) ---
(In reply to Alex Deucher from comment #40)
> Does this patch help?
Booted to v5.7 with it applied now. We'll see. Since the bug can take awhile
to trigger on my hardware, if the patch fixe
Hi, Dennis:
Dennis YC Hsieh 於 2020年7月6日 週一 下午3:20寫道：
>
> Add clear parameter to let client decide if
> event should be clear to 0 after GCE receive it.
>
> Fixes: 2f965be7f9008 ("drm/mediatek: apply CMDQ control flow")
I think this patch include two things, one is bug fix, another is
changing in
Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the
Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
Also add support for 10-bit 4:4:4 format while at it.
V2: Added NV30 support
Signed-off-by: Jonas Karlman
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.
Hi,
This series adds support for displaying 10-bit 4:2:0 and 4:2:2 formats produced
by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
Also include 10-bit 4:4:4 support since VOP can support that also.
First patch adds new fourcc 10-bit YUV formats with 4:2:2/4:4:4 sub-sa
DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
variant of NV15, a 10-bit 2-plane YUV format that has no padding between
components. Instead, luminance and chrominance samples are grouped into 4s
so that each group is packed into an integer number of bytes:
= UVUV =
https://bugzilla.kernel.org/show_bug.cgi?id=208443
mikkl (ironmi...@gmx.net) changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|-
Hi,
On 6/22/20 9:57 AM, Uwe Kleine-König wrote:
On Sat, Jun 20, 2020 at 02:17:54PM +0200, Hans de Goede wrote:
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v3:
- Add Andy
Hi,
On 6/22/20 9:55 AM, Uwe Kleine-König wrote:
Hello,
[adding Shobhit Kumar to Cc who is the author
of this driver according to the comment on the top of the driver]
On Sat, Jun 20, 2020 at 02:17:52PM +0200, Hans de Goede wrote:
The pwm-crc code is using 2 different enable bits:
1. bit 7 o
Hi,
On 6/30/20 3:51 PM, Jani Nikula wrote:
On Sat, 20 Jun 2020, Hans de Goede wrote:
Hi All,
Here is v3 of my patch series converting the i915 driver's code for
controlling the panel's backlight with an external PWM controller to
use the atomic PWM API. See below for the changelog.
Initially
Hi,
Thank you for your review and sorry for the slow reply.
I would like to get this series upstream this cycle, so
I will do my best to be a lot faster with responding from
now on.
On 6/22/20 9:35 AM, Uwe Kleine-König wrote:
On Sat, Jun 20, 2020 at 02:17:47PM +0200, Hans de Goede wrote:
Whe
On 04/07/2020 15:52, Sam Ravnborg wrote:
> Hi Mark.
>
> On Sat, Jul 04, 2020 at 03:16:47PM +0100, Mark Cave-Ayland wrote:
>> On 04/07/2020 14:41, Sam Ravnborg wrote:
>>
>>> I think what is happening is that the bochs driver request a shadow copy
>>> for the frambuffer. And with the change to fbop
Now that TTM is fixed up we can finally stop that nonsense.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 104 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +++-
2 files changed, 42 insertions(+), 80 deletions(-)
diff --git a/drivers/
Stop touching the backend private pointer alltogether and
make sure we never put the same mem twice by.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 46 +++--
include/drm/ttm/ttm_bo_driver.h | 2 --
2 files changed, 26 insertions(+), 22 deleti
Quoting Flavio Suligoi (2020-07-03 13:50:46)
> Fix typo: "TRIGER" --> "TRIGGER"
>
> The two misplelled macros:
>
> 1) OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK
> 2) OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK
>
> are not used in any other sources of the kernel,
> so this change can be consider
Hi
Am 06.07.20 um 16:47 schrieb Zenghui Yu:
> The HiSilicon hibmc driver triggers a splat at boot time as below
>
> [ 14.137806] [ cut here ]
> [ 14.142405] hibmc-drm :0a:00.0: Device has not been registered.
> [ 14.148661] WARNING: CPU: 0 PID: 496 at
> drivers/
https://bugzilla.kernel.org/show_bug.cgi?id=207383
--- Comment #40 from Alex Deucher (alexdeuc...@gmail.com) ---
Does this patch help?
https://gitlab.freedesktop.org/drm/amd/uploads/356586b6aa81f64cfa9b4b034499fdd8/amdgpu-bugfix-revert-vmalloc-size-change.patch
--
You are receiving this mail bec
On Thu, Jul 02, 2020 at 04:39:09PM +0530, Rajendra Nayak wrote:
> On SDM845 and SC7180 DSI needs to express a performance state
> requirement on a power domain depending on the clock rates.
> Use OPP table from DT to register with OPP framework and use
> dev_pm_opp_set_rate() to set the clk/perf st
On Thu, Jul 2, 2020 at 3:25 AM YueHaibing wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c: In function 'amdgpu_init_mem_type':
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:81:24: warning:
> variable 'adev' set but not used [-Wunused-but-set-varia
https://bugzilla.kernel.org/show_bug.cgi?id=208413
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On 05/07/2020 08:48, Dennis YC Hsieh wrote:
> Add address shift when compose jump instruction
> to compatible with 35bit format.
>
> Signed-off-by: Dennis YC Hsieh
You are missing Bibby's Reviewed-by. Please honour the effort reviewers do by
adding the appropriate tags.
Please double check t
https://bugzilla.kernel.org/show_bug.cgi?id=208443
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
https://bugzilla.kernel.org/show_bug.cgi?id=208129
Martin Jørgensen (m...@gotu.dk) changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolu
The hdmi4.c and hdmi5.c files include the legacy GPIO
header but does not use any of the symbols
from this file.
What it does use is the implicit inclusion of
leading to compile errors if we just drop this include.
Include the right header.
Cc: Tony Lindgren
Signed-off-by: Linus Walleij
---
Hi,
On 3/12/20 7:56 PM, Rajat Jain wrote:
Add support for an ACPI based integrated privacy screen that is
available on some systems.
Signed-off-by: Rajat Jain
So as discussed a while ago I'm working on adding support for the
privacy-screen on Lenovo Thinkpads, introducing a small new
subsyst
From: Tom Rix
clang static analysis flags this error
drivers/gpu/drm/radeon/ci_dpm.c:5652:9: warning: Use of memory after it is
freed [unix.Malloc]
kfree(rdev->pm.dpm.ps[i].ps_priv);
^~
drivers/gpu/drm/radeon/ci_dpm.c:5654:2: warning
Hi,
On 06/07/2020 01:57, Paul Boddie wrote:
> Hello,
>
> On Friday, 15 May 2020 09:43:54 CEST Neil Armstrong wrote:
>>
>> On 15/05/2020 00:04, Paul Boddie wrote:
>>>
>>> Well, I've done this but I probably need to know what to look for. One
>>> thing that appears regardless of this debugging outp
On Mon, Jul 6, 2020 at 1:02 AM Tomi Valkeinen wrote:
>
> Hi,
>
> On 03/07/2020 22:36, Sam Ravnborg wrote:
> > Hi Tomi.
> >
> > On Fri, Jul 03, 2020 at 10:17:29AM +0300, Tomi Valkeinen wrote:
> >> On 30/06/2020 21:26, Adam Ford wrote:
> >>> The drm/omap driver was fixed to correct an issue where us
https://bugzilla.kernel.org/show_bug.cgi?id=208443
--- Comment #1 from Michel Dänzer (mic...@daenzer.net) ---
See https://gitlab.freedesktop.org/drm/amd/-/issues/1189 .
--
You are receiving this mail because:
You are watching the assignee of the bug.
_
Hi,
On 03/07/2020 22:36, Sam Ravnborg wrote:
Hi Tomi.
On Fri, Jul 03, 2020 at 10:17:29AM +0300, Tomi Valkeinen wrote:
On 30/06/2020 21:26, Adam Ford wrote:
The drm/omap driver was fixed to correct an issue where using a
divider of 32 breaks the DSS despite the TRM stating 32 is a valid
number
Hi Sandy,
Am Montag, 6. Juli 2020, 09:59:44 CEST schrieb Sandy Huang:
> don't mask possible_crtcs if remote-point is disabled.
>
> Signed-off-by: Sandy Huang
> ---
> drivers/gpu/drm/drm_of.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/dr
Hi
Am 02.07.20 um 12:12 schrieb Thomas Zimmermann:
> Thanks!
>
> Am 02.07.20 um 10:54 schrieb Tian Tao:
>> code refactoring for hibmc_drv_vdac.c, no actual function changes.
>>
>> v2:
>> remove the debug message.
>>
>> v3:
>> embedding connector and encoder in struct hibmc_drm_private.
>>
>> Sign
Hi,
On 03/07/2020 11:08, Simon Ser wrote:
> Thanks for the update!
>
> The driver should also disallow importing a AMLOGIC_FBC_LAYOUT_SCATTER
> DMA-BUF from another device, but I guess this is clear enough ("not
> transferrable between Amlogic SoCs").
Good idea, I'll experiment disabling import
Hi,
On Sat, Jul 04, 2020 at 12:25:34PM +0200, Clément Péron wrote:
> Add an Operating Performance Points table for the GPU to
> enable Dynamic Voltage & Frequency Scaling on the H6.
>
> The voltage range is set with minival voltage set to the target
> and the maximal voltage set to 1.2V. This all
Introduce a proper panfrost_devfreq to deal with devfreq variables.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 76 -
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 20 +-
drivers/gpu/drm/panfrost/panfrost_devic
Hi Will,
On 2020-07-03 19:07, Will Deacon wrote:
On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
diff --git a/drivers/gpu/drm/msm/msm_iommu.c
b/drivers/gpu/drm/msm/msm_iommu.c
index f455c597f76d..bd1d58229cc2 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/dr
On 2020-07-03 21:34, Rob Clark wrote:
On Fri, Jul 3, 2020 at 7:53 AM Sai Prakash Ranjan
wrote:
Hi Will,
On 2020-07-03 19:07, Will Deacon wrote:
> On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
>> diff --git a/drivers/gpu/drm/msm/msm_iommu.c
>> b/drivers/gpu/drm/msm/msm_io
We will later introduce regulators managed by OPP.
Only alloc regulators when it's needed. This also help use
to release the regulators only when they are allocated.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_device.c | 14 +-
drive
Dear all,
I'm working on a simple kernel module currently called "dummy-backlight"
(https://github.com/fepitre/dummy-backlight) which creates a testing backlight.
After loaded, this driver allows to modify integer values of the virtual
backlight created through its sysfs attributes directly.
I
On Sun, Jul 5, 2020 at 1:30 PM Ondřej Jirman wrote:
>
> Hello Lukas,
>
> On Sun, Jul 05, 2020 at 08:59:17AM +0200, Lukas Bulwahn wrote:
> > Commit a74e81a56405 ("drm/panel: rocktech-jh057n00900: Rename the driver to
> > st7703") and commit 7317f4574492 ("dt-bindings: panel: Convert
> > rocktech,jh
Add address shift when compose jump instruction
to compatible with 35bit format.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
b/drivers/soc/mediatek/mtk-c
Hello,
On Friday, 15 May 2020 09:43:54 CEST Neil Armstrong wrote:
>
> On 15/05/2020 00:04, Paul Boddie wrote:
> >
> > Well, I've done this but I probably need to know what to look for. One
> > thing that appears regardless of this debugging output being enabled is a
> > problem with the vertical
The VC4_SET_FIELD and VC4_GET_FIELD are reimplementing most of the logic
already defined in FIELD_SET and FIELD_GET. Let's convert the vc4 macros to
use the FIELD_* macros.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_regs.h | 9 -
1 file changed, 4 insertions(+), 5 deletions
add write_s_mask_value function in cmdq helper functions which
writes a constant value to address with mask and large dma
access support.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 21 +
include/linux/soc/mediatek/mtk-cmdq.h | 15
Add jump function so that client can jump to any address which
contains instruction.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +
include/linux/soc/mediatek/mtk-cmdq.h | 11 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/
The example is now validated against rocktech,jh057n00900 schema
that was ported to yaml, and didn't validate with:
- '#address-cells', '#size-cells', 'port@0' do not match any of
the regexes: 'pinctrl-[0-9]+'
- 'vcc-supply' is a required property
- 'iovcc-supply' is a required property
- 'reset
Don't include not required headers and sort them.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/pan
Convert busy_count to a simple int protected by spinlock.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 43 +++--
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 9 -
2 files changed, 40 insertions(+), 12 deletions(-)
This use devfreq variable that will be lock with spinlock in future
patches. We should either introduce a function to access this one
but as devfreq is optional let's just remove it.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_job.c | 4
1 f
Add clear parameter to let client decide if
event should be clear to 0 after GCE receive it.
Fixes: 2f965be7f9008 ("drm/mediatek: apply CMDQ control flow")
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c |2 +-
drivers/soc/mediatek/mtk-cmdq-hel
The LVDS controller can invert the polarity / lanes of the LVDS output.
The default polarity causes some issues on some panels.
However, U-Boot has always used the opposite polarity without any reported
issue, and the only currently supported LVDS panel in-tree (the TBS A711)
seems to be able to w
Hi,
On Sat, 4 Jul 2020 at 12:25, Clément Péron wrote:
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> b/arch/arm64/boot/dts/allwin
sam,
I will change to "GPL-2.0-only OR BSD-2-Clause", i thought running
dt_binding_check is enough for .yaml.
On Fri, Jul 3, 2020 at 8:36 PM Sam Ravnborg wrote:
>
> Hi Vinay.
>
> On Thu, Jul 02, 2020 at 06:06:33PM +0530, Vinay Simha BN wrote:
> > Signed-off-by: Vinay Simha BN
> >
> > ---
> > v1
Add read_s function in cmdq helper functions which support read value from
register or dma physical address into gce internal register.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++
include/linux/mailbox/mtk-cmdq-mailbox.h |1 +
include/l
Devfreq cooling device framework is used in Panfrost
to throttle GPU in order to regulate its temperature.
Enable this driver for ARM64 SoC.
Signed-off-by: Clément Péron
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm6
Fix typo: "TRIGER" --> "TRIGGER"
The two misplelled macros:
1) OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK
2) OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK
are not used in any other sources of the kernel,
so this change can be consider only a local change
for the i915_reg.h file.
Signed-off-by: F
Hello Lukas,
On Sun, Jul 05, 2020 at 08:59:17AM +0200, Lukas Bulwahn wrote:
> Commit a74e81a56405 ("drm/panel: rocktech-jh057n00900: Rename the driver to
> st7703") and commit 7317f4574492 ("dt-bindings: panel: Convert
> rocktech,jh057n00900 to yaml") renamed and converted the files mentioned in
>
add write_s_mask function in cmdq helper functions which
writes value contains in internal register to address
with mask and large dma access support.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 23 +++
include/linux/mailbox/mtk-cmdq-mailbo
Add an Operating Performance Points table for the GPU to
enable Dynamic Voltage & Frequency Scaling on the H6.
The voltage range is set with minival voltage set to the target
and the maximal voltage set to 1.2V. This allow DVFS framework to
work properly on board with fixed regulator.
Signed-off-
This driver is tested with two panels individually with Apq8016-IFC6309 board
https://www.inforcecomputing.com/products/single-board-computers-sbc/qualcomm-snapdragon-410-inforce-6309-micro-sbc
1. 1366x768@60 auo,b101xtn01 data-mapping = "jeida-24"
2. 800x480@60 innolux,at070tn92 data-mapping = "v
On Thu, Jul 02, 2020 at 08:15:40PM +0200, Daniel Vetter wrote:
> > > > 3. rdma driver worker gets busy to restart rx:
> > > > 1. lock all dma-buf that are currently in use (dma_resv_lock).
> > > > thanks to ww_mutex deadlock avoidance this is possible
> > > Why all? Why not just loc
Hi Maxime,
On Sat, 4 Jul 2020 at 14:13, Maxime Ripard wrote:
>
> Hi,
>
> On Sat, Jul 04, 2020 at 12:25:34PM +0200, Clément Péron wrote:
> > Add an Operating Performance Points table for the GPU to
> > enable Dynamic Voltage & Frequency Scaling on the H6.
> >
> > The voltage range is set with mini
Some OPP tables specify voltage for each frequency. Devfreq can
handle these regulators but they should be get only 1 time to avoid
issue and know who is in charge.
If OPP table is probe don't init regulator.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/p
Add a simple cooling map for the GPU.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 78b1361
- converted from .txt to .yaml
- dual-link lvds port added and implemented
- dsi data-lanes property removed, it will be picked
from dsi0 ports
- VESA/JEIDA formats picked from panel-lvds dts
- proper indentation
- single-link and dual-link lvds description and
examples are added
- license modi
add write_s function in cmdq helper functions which
writes a constant value to address with large dma
access support.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 14 ++
include/linux/soc/mediatek/mtk-cmdq.h | 13 +
2 files changed, 27
Hi,
This serie cleans and adds regulator support to Panfrost devfreq.
This is mostly based on comment for the freshly introduced lima
devfreq.
We need to add regulator support because on Allwinner the GPU OPP
table defines both frequencies and voltages.
First patches [01-07] should not change th
The display has one port. Allow it in the binding.
Signed-off-by: Ondrej Jirman
---
.../devicetree/bindings/display/panel/rocktech,jh057n00900.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml
b/Documentation/dev
Hi,
On Sat, 4 Jul 2020 at 12:25, Clément Péron wrote:
>
> Hi,
>
> This serie cleans and adds regulator support to Panfrost devfreq.
> This is mostly based on comment for the freshly introduced lima
> devfreq.
>
> We need to add regulator support because on Allwinner the GPU OPP
> table defines bo
add write_s function in cmdq helper functions which
writes value contains in internal register to address
with large dma access support.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 19 +++
include/linux/mailbox/mtk-cmdq-mailbox.h |1 +
incl
Rename goto labels in device_init it will be easier to maintain.
Signed-off-by: Clément Péron
---
drivers/gpu/drm/panfrost/panfrost_device.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/
Commit a74e81a56405 ("drm/panel: rocktech-jh057n00900: Rename the driver to
st7703") and commit 7317f4574492 ("dt-bindings: panel: Convert
rocktech,jh057n00900 to yaml") renamed and converted the files mentioned in
DRM DRIVER FOR ROCKTECH JH057N00900 PANELS, but did not adjust the entries
in MAINTA
This declaration can be avoided so change it.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 38 ++---
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers
Later we will introduce devfreq probing regulator if they
are present. As regulator should be probe only one time we
need to get this logic in the device_init().
panfrost_device is already taking care of devfreq_resume()
and devfreq_suspend(), so it's not totally illogic to move
the devfreq_init()
On Fri, Jul 03, 2020 at 02:52:03PM +0200, Daniel Vetter wrote:
> So maybe I'm just totally confused about the rdma model. I thought:
> - you bind a pile of memory for various transactions, that might
> happen whenever. Kernel driver doesn't have much if any insight into
> when memory isn't needed
This patch support more gce helper function on mt6779 platform.
depends on patch: support gce on mt6779 platform
and depends on following applied patches
soc: mediatek: cmdq: add set event function
soc: mediatek: cmdq: export finalize function
soc: mediatek: cmdq: add assign function
Change sinc
Replace space-indents with tab-indents.
Issues found with checkpatch.
Signed-off-by: Suraj Upadhyay
---
drivers/gpu/drm/drm_connector.c | 38 -
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_co
Add a function to look up a connector by
device tree node, like what of_drm_find_bridge/panel
does.
Signed-off-by: Andy Yan
Reported-by: kernel test robot
---
Changes in v2:
- Add function declaration
drivers/gpu/drm/drm_connector.c | 33 +
include/drm/drm_con
This patchset fixes warnings in the example in display/bridge/nwl-dsi.yaml
revealed during port of display/panel/rocktech,jh057n00900.yaml to
yaml.
Please take a look.
thank you and regards,
Ondrej Jirman
Ondrej Jirman (2):
dt-bindings: display: Fix example in nwl-dsi.yaml
dt-binding: disp
02.07.2020 15:36, Georgi Djakov пишет:
...
+ mc->provider.data = data;
+ mc->provider.xlate = of_icc_xlate_onecell;
+ mc->provider.aggregate = tegra_mc_icc_aggregate;
+
+ err = icc_provider_add(&mc->provider);
+ if (err)
+ goto err_msg;
>>>
>>> Nit:
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 3f7ceeb1a767..14257f7476b8 100644
-
Hi
On Fri, Jul 03, 2020 at 05:47:08PM +0200, Andrzej Hajda wrote:
> On 30.06.2020 15:27, Maxime Ripard wrote:
> > I've tried to bring-up the DSI controller on the RaspberryPi4, and I've
> > just encountered something that could make it troublesome to support.
> >
> > For context, the RaspberryPi
Hi,
In the last meeting, X.Org Foundation board has decided that XDC 2020
will be a virtual conference, given the uncertain COVID-19 situation in
Europe by September, including the possibility of a second wave,
outbreaks and travel restrictions, either in Poland or in other
countries.
XDC 2020 or
Introduce a boolean to know if opp table has been added.
With this, we can call panfrost_devfreq_fini() in case of error
and release what has been initialised.
Signed-off-by: Clément Péron
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 25 -
dri
On Fri, Jul 03, 2020 at 12:44:48PM +0200, megous hlavni wrote:
> Hello Sam,
>
> On Fri, Jul 03, 2020 at 07:11:55AM +0200, Sam Ravnborg wrote:
> > Hi Ondrej.
> >
> > > > My bot found errors running 'make dt_binding_check' on your patch:
> > > >
> > > > /builds/robherring/linux-dt-review/Documenta
The function mipi_dbi_spi1_transfer() will transfer its payload as 9-bit
data, the 9th (MSB) bit being the data/command bit. In order to do that,
it unpacks the 8-bit values into 16-bit values, then sets the 9th bit if
the byte corresponds to data, clears it otherwise. The 7 MSB are
padding. The ar
Hi,
On Tue, Jun 30, 2020 at 04:26:20PM +0800, Jian-Hong Pan wrote:
> Maxime Ripard 於 2020年6月29日 週一 下午10:21寫道：
> >
> > Hi!
> >
> > On Fri, Jun 05, 2020 at 04:44:51PM +0800, Jian-Hong Pan wrote:
> > > Maxime Ripard 於 2020年6月2日 週二 下午7:04寫道：
> > > >
> > > > Hi,
> > > >
> > > > On Mon, Jun 01, 2020 a
Hello Sam,
On Fri, Jul 03, 2020 at 07:11:55AM +0200, Sam Ravnborg wrote:
> Hi Ondrej.
>
> > > My bot found errors running 'make dt_binding_check' on your patch:
> > >
> > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/nwl-dsi.example.dt.yaml:
> > > panel@0
On Wed, 24 Jun 2020, Lee Jones wrote:
> Attempting to clean-up W=1 kernel builds, which are currently
> overwhelmingly riddled with niggly little warnings.
>
> Lee Jones (8):
> backlight: lms501kf03: Remove unused const variables
> backlight: lcd: Add missing kerneldoc entry for 'struct devic
On Thu, 25 Jun 2020, Daniel Thompson wrote:
> On Wed, Jun 24, 2020 at 03:57:18PM +0100, Lee Jones wrote:
> > Kerneldoc syntax is used, but not complete. Descriptions required.
> >
> > Prevents warnings like:
> >
> > drivers/video/backlight/ili922x.c:298: warning: Function parameter or
> > mem
On Thu, 25 Jun 2020, Daniel Thompson wrote:
> On Wed, Jun 24, 2020 at 03:57:16PM +0100, Lee Jones wrote:
> > Kerneldoc syntax is used, but not complete. Descriptions required.
> >
> > Prevents warnings like:
> >
> > drivers/video/backlight/ili922x.c:116: warning: Function parameter or
> > mem
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