On Thu, Dec 19, 2019 at 09:47:55AM +0100, Maxime Ripard wrote:
> The Allwinner SoCs have a display engine composed of several controllers
> assembled differently depending on the SoC, the number and type of output
> they have, and the additional features they provide. A number of those are
> suppor
https://bugzilla.kernel.org/show_bug.cgi?id=206021
--- Comment #3 from Clément Guérin (li...@protonmail.com) ---
Created attachment 286535
--> https://bugzilla.kernel.org/attachment.cgi?id=286535&action=edit
manually turning the monitor off and on with drm.debug=6
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https://bugzilla.kernel.org/show_bug.cgi?id=206021
--- Comment #2 from Clément Guérin (li...@protonmail.com) ---
Created attachment 286533
--> https://bugzilla.kernel.org/attachment.cgi?id=286533&action=edit
lock/resume with drm.debug=6
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[AMD Official Use Only - Internal Distribution Only]
>
> From: Wentland, Harry
> Sent: Monday, December 30, 2019 23:26
> To: Lin, Wayne; dri-devel@lists.freedesktop.org; amd-...@lists.freedesktop.org
> Cc: ly...@redhat.com; Zuo, Jerry; Kazlauskas, Nicholas
[AMD Official Use Only - Internal Distribution Only]
>
> From: Jani Nikula
> Sent: Monday, December 30, 2019 19:15
> To: Lin, Wayne; dri-devel@lists.freedesktop.org; amd-...@lists.freedesktop.org
> Cc: Zuo, Jerry; Kazlauskas, Nicholas; Lin, Wayne
> Subject
Hi Dave, Daniel:
This include phy timing and plane index fixes.
Regards,
CK
The following changes since commit
e42617b825f8073569da76dc4510bfa019b1c35a:
Linux 5.5-rc1 (2019-12-08 14:57:55 -0800)
are available in the Git repository at:
https://github.com/ckhu-mediatek/linux.git-tags.git
ta
On Sat, Dec 28, 2019 at 1:37 AM Martin Blumenstingl
wrote:
>
> Most platforms with a Mali-400 or Mali-450 GPU also have support for
> changing the GPU clock frequency. Add devfreq support so the GPU clock
> rate is updated based on the actual GPU usage when the
> "operating-points-v2" property is
https://bugzilla.kernel.org/show_bug.cgi?id=206021
Bug ID: 206021
Summary: AMDGPU/DC: freesync disabled on the monitor side after
the monitor sleeps and resumes
Product: Drivers
Version: 2.5
Kernel Version: 5.4
Hardware
https://bugzilla.kernel.org/show_bug.cgi?id=206021
--- Comment #1 from Clément Guérin (li...@protonmail.com) ---
Created attachment 286527
--> https://bugzilla.kernel.org/attachment.cgi?id=286527&action=edit
Freesync OFF
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On 30-12-2019 21:41, Harry Wentland wrote:
On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
On 24-12-2019 01:23, Harry Wentland wrote:
On 2019-12-23 12:03 p.m., Animesh Manna wrote:
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After p
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i91
Send uevent to testapp and set test_active flag. To align with link
compliance design existing intel_dp_compliance tool will be used to
get the phy request in userspace through uevent.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 --
1 file changed, 8 ins
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Reviewed-by: Harry Wentland
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/amd/display/dc/core/d
As per request from DP phy compliance test few special
test pattern need to set by source. Added function
to set pattern in DP_COMP_CTL register. It will be
called along with other test parameters like vswing,
pre-emphasis programming in atomic_commit_tail path.
Signed-off-by: Animesh Manna
---
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointe
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
drive
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Acked-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Note: FIXME tag added as design discusion is ongoing in previous patch
series. Some temporary fix added and the patch is under-development, not for
review.
Signed-off-by: Animesh Manna
---
Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.
Overall design:
--
Automate test request will come to source device as HDP s
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp revision
On 2019-12-30 11:05 a.m., Manna, Animesh wrote:
> On 24-12-2019 01:23, Harry Wentland wrote:
>>
>> On 2019-12-23 12:03 p.m., Animesh Manna wrote:
>>> During phy compliance auto test mode source need to read
>>> requested test pattern from sink through DPCD. After processing
>>> the request source
On 24-12-2019 01:23, Harry Wentland wrote:
On 2019-12-23 12:03 p.m., Animesh Manna wrote:
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as
https://bugzilla.kernel.org/show_bug.cgi?id=206017
--- Comment #1 from udo (udo...@xs4all.nl) ---
See https://gitlab.freedesktop.org/drm/amd/issues/934 for more details.
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https://bugzilla.kernel.org/show_bug.cgi?id=206017
Bug ID: 206017
Summary: Kernel 5.4.x unusable with GUI due to
[drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
Waiting for fences timed out!
Product: Drivers
V
Most Kconfig options to enable a driver are in the Kconfig file
inside the relevant directory, move these two to the same.
Signed-off-by: Andrew F. Davis
---
Changes from v1:
- Rebased
drivers/gpu/drm/Kconfig| 34 --
drivers/gpu/drm/amd/amdgpu/Kconfig |
On Fri, Dec 20, 2019 at 12:56:50PM +0100, Artur Świgoń wrote:
> This patch adds the following properties to the Exynos4412 DT:
> - exynos,interconnect-parent-node: to declare connections between
> nodes in order to guarantee PM QoS requirements between nodes;
> - #interconnect-cells: requir
On 2019-12-30 2:05 a.m., Wayne Lin wrote:
> [Why]
> According to DP spec, it should shift left 4 digits for NO_STOP_BIT
> in REMOTE_I2C_READ message. Not 5 digits.
>
> [How]
> Correct the shifting value of NO_STOP_BIT for DP_REMOTE_I2C_READ case in
> drm_dp_encode_sideband_req().
>
> Signed-off-b
When userspace requests a video mode parameter value that is not
supported, frame buffer device drivers should round it up to a supported
value, if possible, instead of just rejecting it. This allows
applications to quickly scan for supported video modes.
Currently this rule is not followed for t
On Mon, Dec 16, 2019 at 9:51 PM Hans de Goede wrote:
> Currently only the drivers/pinctrl/devicetree.c code allows registering
> pinctrl-mappings which may later be unregistered, all other mappings
> are assumed to be permanent.
>
> Non-dt platforms may also want to register pinctrl mappings from
When configuring the frame memory window, the last column and row
numbers are written to the column resp. page address registers. These
numbers are thus one less than the actual window width resp. height.
While this is handled correctly in mipi_dbi_fb_dirty() since commit
03ceb1c8dfd1e293 ("drm/t
On Mon, 30 Dec 2019, Wayne Lin wrote:
> [Why]
> According to DP spec, it should shift left 4 digits for NO_STOP_BIT
> in REMOTE_I2C_READ message. Not 5 digits.
>
> [How]
> Correct the shifting value of NO_STOP_BIT for DP_REMOTE_I2C_READ case in
> drm_dp_encode_sideband_req().
Which commit introdu
Hi Tian,
On Sat, 28 Dec 2019 at 01:14, Tian Tao wrote:
> @@ -118,11 +119,9 @@ static void hibmc_plane_atomic_update(struct drm_plane
> *plane,
> writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
>
> reg = state->fb->width * (state->fb->format->cpp[0]);
> - /* now line_pa
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