On 2018-11-01 23:17, Jayant Shekhar wrote:
In case of msm drm bind failure, dpu_mdss_destroy is triggered.
In this function, resources are freed and pm runtime disable is
called, which triggers dpu_mdss_disable. Now in dpu_mdss_disable,
driver tries to access a memory which is already freed. This
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc para
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
C
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI er
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v3:
* C
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
C
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_tran
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Manasi Na
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Mana
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload
This patch series addresses review comments on previous DSC series:
https://patchwork.freedesktop.org/series/47514/
Gaurav K Singh (3):
drm/i915/dsc: Define & Compute VESA DSC params
drm/i915/dsc: Compute Rate Control parameters for DSC
drm/i915/dp: Enable/Disable DSC in DP Sink
Manasi Nav
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of inte
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDS
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3: Print FEC CAPABILITY value. (Manasi)
Suggested-by: J
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, be
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style change
Hi Linus,
Pretty much a normal fixes pull pre-rc1, mostly amdgpu fixes, one i915
link training regression fix, and a couple of minor panel/bridge fixes
and a panel quirk.
Thanks,
Dave.
drm-next-2018-11-02:
drm, i915, amdgpu, bridge + core quirk
The following changes since commit f2bfc71aee75feff
https://bugzilla.kernel.org/show_bug.cgi?id=201599
Bug ID: 201599
Summary: [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in
loop for more than 5secs aborting
Product: Drivers
Version: 2.5
Kernel Version: 4.18.14-300.fc29.x86
https://bugs.freedesktop.org/show_bug.cgi?id=108533
Dieter Nützel changed:
What|Removed |Added
Status|RESOLVED|CLOSED
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https://bugs.freedesktop.org/show_bug.cgi?id=108577
--- Comment #18 from Duncan Roe ---
Created attachment 142334
--> https://bugs.freedesktop.org/attachment.cgi?id=142334&action=edit
Patch for Linux-19.0 to revert 5099114 & reinstate DRM_AMD_DC_FBC kconfig
option
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Reviving the patch posted by Sean initially.
This patch set adds MDSS and DSI nodes to SDM845 dtsi to enable display. The
patches are tested on SDM845 MTP platform using the kernel based on [1].
Part of the dependent drivers are already posted on list. Rest of the
dependencies are met using usin
DPU is short for the Display Processing Unit. It is the display
controller on Qualcomm SDM845 chips.
This change adds MDSS and DSI nodes to enable display on the
target device.
Changes in v2:
- Beefed up commit message
- Use SoC specific compatibles for mdss and dpu (Rob H)
[why]
Removing connector reusage from DM to match the rest of the tree ended
up revealing an issue that was surprisingly subtle. The original amdgpu
code for DC that was submitted appears to have left a chunk in
dm_dp_create_fake_mst_encoder() that tries to find a "master encoder",
the likes of whi
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #39 from gr...@sub.red ---
(In reply to Michel Dänzer from comment #34)
>
> Right, you'd have to disable TearFree as well.
Then I think the logs should represent that, even when the manpage tells me
that tearfree is using page flipp
On Thu, Nov 01, 2018 at 04:54:14PM -0700, Manasi Navare wrote:
> Thanks for reviewing this patch. Find some comments inline
>
> On Thu, Nov 01, 2018 at 06:46:28PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:23PM -0700, Manasi Navare wrote:
> > > According to Display Stream compre
https://bugs.freedesktop.org/show_bug.cgi?id=93829
Timothy Arceri changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEEDINFO
Thanks for reviewing this patch. Find some comments inline
On Thu, Nov 01, 2018 at 06:46:28PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:23PM -0700, Manasi Navare wrote:
> > According to Display Stream compression spec 1.2, the picture
> > parameter set metadata is sent from sourc
+dri-devel list since a lot of the relevant audience is on that list.
On Mon, Oct 29, 2018 at 07:49:13PM -0400, Kenny Ho wrote:
> (Resending in plain text)
>
> Hi,
>
> We are thinking of using cgroup to manage resources in GPUs. I
> believe Matt Roper from Intel has been trying to do something
https://bugs.freedesktop.org/show_bug.cgi?id=108613
--- Comment #5 from tempel.jul...@gmail.com ---
Yeah, looks like that. It also happens when changing ttys.
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On Thu, Nov 01, 2018 at 06:42:17PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:20PM -0700, Manasi Navare wrote:
> > This patch defines a new header file for all the DSC 1.2 structures
> > and creates a structure for PPS infoframe which will be used to send
> > picture parameter set
The TPO (Toppoly) TPG110 is a pretty generic display driver
similar in vein to the Ilitek 93xx devices. It is not a panel
per se but a driver used with several low-cost noname panels.
This is used on the Nomadik NHK15 combined with a OSD
OSD057VA01CT display for WVGA 800x480.
The driver is pretty
On Thu, Nov 01, 2018 at 05:03:15PM -0400, Sean Paul wrote:
> On Wed, Oct 10, 2018 at 10:15:59AM -0700, Chandan Uddaraju wrote:
> > Add the needed DP PLL specific files to support
> > display port interface on msm targets.
> >
> > The DP driver calls the DP PLL driver registration.
> > The DP drive
The TPO TPG110 bindings were using the DPI bindings (popular
in the fbdev subsystem) but this misses the finer points
learned in the DRM subsystem.
We need to augment the bindings for proper DRM integration:
the timings are expressed by the hardware, not put into the
device tree. I.e. this hardwar
https://bugs.freedesktop.org/show_bug.cgi?id=108613
--- Comment #4 from dwagner ---
This is most certainly a duplicate of bug
https://bugs.freedesktop.org/show_bug.cgi?id=107141 (which I would really
really like to be fixed one day...)
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On Wed, Oct 10, 2018 at 10:15:59AM -0700, Chandan Uddaraju wrote:
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
>
> The DP driver calls the DP PLL driver registration.
> The DP driver sets the link and pixel clock sources.
>
> Signed-off-by: Chandan Ud
Hi,
Le jeudi 01 novembre 2018 à 21:00 +0100, Paul Kocialkowski a écrit :
> The series adds support for the BL035-RGB-002 LCD panel and the required
> device-tree bindings for using it on the BananaPi M1.
>
> Only the changes related to the DRM driver and the panel are submitted
> for merge, which
Nick Kreeger writes:
> This patch is needed to help implement half-float texturing and
> rendering for the vc4 driver in mesa. This small patch introduces the
> cpp value for the RGBA64 texture. A future patch will include updates to
> vc4_render_cl.c to handle HDR color stores.
We'll need a GET
This adds support for the 3.5" LCD panel from LeMaker, sold for use with
BananaPi boards. It comes with a 24-bit RGB888 parallel interface and
requires an active-low DE signal
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/panel/panel-simple.c | 27 +++
1 file chang
This adds the backlight panel, power, pwm and tcon0 device-tree bindings
required for supporting the 3.5" LCD from LeMaker on the BananaPi M1.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 89
1 file changed, 89 insertions(+)
diff --git
This adds the pin muxing definition for configuring the PD pins in LCD0
mode for a RGB888 format to the sun7i device-tree.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arc
This adds the device-tree bindings for the LeMaker BL035-RGB-002 3.5"
QVGA TFT LCD panel, compatible with simple-panel.
Signed-off-by: Paul Kocialkowski
---
.../bindings/display/panel/lemaker,bl035-rgb-002.txt | 7 +++
1 file changed, 7 insertions(+)
create mode 100644
Documentation/
This introduces a new device-tree binding vendor prefix for Shenzhen
LeMaker Technology Co., Ltd.
Signed-off-by: Paul Kocialkowski
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
Some panels need an active-low data enable (DE) signal for the RGB
interface. This requires flipping a bit in the TCON0 polarity register
when setting up the mode for the RGB interface.
Match the associated bus flag and use it to set the polarity inversion
bit for the DE signal when required.
Sig
The series adds support for the BL035-RGB-002 LCD panel and the required
device-tree bindings for using it on the BananaPi M1.
Only the changes related to the DRM driver and the panel are submitted
for merge, which does not include the two final commits.
Changes since v1:
* Used the full name of
Features such as dithering and pixel data edge configuration currently
rely on the panel registered with the TCON driver. However, bridges are
also supported in addition panels.
Instead of retrieving the connector from the panel, pass the encoder
from the calling function, as is done for other int
https://bugs.freedesktop.org/show_bug.cgi?id=108628
Bug ID: 108628
Summary: Middle-Earth: Shadow of Mordor: artifacts in benchmark
mode
Product: Mesa
Version: 18.2
Hardware: Other
OS: Linux (All)
On Wed, Oct 31, 2018 at 05:19:04PM -0700, Jeykumar Sankaran wrote:
> DPU was using one thread per display to dispatch async
> commits and vblank requests. Since clean up already happened
> in msm to use the common thread for all the display commits,
> display threads are only used to cater vblank r
https://bugs.freedesktop.org/show_bug.cgi?id=108627
Martin Peres changed:
What|Removed |Added
Status|RESOLVED|CLOSED
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On Wed, Oct 31, 2018 at 05:19:05PM -0700, Jeykumar Sankaran wrote:
> msm maintains a separate structure to define vblank
> work definitions and a list to track events submitted
> to the display worker thread. We can avoid these
> redundant list and its protection mechanism, if we
> subclass the wor
On Wed, Oct 31, 2018 at 05:19:04PM -0700, Jeykumar Sankaran wrote:
> DPU was using one thread per display to dispatch async
> commits and vblank requests. Since clean up already happened
> in msm to use the common thread for all the display commits,
> display threads are only used to cater vblank r
From: Ville Syrjälä
Convert drm_atomic_plane_check() over to using explicit old vs. new
plane states. Avoids the confusion of "what does plane->state mean
again?".
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c | 90 ++--
1 file changed, 46 insert
From: Ville Syrjälä
Convert drm_atomic_crtc_check() over to using explicit old vs. new
crtc states. Avoids the confusion of "what does crtc->state mean
again?".
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c | 26 +++---
1 file changed, 15 insertions(+), 11 d
From: Ville Syrjälä
Replace 'crtc->state' with the explicit old crtc state.
Actually it shouldn't matter whether we use the old or the new
crtc state here since any plane that has been removed from the
crtc since the crtc state was duplicated will have been added
to the atomic state already. Tha
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #38 from bmil...@gmail.com ---
(In reply to tempel.julian from comment #37)
> I think software cursor would also be unusable even if it left pageflipping
> on. It causes nasty issues like flickering cursor or other visual corruption.
https://bugs.freedesktop.org/show_bug.cgi?id=108627
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108075
--- Comment #2 from Martin Peres ---
*** Bug 108627 has been marked as a duplicate of this bug. ***
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https://bugs.freedesktop.org/show_bug.cgi?id=108075
Martin Peres changed:
What|Removed |Added
Component|DRM/Intel |IGT
QA Contact|intel-gfx-bugs@li
https://bugs.freedesktop.org/show_bug.cgi?id=108627
Martin Peres changed:
What|Removed |Added
Component|DRM/Intel |IGT
QA Contact|intel-gfx-bugs@li
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #37 from tempel.jul...@gmail.com ---
I think software cursor would also be unusable even if it left pageflipping on.
It causes nasty issues like flickering cursor or other visual corruption.
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https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #36 from bmil...@gmail.com ---
So, to help find the origin of the issue, there are a few options that get rid
of stutter when compositing:
1 - amdgpu.dc=0 - The old DC seems unaffected by the bug.
2 - SWcursor on - Unaffected by bug
https://bugs.freedesktop.org/show_bug.cgi?id=108625
--- Comment #1 from Alex Deucher ---
Please attach your full dmesg output and xorg log if using X.
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https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #35 from bmil...@gmail.com ---
(In reply to Michel Dänzer from comment #31)
> Note that SWcursor completely disables page flipping, at least with
> xf86-video-amdgpu, because the two things are fundamentally incompatible
> with each o
https://bugs.freedesktop.org/show_bug.cgi?id=108606
--- Comment #16 from Samantha McVey ---
Created attachment 142330
--> https://bugs.freedesktop.org/attachment.cgi?id=142330&action=edit
amdgpu.ppfeaturemask=0xfffdbfff lockup during normal usage
I did more testing on amdgpu.ppfeaturemask=0xff
https://bugzilla.kernel.org/show_bug.cgi?id=201585
--- Comment #8 from Dan Acristinii (d...@acristinii.com) ---
Created attachment 279289
--> https://bugzilla.kernel.org/attachment.cgi?id=279289&action=edit
4.18 with drm.debug=4
I think I added it in the right way
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On 11/1/18 1:05 PM, Michel Dänzer wrote:
> On 2018-11-01 3:58 p.m., Kazlauskas, Nicholas wrote:
>> On 11/1/18 6:58 AM, Michel Dänzer wrote:
>>> On 2018-10-31 6:54 p.m., Kazlauskas, Nicholas wrote:
On 10/31/18 12:20 PM, Michel Dänzer wrote:
> On 2018-10-31 3:41 p.m., Kazlauskas, Nicholas wr
Hey Chris,
On 2018-11-01 17:26, Chris Wilson wrote:
Quoting Robert Foss (2018-11-01 16:12:28)
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
On 2018-11-01 3:58 p.m., Kazlauskas, Nicholas wrote:
> On 11/1/18 6:58 AM, Michel Dänzer wrote:
>> On 2018-10-31 6:54 p.m., Kazlauskas, Nicholas wrote:
>>> On 10/31/18 12:20 PM, Michel Dänzer wrote:
On 2018-10-31 3:41 p.m., Kazlauskas, Nicholas wrote:
> On 10/31/18 10:12 AM, Michel Dänzer
For some pixel formats .cpp structure in drm_format info it's not
enough to describe the peculiarities of the pixel layout, for example
tiled formats or packed formats at bit level.
What's implemented here is to add three new members to drm_format_info
that could describe such formats:
- char_per
https://bugs.freedesktop.org/show_bug.cgi?id=107402
Martin Peres changed:
What|Removed |Added
Status|RESOLVED|CLOSED
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https://bugs.freedesktop.org/show_bug.cgi?id=107402
Martin Peres changed:
What|Removed |Added
Resolution|--- |WORKSFORME
Status|NEW
On Thu, Nov 01, 2018 at 06:42:17PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:20PM -0700, Manasi Navare wrote:
> > This patch defines a new header file for all the DSC 1.2 structures
> > and creates a structure for PPS infoframe which will be used to send
> > picture parameter set
https://bugs.freedesktop.org/show_bug.cgi?id=108606
--- Comment #15 from Samantha McVey ---
Alex,
The conditions in your patch never get triggered. I added some print statements
in there, and gfx_v9_0_init_rlc_ext_microcode(adev) runs, but
`adev->powerplay.pp_feature &= ~PP_GFXOFF_MASK` never run
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #39 from bmil...@gmail.com ---
Another interesting info, even with amdgpu.dc=0 I get flickering @75hz.
Difference is the flickering immediatly stops when I switch back to 60hz (no
need to reboot or switch monitor off/on)
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You are
On Wed, Oct 24, 2018 at 03:28:23PM -0700, Manasi Navare wrote:
> According to Display Stream compression spec 1.2, the picture
> parameter set metadata is sent from source to sink device
> using the DP Secondary data packet. An infoframe is formed
> for the PPS SDP header and PPS SDP payload bytes.
On Wed, Oct 24, 2018 at 03:28:20PM -0700, Manasi Navare wrote:
> This patch defines a new header file for all the DSC 1.2 structures
> and creates a structure for PPS infoframe which will be used to send
> picture parameter set secondary data packet for display stream compression.
> All the PPS inf
https://bugs.freedesktop.org/show_bug.cgi?id=107222
Martin Peres changed:
What|Removed |Added
Resolution|--- |WORKSFORME
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=107222
Martin Peres changed:
What|Removed |Added
Status|RESOLVED|CLOSED
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https://bugs.freedesktop.org/show_bug.cgi?id=107221
Martin Peres changed:
What|Removed |Added
Status|RESOLVED|CLOSED
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https://bugs.freedesktop.org/show_bug.cgi?id=107221
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Quoting Robert Foss (2018-11-01 16:12:28)
> If dma_fence_wait fails to wait for a supplied in-fence in
> msm_ioctl_gem_submit, make sure we release that in-fence.
>
> Also remove this dma_fence_put() from the 'out' label.
>
> Signed-off-by: Robert Foss
> ---
> drivers/gpu/drm/msm/msm_gem_submit
Hi Tony,
On Thursday, 1 November 2018 17:58:56 EET Tony Lindgren wrote:
> * Laurent Pinchart [181101 12:13]:
> > On Thursday, 1 November 2018 13:47:40 EET Tomi Valkeinen wrote:
> > > We do dispc_runtime_get/put in the HDMI driver's suspend/resume too, so
> > > don't we need similar hack (as you a
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
1 file changed, 5 insertions(+), 5 del
https://bugs.freedesktop.org/show_bug.cgi?id=108625
Bug ID: 108625
Summary: AMDGPU - Can't even get Xorg to start - Kernel driver
hangs with ring buffer timeout on ARM64
Product: DRI
Version: unspecified
Hardware: ARM
https://bugs.freedesktop.org/show_bug.cgi?id=108613
Michel Dänzer changed:
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https://bugs.freedesktop.org/show_bug.cgi?id=108613
Michel Dänzer changed:
What|Removed |Added
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https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #34 from Michel Dänzer ---
(In reply to tempel.julian from comment #33)
> I suppose TearFree forces pageflipping regardless, as we don't see any
> tearing with that configuration.
Right, you'd have to disable TearFree as well. Can b
https://bugs.freedesktop.org/show_bug.cgi?id=108098
--- Comment #7 from Michel Dänzer ---
FWIW, I advise against paying too much attention to fin4478. They are not
involved in driver development and known for making rather questionable
suggestions which are definitely not suitable for everyone.
On Thu, Nov 01, 2018 at 01:31:06PM +, Alexandru-Cosmin Gheorghe wrote:
> Hi,
>
> Liviu, can I merge this through drm-misc-next.
Yeah, that is fine with me.
Best regards,
Liviu
>
> On Mon, Oct 29, 2018 at 05:14:38PM +, Alexandru-Cosmin Gheorghe wrote:
> > Enable the following formats
>
Hi Dave,
Fixes for 4.20. Highlights:
- Fix flickering at low backlight levels on some systems
- Fix some overclocking regressions
- Vega20 updates for
- GPU recovery fixes
- Disable gfxoff on RV as some sbios/fw combinations are not stable yet
The following changes since commit 0af5c656fdb797f74
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