Pixel blend modes represent the alpha blending equation
selection, describing how the pixels from the current
plane are composited with the background.
Adds a pixel_blend_mode to drm_plane_state and a
blend_mode_property to drm_plane, and related support
functions.
Defines three blend modes in dr
Checks the pixel blending mode and plane alpha value when
do the plane_check. Mali DP supports blending the current plane
with the background either based on the pixel alpha blending
mode or by using the layer's alpha value, but not both at the
same time. If both case, plane_check will return faile
Hi,
This serie aims at adding the support for pixel blend modes represent the
alpha blending equation selection in the driver. It also introduces to use
it in the malidp driver.
Let me know what you think,
Lowry
Changes for v4:
- Refines drm_plane_create_blend_mode_property(). drm_property_add_
On Tue, Aug 14, 2018 at 02:23:10PM +0200, Maarten Lankhorst wrote:
> Op 14-08-18 om 13:32 schreef Lowry Li:
> > Pixel blend modes represent the alpha blending equation
> > selection, describing how the pixels from the current
> > plane are composited with the background.
> >
> > Adds a pixel_blend_
On Sun, 12 Aug 2018, Sam Ravnborg wrote:
> The LCDC IP used by some Atmel SOC's have a
> multifunction device that include two sub-devices:
> - pwm
> - display controller
>
> This mfd device provide a regmap that can be used by the
> sub-devices to safely access the registers.
> The m
tree: git://people.freedesktop.org/~agd5f/linux.git vega20_psp_smu
head: 9b9ef18df4349dd2d2b8941e76c032ed8acf2529
commit: 24048ee665f3c9367dfa4978f3cd9b4e428fe2e5 [12/44] drm/amdgpu: Add nbio
7.4 support for vega20 (v2)
reproduce:
# apt-get install sparse
git checkout 24048ee66
Fixes: 24048ee665f3 ("drm/amdgpu: Add nbio 7.4 support for vega20 (v2)")
Signed-off-by: kbuild test robot
---
nbio_v7_4.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 623ffde..89ea920
tree: git://people.freedesktop.org/~agd5f/linux.git vega20_psp_smu
head: 9b9ef18df4349dd2d2b8941e76c032ed8acf2529
commit: 27480799ed68e17e8228372a4afac7d5dcfbf01a [28/44] drm/amd/powerplay: new
interfaces for overdrive vega20 sclk and mclk
config: arm-allmodconfig (attached as .config)
compile
Hi, Stu:
For the series, applied to mediatek-drm-next-4.19 [1], but I modified
'drm/mediatek: add RGB color format support for RDMA' and 'drm/mediatek:
add YUYV/UYVY color format support for RDMA' because I would like to
place related register definition together.
[1]
https://github.com/ckhu-medi
On Tue, 2018-08-14 at 10:46 -0500, Dinh Nguyen wrote:
>
> On 08/14/2018 03:57 AM, Hean-Loong, Ong wrote:
> >
> > From: Ong Hean Loong
> >
> > Driver for Intel FPGA Video and Image Processing Suite Frame Buffer
> > II.
> > The driver only supports the Intel Arria10 devkit and its variants.
> Why
On Tue, 2018-08-14 at 10:48 -0500, Dinh Nguyen wrote:
>
> On 08/14/2018 03:57 AM, Hean-Loong, Ong wrote:
> >
> > From: Ong, Hean Loong
> >
> > The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM
> > driver patch
> > here is allocating memory for information to be streamed from t
On 2018-08-14 13:26, Sean Paul wrote:
On Tue, Aug 07, 2018 at 08:20:10PM -0700, Jeykumar Sankaran wrote:
Subclass drm private state for DPU for handling driver
specific data. Adds atomic private object and private object
lock to dpu kms. Provides helper function to retrieve DPU
private data from
On 2018-08-14 13:14, Sean Paul wrote:
On Tue, Aug 07, 2018 at 08:20:08PM -0700, Jeykumar Sankaran wrote:
Strip down the support for topology enums. It
can be replaced with simple hw count checks.
Can you remove the enum entirely? A quick scan seems like it might be
possible,
it seems like it's
On 2018-08-14 12:19, Sean Paul wrote:
On Tue, Aug 07, 2018 at 08:12:31PM -0700, Jeykumar Sankaran wrote:
Identify slave-master encoders and program them explicitly.
You've got the what, but could you please explain the why?
changes in v2:
- none
changes in v3:
- none
Change
Pushed to drm-misc-next with the whitespace fix.
Thanks for the patch.
Regards
Manasi
On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field indi
https://bugs.freedesktop.org/show_bug.cgi?id=107572
Bug ID: 107572
Summary: Unrecoverable GPU hang with IP block:gfx_v8_0 is hung
Product: DRI
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NE
On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field indicates the panels true
> capabilities are described in DPCD address space 02200h through
One more CFL ID added to spec.
Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")
v2: fix commit subject.
Cc: José Roberto de Souza
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
---
intel/intel_chipset.h | 6 --
1 file changed, 4 insertions(+),
On Tue, Aug 14, 2018 at 06:43:43PM +0200, Sam Ravnborg wrote:
> Hi Rob.
>
> > I don't know that 2 registers for a backlight PWM constitute an MFD. A
> > single node can be both an LCD controller and a PWM.
>
> Current suggestion from v1 patchset looks like this:
> lcdc0: lcdc@70 {
>
https://bugs.freedesktop.org/show_bug.cgi?id=105880
Alex Deucher changed:
What|Removed |Added
Attachment #141088|0 |1
is obsolete|
https://bugs.freedesktop.org/show_bug.cgi?id=105880
Alex Deucher changed:
What|Removed |Added
Attachment #141087|0 |1
is obsolete|
https://bugs.freedesktop.org/show_bug.cgi?id=102322
--- Comment #39 from Andrey Grodzovsky ---
(In reply to dwagner from comment #37)
> In the related bug report
> (https://bugs.freedesktop.org/show_bug.cgi?id=107152) I noticed that this
> bug can be triggered very reliably and quickly by playing
https://bugs.freedesktop.org/show_bug.cgi?id=105880
--- Comment #30 from Alex Deucher ---
Created attachment 141087
--> https://bugs.freedesktop.org/attachment.cgi?id=141087&action=edit
Add support for LVDS
The attached patch adds support for LVDS. I don't have a board with LVDS at
the moment
https://bugs.freedesktop.org/show_bug.cgi?id=105880
Alex Deucher changed:
What|Removed |Added
CC||shawn.st...@rogers.com
--- Comment #29 f
https://bugs.freedesktop.org/show_bug.cgi?id=105996
Alex Deucher changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Tue, Aug 07, 2018 at 08:20:11PM -0700, Jeykumar Sankaran wrote:
> Switch to state based resource management. This patch
> overhauls the resource manager and HW allocation methods by
> maintaining the global resource pool and allocated hw
> blocks in respective drm component states.
>
> Global r
https://bugs.freedesktop.org/show_bug.cgi?id=105733
--- Comment #26 from Allan ---
I will do it as soon as possible, but it may take a while (maybe a month)
because my motherboard showed many issues and I'm requesting money back to buy
another.
--
You are receiving this mail because:
You are th
On Tue, Aug 07, 2018 at 08:20:10PM -0700, Jeykumar Sankaran wrote:
> Subclass drm private state for DPU for handling driver
> specific data. Adds atomic private object and private object
> lock to dpu kms. Provides helper function to retrieve DPU
> private data from current atomic state.
>
> chang
On Tue, Aug 07, 2018 at 08:20:09PM -0700, Jeykumar Sankaran wrote:
> Encoder H_TILE values are not used for allocating the hw blocks.
> no. of hw_intf blocks provides the info.
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: I1c1c13e9b9f608fbaa8c5897f9f1892029107a
On Tue, Aug 07, 2018 at 08:20:08PM -0700, Jeykumar Sankaran wrote:
> Strip down the support for topology enums. It
> can be replaced with simple hw count checks.
Can you remove the enum entirely? A quick scan seems like it might be possible,
it seems like it's only used in topology_def to pass to
On Tue, Aug 07, 2018 at 08:12:36PM -0700, Jeykumar Sankaran wrote:
> Prep change for state based resource management.
>
> Rename hw_ctl to lm_ctl to mean the ctl associated
> with the hw layer mixer block.
Did you do this via spatch, sed, etc? Rename patches should contain the
invocation to repro
On Tue, Aug 07, 2018 at 08:12:35PM -0700, Jeykumar Sankaran wrote:
> Prep changes for state based resource management.
>
> Moves all the hw block tracking for the crtc to the state
> object.
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: I2816e9e28b27f1126b477d6
On Tue, Aug 14, 2018 at 9:03 PM, Haneen Mohammed
wrote:
> On Tue, Aug 14, 2018 at 10:21:29AM +0200, Daniel Vetter wrote:
>> On Mon, Aug 13, 2018 at 11:04:11PM +0300, Haneen Mohammed wrote:
>> > On Wed, Aug 08, 2018 at 10:23:27AM +0200, Daniel Vetter wrote:
>> > > On Wed, Aug 08, 2018 at 06:53:17AM
https://bugs.freedesktop.org/show_bug.cgi?id=105733
--- Comment #25 from Andrey Grodzovsky ---
(In reply to Allan from comment #12)
> My system started to power down for nothing sometimes, even using the
> GTX1070 (nvidia|nouveau) .
> Then I installed a Windows image just to be sure if the kernel
On Tue, Aug 07, 2018 at 08:12:34PM -0700, Jeykumar Sankaran wrote:
> hw intf blocks are needed only during encoder enable to program
> timing engines(for video panels). encoder->enable is triggered
> only after atomic_modeset at which point we assign the
> resources for the display pipeline. This p
https://bugs.freedesktop.org/show_bug.cgi?id=107072
Pontus Gråskæg changed:
What|Removed |Added
CC||graaskaeg.via.forwarder@nev
On Tue, Aug 07, 2018 at 08:12:33PM -0700, Jeykumar Sankaran wrote:
> Instead of iterating for hw ctrl per physical encoder, this
> patch moves the iterations and assignment to the virtual encoder.
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: I896a8c36d635398658
https://bugs.freedesktop.org/show_bug.cgi?id=105251
--- Comment #16 from Andrey Grodzovsky ---
Hi everyone, I've tried with latest kernel and latest VEGA10 firmware and
wasn't able to reproduce this problem.
>From the logs it seems all of you are running 4.17.x kernel or earlier - try
latest 4.1
On Tue, Aug 07, 2018 at 08:12:32PM -0700, Jeykumar Sankaran wrote:
> Avoid querying RM for hw mdp block. Use the one
> stored in KMS during initialization.
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: I52129b96bd561a5547507d7f567bcaa3dbe554aa
> Signed-off-by: J
On Tue, Aug 07, 2018 at 08:12:31PM -0700, Jeykumar Sankaran wrote:
> Identify slave-master encoders and program them explicitly.
You've got the what, but could you please explain the why?
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: I0ebfada05bd7f8437f842ad86
https://bugs.freedesktop.org/show_bug.cgi?id=105880
--- Comment #28 from Pontus Gråskæg ---
Thank-you for the swift response, Alex.
Coding this is certainly beyond my current capabilities - I would have a rather
steep learning curve. I hope this is an itch somebody with the right experience
suff
On Tue, Aug 07, 2018 at 08:12:30PM -0700, Jeykumar Sankaran wrote:
> removes left out variables of previous ping pong
> split topology cleanup.
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: I1bf9d242039ce7cfd271233fa27840e83184fb95
> Signed-off-by: Jeykumar Sank
On Tue, Aug 07, 2018 at 08:12:29PM -0700, Jeykumar Sankaran wrote:
> resource pool manager utility was introduced to manage
> rotator sessions. Removing the support as the rotator
> feature doesn't exist.
>
> changes in v2:
> - none
> changes in v3:
> - rebase on [1]
>
> [1] https://g
On Tue, Aug 14, 2018 at 04:56:27PM +0530, spa...@codeaurora.org wrote:
> On 2018-08-14 03:00, Sean Paul wrote:
> > From: Sean Paul
> >
> > Instead of just waiting 20ms for training to complete, actually poll the
> > status to ensure training is finished.
> >
> > Changes in v3:
> > - Added to the
On Tue, Aug 14, 2018 at 04:10:02PM +0530, spa...@codeaurora.org wrote:
> On 2018-08-14 03:00, Sean Paul wrote:
> > From: Sean Paul
> >
> > The panel datasheet specifies a 500ms delay after power-down before
> > re-enabling.
> >
> > Changes in v2:
> > - None
> > Changes in v3:
> > - Added to the
https://bugs.freedesktop.org/show_bug.cgi?id=107454
--- Comment #2 from Gert Wollny ---
Created attachment 141085
--> https://bugs.freedesktop.org/attachment.cgi?id=141085&action=edit
Shader that gets incorrectly optimized by sb
The attached shader is one of the exampled that gets incorrectly
https://bugs.freedesktop.org/show_bug.cgi?id=107545
--- Comment #1 from Julien Isorce ---
Created attachment 141084
--> https://bugs.freedesktop.org/attachment.cgi?id=141084&action=edit
simple.c
Minimal test to reproduce the issue by just drawing 2 lines. Run: for i in
{0..300}; do (./simple &
Reviewed-by: Andrey Grodzovsky
Andrey
On 08/14/2018 04:23 AM, Huang Rui wrote:
On Tue, Aug 14, 2018 at 10:12:23AM +0200, Christian König wrote:
Return -ENOMEM when allocating the rq_list fails.
Signed-off-by: Christian König
Reviewed-by: Huang Rui
---
drivers/gpu/drm/scheduler/gpu_sc
On 08/14/2018 11:26 AM, Christian König wrote:
Am 14.08.2018 um 17:17 schrieb Andrey Grodzovsky:
I assume that this is the only code change and no locks are taken in
drm_sched_entity_push_job -
What are you talking about? You surely now take looks in
drm_sched_entity_push_job():
+ s
On 08/14/2018 03:57 AM, Hean-Loong, Ong wrote:
> From: Ong, Hean Loong
>
> The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver
> patch
> here is allocating memory for information to be streamed from the ARM/Linux
> to the display port. Basically the driver just wraps th
https://bugs.freedesktop.org/show_bug.cgi?id=105880
--- Comment #27 from Alex Deucher ---
(In reply to Pontus Gråskæg from comment #26)
> Given the commit to the kernel
>
> https://lkml.org/lkml/2018/7/6/30
>
> and the same commit going into the 4.18 tree
>
> https://patchwork.freedesktop.org/
On 08/14/2018 03:57 AM, Hean-Loong, Ong wrote:
> From: Ong Hean Loong
>
> Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II.
> The driver only supports the Intel Arria10 devkit and its variants.
Why only Arria10? That's not true is it? I remember running a version of
this
Am 14.08.2018 um 17:17 schrieb Andrey Grodzovsky:
I assume that this is the only code change and no locks are taken in
drm_sched_entity_push_job -
What are you talking about? You surely now take looks in
drm_sched_entity_push_job():
+ spin_lock(&entity->rq_lock);
+ entity->last_user
I assume that this is the only code change and no locks are taken in
drm_sched_entity_push_job -
What happens if process A runs drm_sched_entity_push_job after this code
was executed from the (dying) process B and there
are still jobs in the queue (the wait_event terminated prematurely), the
On Tue, Aug 14, 2018 at 04:57:07PM +0800, Hean-Loong, Ong wrote:
> From: Ong, Hean Loong
>
> Device tree binding for Intel FPGA Video and Image Processing Suite. The
> binding involved would be generated from the Altera (Intel) Qsys system. The
> bindings would set the max width, max height, bu
On Tue, Aug 14, 2018 at 12:36 AM Peter Rosin wrote:
>
> On 2018-08-13 22:52, Rob Herring wrote:
> > On Mon, Aug 13, 2018 at 8:25 AM Peter Rosin wrote:
> >>
> >> On 2018-08-13 15:59, jacopo mondi wrote:
> >>> Hi Peter,
> >>>
> >>> On Fri, Aug 10, 2018 at 03:03:58PM +0200, Peter Rosin wrote:
>
Hi Lucas, Christoph,
After switching ARC to generic dma_noncoherent cache ops
etnaviv driver start failing on dma maping functions because of
dma_mask lack.
So I'm wondering is it valid case to have device which is
DMA capable and doesn't have dma_mask set?
If not, then I guess something like t
https://bugs.freedesktop.org/show_bug.cgi?id=107552
--- Comment #5 from Sylvain BERTRAND ---
bisected:
commit cbf0bb7f192b814be84dff538fb90dacf65958c7
Author: Christian König
Date: Thu Aug 2 10:45:19 2018 +0200
On Mon, Feb 26, 2018 at 8:52 AM, Jyri Sarha wrote:
> On 25/02/18 11:22, Lukas Wunner wrote:
>> On Thu, Feb 22, 2018 at 07:42:46PM +0200, Jyri Sarha wrote:
>>> Put consumer device to deferred probe list if it is unbound due to a
>>> dropped link to a supplier.
>>>
>>> When a device link supplier is
On Tue, Aug 14, 2018 at 04:59:31PM +0530, spa...@codeaurora.org wrote:
> On 2018-08-14 03:00, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch adds a 70ms mystery delay to the bridge driver in enable.
> > By experimentation, it seems like it can go anywhere up until we
> > initiate semi-au
On Tue, Aug 14, 2018 at 10:00:33AM -0400, Sean Paul wrote:
> On Tue, Aug 14, 2018 at 04:59:31PM +0530, spa...@codeaurora.org wrote:
> > On 2018-08-14 03:00, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > This patch adds a 70ms mystery delay to the bridge driver in enable.
> > > By experimenta
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
This patch adds a 70ms mystery delay to the bridge driver in enable.
By experimentation, it seems like it can go anywhere up until we
initiate semi-auto link training. If we don't have the delay, link
training fails.
I tried to root cause t
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
Instead of just waiting 20ms for training to complete, actually poll
the
status to ensure training is finished.
Changes in v3:
- Added to the set
Cc: Sandeep Panda
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 1
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
This was hand-rolled in the first version, and will surely be useful as
we expand the driver to support more varied use cases.
Changes in v2:
- Change subject prefix s/panel/bridge/
- Downgrade warning in poll function to error message
- Fi
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
Instead of just waiting and hoping, actually poll for the pll lock to
be
acquired. As a bonus, this should be significantly faster than the
sleep.
Changes in v3:
- Added to the set
Cc: Sandeep Panda
Signed-off-by: Sean Paul
---
driver
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
prepare() is the old-timey way to say pre_enable(). It should be called
before modeset. This fixes an issue where the panel on cheza must have
the regulator always-on/boot-on for it to work.
Changes in v3:
- Added to the set
Cc: Sandeep Pa
> Stefan Wahren hat am 14. August 2018 um 00:54
> geschrieben:
>
>
> Hi,
>
> today i accidently found a regression on the Raspberry Pi 3 with
> arm64/defconfig (bcm2835_defconfig and multi_v7_defconfig are not affected)
> in current 4.18.
>
> Symptoms: Raspberry Pi 3 boots to serial console
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
Order registers by offset and rename bits & masks to match the
datasheet. This makes the driver a bit easier to grok and
cross-reference with the datasheet.
Changes in v3:
- Added to the set
Cc: Sandeep Panda
Signed-off-by: Sean Paul
---
On Tue, Aug 14, 2018 at 12:42:42PM +0200, Daniel Vetter wrote:
> Given your past track record of handling other contributors I think it's
> entirely understandably that people do not choose to collaborate with you
> voluntarily. Fixing that is entirely up to you though.
I do not work piecemeal. I
On 2018-08-14 03:00, Sean Paul wrote:
From: Sean Paul
The panel datasheet specifies a 500ms delay after power-down before
re-enabling.
Changes in v2:
- None
Changes in v3:
- Added to the set
Cc: Sandeep Panda
Signed-off-by: Sean Paul
---
drivers/gpu/drm/panel/panel-simple.c | 3 +++
1 file
Op 14-08-18 om 13:32 schreef Lowry Li:
> Pixel blend modes represent the alpha blending equation
> selection, describing how the pixels from the current
> plane are composited with the background.
>
> Adds a pixel_blend_mode to drm_plane_state and a
> blend_mode_property to drm_plane, and related s
On Mon, Jun 04, 2018 at 02:49:26PM +0100, Emil Velikov wrote:
> On 1 June 2018 at 13:41, Lowry Li wrote:
> > Pixel blend modes represent the alpha blending equation
> > selection, describing how the pixels from the current
> > plane are composited with the background.
> >
> > Add a pixel_blend_mod
Hi,
This serie aims at adding the support for pixel blend modes represent the
alpha blending equation selection in the driver. It also introduces to use
it in the malidp driver.
Let me know what you think,
Lowry
Changes for v4:
- Refines drm_plane_create_blend_mode_property(). drm_property_add_
Pixel blend modes represent the alpha blending equation
selection, describing how the pixels from the current
plane are composited with the background.
Adds a pixel_blend_mode to drm_plane_state and a
blend_mode_property to drm_plane, and related support
functions.
Defines three blend modes in dr
Checks the pixel blending mode and plane alpha value when
do the plane_check. Mali DP supports blending the current plane
with the background either based on the pixel alpha blending
mode or by using the layer's alpha value, but not both at the
same time. If both case, plane_check will return faile
https://bugs.freedesktop.org/show_bug.cgi?id=107459
Michel Dänzer changed:
What|Removed |Added
Attachment #140977|text/x-log |text/plain
mime type|
https://bugs.freedesktop.org/show_bug.cgi?id=106519
Michel Dänzer changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On Tue, Aug 14, 2018 at 12:48 PM, Russell King - ARM Linux
wrote:
> On Tue, Aug 14, 2018 at 12:42:42PM +0200, Daniel Vetter wrote:
>> Given your past track record of handling other contributors I think it's
>> entirely understandably that people do not choose to collaborate with you
>> voluntarily
/linux/commits/Sam-Ravnborg/add-at91sam9-LCDC-DRM-driver/20180814-163056
base: https://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
at91-next
config: sparc64-allyesconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget
https
https://bugs.freedesktop.org/show_bug.cgi?id=106519
Michel Dänzer changed:
What|Removed |Added
Attachment #140983|text/x-log |text/plain
mime type|
https://bugs.freedesktop.org/show_bug.cgi?id=105880
--- Comment #26 from Pontus Gråskæg ---
Given the commit to the kernel
https://lkml.org/lkml/2018/7/6/30
and the same commit going into the 4.18 tree
https://patchwork.freedesktop.org/patch/230643/
can Harry Wentland or Alex Deucher clarify
https://bugs.freedesktop.org/show_bug.cgi?id=107482
Michel Dänzer changed:
What|Removed |Added
Attachment #140974|text/x-log |text/plain
mime type|
https://bugs.freedesktop.org/show_bug.cgi?id=107432
--- Comment #9 from Michel Dänzer ---
Please test https://patchwork.freedesktop.org/patch/242563/ instead.
--
You are receiving this mail because:
You are the assignee for the bug.___
dri-devel maili
On Fri, Aug 10, 2018 at 06:16:30PM +0100, Russell King - ARM Linux wrote:
> On Fri, Aug 10, 2018 at 01:02:29PM -0400, Sean Paul wrote:
> > On Fri, Aug 10, 2018 at 05:50:37PM +0100, Russell King - ARM Linux wrote:
> > > Almost none of my DRM specific patches on dri-devel this time around
> > > recei
On Tue, Aug 14, 2018 at 12:48:08PM +0300, Laurent Pinchart wrote:
> Hi Dmitry,
>
> Thank you for the patch.
>
> On Tuesday, 7 August 2018 20:22:01 EEST Dmitry Osipenko wrote:
> > From: Laurent Pinchart
> >
> > Color keying is the action of replacing pixels matching a given color
> > (or range o
The Rockchip DSI driver was separate till now, not using the common
bridge driver that was introduced a bit later. So this series migrates
over to use that common bridge driver and then also adds support for
dual-dsi to both the bridge and Rockchip glue code.
The bridge-migration itself is based o
From a specified output port of one dsi controller this function allows to
iterate over the list of registered dsi controllers trying to find a second
instance connected to the same display, like it is used in dual-dsi setups.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/drm_mipi_dsi.c | 56
From: Nickey Yang
Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge and remove the old separate one.
changes:
v2:
add err_pllref, remove unnecessary encoder.enable & disable
correct spelling mistakes
v3:
call dw_mipi_dsi_unbind() i
Right now the host is only unregistered when the driver is used via the
bridge api and not via the component api, leading to the host staying
registered in cases like probe deferral.
So move the host unregister to the general remove function, so that it
gets cleaned up in all cases.
Signed-off-by
Add the Rockchip-sepcific dual-dsi setup and hook it into the VOP as well.
As described in the general dual-dsi devicetree binding, the panel should
define two input ports and point each of them to one of the used dsi-
controllers, as well as declare one of them as clock-master.
This is used to det
From: Nickey Yang
Allow to also drive a slave dw-mipi-dsi controller in a dual-dsi
setup. This will require additional implementation-specific
code to look up the slave instance and do specific setup.
Also will probably need code in the specific crtcs as dual-dsi
does not equal two separate dsi o
__dw_mipi_dsi_probe() does all the grabbing of resources and does it using
devm-helpers. So this is happening on each try of master bringup possibly
slowing down things a lot.
Drivers using the component framework may instead want to call
dw_mipi_dsi_probe separately in their probe function to set
With the regular means of adding the dsi-component in probe it creates
a race condition with the panel probing, as the panel device only gets
created after the dsi-bus got created.
When the panel-driver is build as a module it currently fails hard as the
panel cannot be probed directly:
dw_mipi_d
From: Nickey Yang
This patch update describe panel/port links, including
unit addresses in documentation of device tree bindings
for the rockchip DSI controller based on the Synopsys
DesignWare MIPI DSI host controller.
Signed-off-by: Nickey Yang
Reviewed-by: Brian Norris
Reviewed-by: Rob Herr
Am 14.08.2018 um 11:56 schrieb Michel Dänzer:
From: Michel Dänzer
The compiler points out that an int doesn't work as intended if
dev->bo_handles.max_key > INT_MAX:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:550:16: warning: comparison of in
From: Michel Dänzer
Arithmetic using void* pointers isn't defined by the C standard, only as
a GCC extension. Avoids compiler warnings:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:554:48: warning: pointer of type ‘void *’ used in
arithmetic [-
From: Michel Dänzer
The compiler points out that an int doesn't work as intended if
dev->bo_handles.max_key > INT_MAX:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:550:16: warning: comparison of integer expressions of
different signedness: ‘int
Hi Dmitry,
Thank you for the patch.
On Tuesday, 7 August 2018 20:22:01 EEST Dmitry Osipenko wrote:
> From: Laurent Pinchart
>
> Color keying is the action of replacing pixels matching a given color
> (or range of colors) with transparent pixels in an overlay when
> performing blitting. Dependin
On evergreen depth-stencil textures are allocated as two objects, and
when using the eg_surface_init_1d_miptrees code path the size evaluation
uses the generalized surf_minify function. Here when allocating the
depth texture the alignment takes the depth bpe value into account, and
uses bpe=1 for t
On Tue, Aug 14, 2018 at 11:15:43AM +0200, Maarten Lankhorst wrote:
> Op 14-08-18 om 05:11 schreef Lowry Li:
> > On Mon, Aug 13, 2018 at 12:49:13PM +0200, Maarten Lankhorst wrote:
> >> Op 05-06-18 om 11:07 schreef Lowry Li:
> >>> On Mon, Jun 04, 2018 at 02:49:26PM +0100, Emil Velikov wrote:
> O
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