On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
It's too early to detect fast link training, if other step after it
failed, we will set fast_link flag to 1, and retry set_bridge again. In
this case we will power down and power up panel power supply, and we
wi
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Douglas Anderson
The current user of the analogix power_off is "analogix_dp-rockchip".
That driver does this:
- deactivate PSR
- turn off a clock
Both of these things (especially deactive PSR) should be done before
we tu
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Douglas Anderson
The code in analogix_dp_transfer() that was supposed to print out:
AUX CH error happened
Was actually dead code. That's because the previous check (whether
the interrupt status indicated any errors) w
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Douglas Anderson
The comments in analogix_dp_init_aux() claim that we're disabling aux
channel retries, but then right below it for Rockchip it sets them to
3. If we actually need 3 retries for Rockchip then we could adj
Dear Stephen,
when rebuilding linux-next you're going to see a merge conflict in:
sound/pci/hda/hda_intel.c
betwen commit:
1ba8f9d30817 ("ALSA: hda: Add a power_save blacklist")
from the sound tree and commit:
07f4f97d7b4b ("vga_switcheroo: Use device link for HDA controller")
from the
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to
Exynos:
on Exynos edp phy,
BIT 7 MASTER_VID_FUNC_EN_N
BIT 6 reserved
BIT 5 SLAVE_VID_FUNC_EN_N
on Rockchip ed
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Reviewed-by: Archit Taneja
Thanks
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
If we failed disable psr, it would hang the display until next psr
cycle coming. So we should restore psr->state when it failed.
For the bridge part,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
AUX errors are caused by many different reasons. We may not know what
happened in aux channel on failure, so let's reset aux channel if some
errors occurred.
Cc: 征增 王
Cc: Douglas Anderson
Signed-off-by: Lin H
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
There are some different bits between Rockchip and Exynos in register
"AUX_PD". This patch fixes the incorrect operations about it.
You mean the register ANALOGIX_DP_PHY_PD/ANALOGIX_DP_PD, right? AUX_PD
sounds
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to check the dpcd write/read return value to see whether the
write/read was successful
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Kristian H. Kristensen
Signed-off-by: Lin Huang
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Enhanced mode is required by the eDP 1.2 specification, and not doing it
early could result in a period of time where we have a link transmitting
idle packets without it. Since there is no reason to disable it,
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
There was a 1ms delay to detect the hpd signal, which is too short to
detect a short pulse. This patch extends this delay to 100ms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征增
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zai
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Reviewed-by: Archit T
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: S
On Sun, Mar 11, 2018 at 04:55:49PM +0100, Lukas Wunner wrote:
> > On Sat, Mar 03, 2018 at 10:53:24AM +0100, Lukas Wunner wrote:
> > > Modernize vga_switcheroo by using a device link to enforce a runtime PM
> > > dependency from an HDA controller to the GPU it's integrated into, v2.
> > >
> > > htt
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Panel would reset its setting when it powers down. It would forget the last
succeeded link training setting. So we can't use the last successful link
training setting to do fast link training. Let's reset fast_t
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to enable video before analogix_dp_is_video_stream_on(), so
we can get the right video stream status.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
Signed-off-by:
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: zain wang
We currently wait for the panel to mirror our intended PSR state
before continuing on both PSR enter and PSR exit. This is really
only important to do when we're entering PSR, since we want to
be sure the last f
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: zain wang
We would meet a short black screen when exit PSR with the full link
training, In this case, we should use fast link train instead of full
link training.
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signe
Remove DT entries of hw block offsets and other target specific catalog
information for SDM845.
Signed-off-by: Sravanthi Kollukuduru
---
.../devicetree/bindings/display/msm/dpu.txt| 530 -
1 file changed, 530 deletions(-)
diff --git a/Documentation/devicetree/binding
This patch series aims at adding the target specific hardware
catalog information in driver source.
As a result, the current logic of dt based parsing is removed.
The DT clean up patch corresponding to this driver change will
be posted separately.
Sravanthi Kollukuduru (2):
dt-bindings: msm/dis
There is already condition checking input values between 2 and 4096
so condition checking 0 is always false. Remove the dead condition.
Signed-off-by: Seung-Woo Kim
---
tests/exynos/exynos_fimg2d_perf.c |7 ---
1 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/tests/exynos/e
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Reviewed-by: Archit Taneja
Cc: Tome
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Yakir Yang
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Reviewed-by: Archit Taneja
Cc: 征增 王
https://bugs.freedesktop.org/show_bug.cgi?id=102905
Roland Scheidegger changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=104037
--- Comment #1 from sh...@mcewan.id.au ---
Created attachment 138087
--> https://bugs.freedesktop.org/attachment.cgi?id=138087&action=edit
Content of /sys/class/drm/card0/error
I'm also getting this exact error. I was running XScreensaver at t
https://bugs.freedesktop.org/show_bug.cgi?id=100726
--- Comment #9 from hiwatari.se...@gmail.com ---
My last try of bisecting the error. I'm pretty sure I've got the correct commit
this time. I first ran 4 Weeks on the 4.9-rc1 without the error ever appearing,
upgraded to one or two release candid
https://bugs.freedesktop.org/show_bug.cgi?id=100726
--- Comment #10 from hiwatari.se...@gmail.com ---
Created attachment 138086
--> https://bugs.freedesktop.org/attachment.cgi?id=138086&action=edit
Bisect Log 3
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On 7 March 2018 at 18:27, Tomi Valkeinen wrote:
> Hi Dave,
>
> Please pull omapdrm changes for v4.17.
Hi Tomi,
Sorry for delay, pulled this it broken my ARM build
/home/airlied/devel/kernel/drm-next/drivers/gpu/drm/omapdrm/dss/dss.c:
In function ‘dss_probe’:
/home/airlied/devel/kernel/drm-next/
Fixes: db81084f9084 ("drm/xen-front: Add support for Xen PV display frontend")
Signed-off-by: Fengguang Wu
---
xen_drm_front.c |2 +-
xen_drm_front_drv.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xen/xen_drm_front.c
b/drivers/gpu/drm/xen/x
Hi Oleksandr,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v4.16-rc5 next-20180313]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
On 2018-03-12 13:21, Sean Paul wrote:
On Thu, Mar 08, 2018 at 04:56:01PM -0800, Jeykumar Sankaran wrote:
On 2018-02-28 11:18, Sean Paul wrote:
> Instead, shuffle things around so we kickoff crtc after enabling
encoder
> during modesets. Also moves the vblank wait to after the frame.
>
> Change
This allows for importing buffers allocated from the
hikey and hikey960 gralloc implementations.
Cc: Marissa Wall
Cc: Sean Paul
Cc: Dmitry Shmidt
Cc: Robert Foss
Cc: Matt Szczesiak
Cc: Liviu Dudau
Cc: David Hanna
Cc: Rob Herring
Cc: Alexandru-Cosmin Gheorghe
Cc: Alistair Strachan
Acked-b
https://bugs.freedesktop.org/show_bug.cgi?id=105463
--- Comment #6 from erhar...@mailbox.org ---
Created attachment 138085
--> https://bugs.freedesktop.org/attachment.cgi?id=138085&action=edit
html summary from 'pigllit run all' with LLVM
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You are receiving this mail because:
You are the ass
On Mon, 2018-03-12 at 23:01 +0200, Ville Syrjälä wrote:
> On Fri, Mar 09, 2018 at 04:32:27PM -0500, Lyude Paul wrote:
> > While having the modeset_retry_work in intel_connector makes sense with
> > SST, this paradigm doesn't make a whole ton of sense when it comes to
> > MST since we have to deal w
On Mon, 2018-03-12 at 13:45 -0700, Manasi Navare wrote:
> On Fri, Mar 09, 2018 at 04:32:28PM -0500, Lyude Paul wrote:
> > When a DP MST link needs retraining, sometimes the hub will detect that
> > the current link bw config is impossible and will update it's RX caps in
> > the DPCD to reflect the
https://bugs.freedesktop.org/show_bug.cgi?id=105463
--- Comment #5 from erhar...@mailbox.org ---
Created attachment 138084
--> https://bugs.freedesktop.org/attachment.cgi?id=138084&action=edit
results from 'pigllit run all' with LLVM
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You are receiving this mail because:
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On Tue, Mar 13, 2018 at 09:59:54PM +0100, Arnd Bergmann wrote:
> Like many other panel drivers, this one fails to build
> when backlight support is disabled:
>
> drivers/gpu/drm/panel/panel-raydium-rm68200.o: In function `rm68200_probe':
> panel-raydium-rm68200.c:(.text+0x14a): undefined reference
On Tue, Mar 13, 2018 at 04:23:10PM +0100, Daniel Vetter wrote:
> On Tue, Mar 13, 2018 at 02:49:59PM +0100, yannick fertre wrote:
> > Version 3:
> > - Replace some pr_error, pr_warn or pr_info by dev_error, dev_warn &
> > dev_info.
> > - Refresh stm32f769-disco_defconfig with last modification done
https://bugs.freedesktop.org/show_bug.cgi?id=105463
--- Comment #4 from erhar...@mailbox.org ---
Same setup but with mesa built with LLVM support:
# ./piglit run -s all results/OpenGL_all_llvm
Skipping GL_ARB_gpu_shader_fp64 tests
[54211/54211] skip: 30608, pass: 20471, warn: 15, fail: 3044, cras
drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary
arguments that can be removed by creating separate functins.
Create specific functions for these calls to reduce x86/64 defconfig
size by ~20k.
Modify the existing macros to use the specific calls.
new:
$ size -t drivers/gpu/dr
Like many other panel drivers, this one fails to build
when backlight support is disabled:
drivers/gpu/drm/panel/panel-raydium-rm68200.o: In function `rm68200_probe':
panel-raydium-rm68200.c:(.text+0x14a): undefined reference to
`devm_of_find_backlight'
This adds the appropriate dependency.
Fix
On Tue, Mar 13, 2018 at 1:50 PM, Anatolij Gustschin wrote:
> On Tue, 13 Mar 2018 16:23:10 +0100
> Daniel Vetter dan...@ffwll.ch wrote:
> ...
>> Shouldn't we patch the drivers/gpu/drm/stm driver instead of the
>> drivers/video one? fbdev is kinda a dead end and not for adding new hw
>> support ...
Some drivers duplicate the logic to create a property to store a per-plane
alpha.
This is especially useful if we ever want to support extra protocols for
Wayland like:
https://lists.freedesktop.org/archives/wayland-devel/2017-August/034741.html
Let's create a helper in order to move that to the
Now that we have support for per-plane alpha in the core, let's use it.
Acked-by: Boris Brezillon
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h| 13 +---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 89 ++
2 files changed, 14 insertions(+
Now that we moved the rcar-du DRM driver has been switched to the generic
alpha property, remove the former property documentation from the
deperecated CSV file.
Signed-off-by: Maxime Ripard
---
Documentation/gpu/kms-properties.csv | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation
Hi,
This serie aims at enhancing the support for plane-wide alpha in the
drivers that are implementing it at the moment, by turning it into a
generic property and converting the drivers (rcar-du and atmel-hclcdc). It
also introduces support for it in the sun4i driver.
Let me know what you think,
Now that we have support for per-plane alpha in the core, let's use it.
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 +-
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 5 +---
drivers/gpu/drm/rcar-du/rcar_du_plane.c | 15 +++--
driv
Our backend supports a per-plane alpha property. Support it through our new
helper.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 16 +---
drivers/gpu/drm/sun4i/sun4i_backend.h | 3 +++
drivers/gpu/drm/sun4i/sun4i_layer.c | 2
Hello, Matt.
cc'ing Roman and Alexei.
On Tue, Mar 06, 2018 at 03:46:55PM -0800, Matt Roper wrote:
> There are cases where other parts of the kernel may wish to store data
> associated with individual cgroups without building a full cgroup
> controller. Let's add interfaces to allow them to regis
On Tue, Mar 06, 2018 at 03:46:57PM -0800, Matt Roper wrote:
> Non-controller kernel subsystems may base access restrictions for
> cgroup-related syscalls/ioctls on a process' access to the cgroup.
> Let's make it easy for other parts of the kernel to check these cgroup
> permissions.
I'm not sure
(cc'ing Roman)
Hello,
On Tue, Mar 06, 2018 at 03:46:56PM -0800, Matt Roper wrote:
> +static inline struct cgroup *
> +task_get_dfl_cgroup(struct task_struct *task)
> +{
> + struct cgroup *cgrp;
> +
> + mutex_lock(&cgroup_mutex);
> + cgrp = task_dfl_cgroup(task);
> + cgroup_get(cgr
https://bugs.freedesktop.org/show_bug.cgi?id=102905
--- Comment #4 from i...@yahoo.com ---
(In reply to Roland Scheidegger from comment #3)
> I've just sent a patch to mesa-dev which should
> fix this, can you verify it works?
Yes it works nicely.
Can't wait to see the patch in git master. :)
-
On Tue, Mar 13, 2018 at 6:46 PM, Tvrtko Ursulin
wrote:
>
> On 13/03/2018 16:19, Arnd Bergmann wrote:
>>
>> The conditional spinlock confuses gcc into thinking the 'flags' value
>> might contain uninitialized data:
>>
>> drivers/gpu/drm/i915/i915_pmu.c: In function '__i915_pmu_event_read':
>> arch/
Hi Maruthi,
FYI, the error/warning still remains.
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: 701dfa780797b7124ba47026a2f071d3f1c6fb2b
commit: 944b5289c92d9c1aad3760c012daf4cf2478381f [699/881] ASoC: AMD: enable
ACP3x drivers build
config: sh-allmodconfig (
Op 13-03-18 om 16:07 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Ignore the vrefresh in the mode the user passed in and instead
> calculate the value based on the actual timings. This way we can
> actually trust mode->vrefresh to some degree.
>
> Or should we compare the user's idea of vrefre
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #27 from Ruben Harutyunyan ---
Hmm.
I guess I got deceived by `CONFIG_DRM_AMD_DC=y` being available in that commit
and logs like `dc_link_detect` and `dc_link_handle_hpd_rx_irq` that didn't show
up before.
Sorry about that!
--
Yo
https://bugzilla.kernel.org/show_bug.cgi?id=198123
sh...@tuta.io changed:
What|Removed |Added
CC||sh...@tuta.io
--- Comment #35 from sh...@
Quoting Eric Engestrom (2018-03-13 07:54:12)
> amdgpu makes use of it
>
> Signed-off-by: Eric Engestrom
> ---
> meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/meson.build b/meson.build
> index 3a33928d02a6dce5f075..f7986af9bb5259be5da5 100644
> --- a/meson.
Hey Alexandru,
On Tue, Mar 13, 2018 at 5:21 PM, Alexandru Gheorghe
wrote:
> This patchset tries to add support for using writeback connector to
> flatten a scene when it doesn't change for a while. This idea had
> been floated around on IRC here [1] and here [2].
>
> 2. Heuristic for triggering t
On 2018-03-12 13:30, Sean Paul wrote:
On Fri, Mar 02, 2018 at 04:44:55PM -0800, Jeykumar Sankaran wrote:
On 2018-02-28 11:19, Sean Paul wrote:
> Remove release/output/retire fences from the dpu driver. These are
> already available via drm core's OUT_FENCE property.
>
> Change-Id: Id4238d0b5457f
On 2018-03-12 13:14, Sean Paul wrote:
On Fri, Mar 02, 2018 at 04:04:24PM -0800, jsa...@codeaurora.org wrote:
On 2018-02-28 11:18, Sean Paul wrote:
> Instead of duplicating whole swaths of atomic helper functions (which
> are already out-of-date), just skip the encoder/crtc disables in the
> .dis
Use the newly exposed VSP1 interface to enable interlaced frame support
through the VSP1 lif pipelines.
Signed-off-by: Kieran Bingham
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 1 +
drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/r
Header mode display lists are now supported on all WPF outputs. To
support extended headers and auto-fld capabilities for interlaced mode
handling only header mode display lists can be used.
Disable the headerless display list configuration, and remove the dead
code.
Signed-off-by: Kieran Bingham
Calculate the top and bottom fields for the interlaced frames and
utilise the extended display list command feature to implement the
auto-field operations. This allows the DU to update the VSP2 registers
dynamically based upon the currently processing field.
Signed-off-by: Kieran Bingham
---
v2
VSPD and VSP-DL devices can provide extended display lists supporting
extended command display list objects.
These extended commands require their own dma memory areas for a header
and body specific to the command type.
Implement a command pool to allocate all necessary memory in a single
DMA all
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #26 from Harry Wentland ---
That regression commit is the one that introduced the new DC display driver, so
going back to the last working commit will effectively be the same as disabling
DC for you.
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You are receiving this mail
If there is an error allocating a display list within a DLM object
the existing display lists are not free'd, and neither is the DL body
pool.
Use the existing vsp1_dlm_destroy() function to clean up on error.
Signed-off-by: Kieran Bingham
---
drivers/media/platform/vsp1/vsp1_dl.c | 4 +++-
1 f
Extended display list headers allow pre and post command lists to be
executed by the VSP pipeline. This provides the base support for
features such as AUTO_FLD (for interlaced support) and AUTO_DISP (for
supporting continuous camera preview pipelines.
Signed-off-by: Kieran Bingham
---
v2:
- re
Both vsp1_dl_list_commit() and __vsp1_dl_list_put() walk the display
list chain referencing the nodes as children, when in reality they are
siblings.
Update the terminology to 'dl_next' to be consistent with the
vsp1_video_pipeline_run() usage.
Signed-off-by: Kieran Bingham
---
drivers/media/pl
The pixel format is 'unsupported'. Fix the small debug message which
incorrectly declares this.
Signed-off-by: Kieran Bingham
---
drivers/media/platform/vsp1/vsp1_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/vsp1/vsp1_drm.c
b/drivers/media/pla
The VSP1 devices define their specific capabilities through features
marked in their device info structure. Various parts of the code read
this info structure to infer if the features are available.
Wrap this into a more readable vsp1_feature(vsp1, f) macro to ensure
that usage is consistent throu
The vsp1 reference in the vsp1_dl_body structure is not used.
Remove it.
Signed-off-by: Kieran Bingham
---
drivers/media/platform/vsp1/vsp1_dl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/media/platform/vsp1/vsp1_dl.c
b/drivers/media/platform/vsp1/vsp1_dl.c
index 8162f4ce66eb.
The Gen3 R-Car DU devices make use of the VSP to handle frame processing.
In this series we implement support for handling interlaced pipelines by using
the auto-fld feature of the VSP hardware.
The implementation is preceded by some cleanup work and refactoring, through
patches 1 to 6. These are
The use of the packed attribute can cause a performance penalty for
all accesses to the struct members, as the compiler will assume that the
structure has the potential to have an unaligned base.
These structures are all correctly aligned and contain no holes, thus
the attribute is redundant and n
Handle both positive and negative dclk polarity,
according to bus_flags, taking care of this:
On A20 and similar SoCs, the only way to achieve Positive Edge
(Rising Edge), is setting dclk clock phase to 2/3(240°).
By default TCON works in Negative Edge(Falling Edge), this is why phase
is set to 0
On 13/03/2018 16:19, Arnd Bergmann wrote:
The conditional spinlock confuses gcc into thinking the 'flags' value
might contain uninitialized data:
drivers/gpu/drm/i915/i915_pmu.c: In function '__i915_pmu_event_read':
arch/x86/include/asm/paravirt_types.h:573:3: error: 'flags' may be used
uninit
https://bugs.freedesktop.org/show_bug.cgi?id=104216
--- Comment #22 from Germano Massullo ---
(In reply to Michel Dänzer from comment #21)
> (In reply to Germano Massullo from comment #20)
> > I experienced the problem with both of them.
>
> Did you check in Firefox about:support (look for "Driv
On Sun, Mar 11, 2018 at 04:55:49PM +0100, Lukas Wunner wrote:
> On Tue, Mar 06, 2018 at 11:29:40AM +0100, Daniel Vetter wrote:
> > On Sat, Mar 03, 2018 at 10:53:24AM +0100, Lukas Wunner wrote:
> > > Modernize vga_switcheroo by using a device link to enforce a runtime PM
> > > dependency from an HDA
On Sat, Mar 03, 2018 at 10:53:24AM +0100, Lukas Wunner wrote:
> From: Rafael J. Wysocki
>
> We leave PCI devices not bound to a driver in D0 during runtime suspend.
> But they may have a parent which is bound and can be transitioned to
> D3cold at runtime. Once the parent goes to D3cold, the unb
Am 13.03.2018 um 17:00 schrieb Daniel Vetter:
On Tue, Mar 13, 2018 at 04:52:02PM +0100, Christian König wrote:
Am 13.03.2018 um 16:17 schrieb Daniel Vetter:
[SNIP]
Ok, so plan is to support fully pipeline moves and everything, with the
old sg tables lazily cleaned up. I was thinking more about
Quoting Arnd Bergmann (2018-03-13 16:19:31)
> The conditional spinlock confuses gcc into thinking the 'flags' value
> might contain uninitialized data:
>
> drivers/gpu/drm/i915/i915_pmu.c: In function '__i915_pmu_event_read':
> arch/x86/include/asm/paravirt_types.h:573:3: error: 'flags' may be use
https://bugs.freedesktop.org/show_bug.cgi?id=105436
almos changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
|
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #25 from Ruben Harutyunyan ---
Seems like this is a regression actually. I've managed bisect the commit which
caused the problems.
Last working commit:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.15-dc&id=8ee5702a
The conditional spinlock confuses gcc into thinking the 'flags' value
might contain uninitialized data:
drivers/gpu/drm/i915/i915_pmu.c: In function '__i915_pmu_event_read':
arch/x86/include/asm/paravirt_types.h:573:3: error: 'flags' may be used
uninitialized in this function [-Werror=maybe-unini
From: Oleksandr Andrushchenko
Add support for Xen para-virtualized frontend display driver.
Accompanying backend [1] is implemented as a user-space application
and its helper library [2], capable of running as a Weston client
or DRM master.
Configuration of both backend and frontend is done via
X
From: Oleksandr Andrushchenko
Hello!
Resending with all the patches squashed on Daniel's request.
This patch series adds support for Xen [1] para-virtualized
frontend display driver. It implements the protocol from
include/xen/interface/io/displif.h [2].
Accompanying backend [3] is implemented
This patchset tries to add support for using writeback connector to
flatten a scene when it doesn't change for a while. This idea had
been floated around on IRC here [1] and here [2].
Developed on top of the latest writeback series, sent by Liviu here
[3].
Probably the patch should/could be broke
From: Oleksandr Andrushchenko
Provide kernel documentation for the Xen para-virtualized
frontend DRM driver.
Signed-off-by: Oleksandr Andrushchenko
---
Documentation/gpu/index.rst | 1 +
Documentation/gpu/xen-front.rst | 77 +
2 files changed, 78 in
On Tue, Mar 13, 2018 at 05:07:57PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No need to store the return value in a variable since we don't have to
> do any unwinding.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_modes.c | 15 ---
On Tue, Mar 13, 2018 at 04:48:26PM +0100, Gerd Hoffmann wrote:
> A driver to let userspace turn iovecs into dma-bufs.
>
> Use case: Allows qemu pass around dmabufs for the guest framebuffer.
> https://www.kraxel.org/cgit/qemu/log/?h=sirius/udmabuf has an
> experimental patch.
>
> Also allows qem
On Tue, Mar 13, 2018 at 04:52:02PM +0100, Christian König wrote:
> Am 13.03.2018 um 16:17 schrieb Daniel Vetter:
> > [SNIP]
> > > > I think a helper which both unmaps _and_ waits for all the fences to
> > > > clear
> > > > would be best, with some guarantees that it'll either fail or all the
> > >
On Mon, Mar 12, 2018 at 11:14:47PM -0700, John Hubbard wrote:
> On 03/12/2018 10:50 AM, Jerome Glisse wrote:
[...]
> Yes, on NVIDIA GPUs, the Host/FIFO unit is limited to 40-bit addresses, so
> things such as the following need to be below (1 << 40), and also accessible
> to both CPU (user space
Am 13.03.2018 um 16:17 schrieb Daniel Vetter:
[SNIP]
I think a helper which both unmaps _and_ waits for all the fences to clear
would be best, with some guarantees that it'll either fail or all the
mappings _will_ be gone. The locking for that one will be hilarious, since
we need to figure out d
A driver to let userspace turn iovecs into dma-bufs.
Use case: Allows qemu pass around dmabufs for the guest framebuffer.
https://www.kraxel.org/cgit/qemu/log/?h=sirius/udmabuf has an
experimental patch.
Also allows qemu to export guest virtio-gpu resources as host dmabufs.
Should be possible to
On Tue, Mar 13, 2018 at 04:35:02PM +0100, Michel Dänzer wrote:
> On 2018-03-13 04:20 PM, Daniel Vetter wrote:
> > On Tue, Mar 13, 2018 at 03:38:38PM +0100, Michel Dänzer wrote:
> >> On 2018-03-13 03:28 PM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä
> >>>
> >>> To make it possible for the core
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