On Di, 2017-03-07 at 21:49 +0100, Noralf Trønnes wrote:
> drm_debugfs_cleanup() now removes all minor->debugfs_list entries
> automatically, so it's not necessary to call
> drm_debugfs_remove_files().
>
> Cc: airl...@linux.ie
> Cc: kra...@redhat.com
> Signed-off-by: Noralf Trønnes
Reviewed-by: G
tree: git://people.freedesktop.org/~airlied/linux.git amdgpu-semaphores
head: daeb3d1adb4451fd27beb4dbded9d6477227225b
commit: daeb3d1adb4451fd27beb4dbded9d6477227225b [1/1] drm/amdgpu: add
semaphores
config: x86_64-randconfig-a0-03081402 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8
On Tue, Mar 07, 2017 at 03:30:30PM -0500, Alex Deucher wrote:
> On Fri, Feb 24, 2017 at 2:19 PM, Lukas Wunner wrote:
> > An external Thunderbolt GPU can neither drive the laptop's panel nor be
> > powered off by the platform, so there's no point in registering it with
> > vga_switcheroo. In fact,
Hi All,
The dsi + panel is a parental relationship, so OF grpah is not needed.
Therefore, the current dsi_parse_dt function will throw an error,
because there is no linked OF graph for case such as fimd + dsi +
panel.
So the 1/5 patch parse the Pll, burst and esc clock frequency
properties in dsi
Add the burst and esc clock frequency properties to the parent (DSI node).
Currently the clock is parsed from the port node, while it should be
taken from the dsi node.
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
arch/arm64/boot/dts/exynos/exynos5433-tm2-
The OF graph is not needed because the panel is a child of dsi. Remove
the ports node in DSI node, and port node in panel node.
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
arch/arm/boot/dts/exynos3250-rinato.dts | 21 -
arch/arm/boot/d
The OF graph is not needed because the panel is a child of dsi. Remove
the ports node in DSI node.
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 14 --
1 file changed, 14 deletions(-)
diff
Add the burst and esc clock frequency properties to the parent (DSI node).
Currently the clock is parsed from the port node, while it should be
taken from the dsi node.
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
arch/arm/boot/dts/exynos3250-rinato.dts |
The dsi + panel is a parental relationship, so OF grpah is not needed.
Therefore, the current dsi_parse_dt function will throw an error,
because there is no linked OF graph for the case fimd + dsi + panel.
Parse the Pll burst and esc clock frequency properties in dsi_parse_dt()
and create a bridge
>> + if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
>> + val = 1;
>> + else
>> + val = 0;
Isn't this better written as
val = (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC);
-- Stefan
___
dri
Oh, a slip of the finger :(, the headline should be "RK3399 cdn-dp patches"
On 03/08/2017 10:27 AM, Chris Zhong wrote:
Hi all
This series is to correct some mistakes in clk_get_rate and the register
address. And in order to better develop, adding more prints.
Chris Zhong (3):
drm/rockchip:
Correct some DP register address for PHY Configuration according to
latest datasheet.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h
b/drivers/gpu/drm/roc
The clk_get_rate return 0 if something goes wrong, so it can never be
less then zero, the ret should be set a error code, otherwise the
cdn_dp_clk_enable will return 0 when it failed at clk_get_rate.
In addition, clk_get_rate() returns an "unsigned long", so use
"unsigned long" instead of "u32" is
Hi all
This series is to correct some mistakes in clk_get_rate and the register
address. And in order to better develop, adding more prints.
Chris Zhong (3):
drm/rockchip: cdn-dp: return error code when clk_get_rate failed
drm/rockchip: cdn-dp: Correct PHY register address
drm/rockchip: cdn
In order to analyze some video config failed, add some useful
printouts.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
index 963d8ab..b14
https://bugs.freedesktop.org/show_bug.cgi?id=100104
--- Comment #1 from Michel Dänzer ---
Can you check if it's due to Mesa or LLVM, then bisect the one that triggered
it?
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dr
From: Hyungwon Hwang
This patch add the panel device tree node for S6E3HA2 display
controller to TM2 dts.
Signed-off-by: Hyungwon Hwang
Signed-off-by: Andrzej Hajda
Signed-off-by: Chanwoo Choi
Signed-off-by: Hoegeun Kwon
Tested-by: Chanwoo Choi
Reviewed-by: Javier Martinez Canillas
---
ar
The Samsung s6e3ha2 is a 5.7" 1440x2560 AMOLED panel connected
using MIPI-DSI interfaces.
Signed-off-by: Donghwa Lee
Signed-off-by: Hyungwon Hwang
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
Reviewed-by: Javier Martinez Canillas
Acked-by: Rob Herring
---
.../bindings/display/pane
This patch add support for MIPI-DSI based S6E3HA2 AMOLED panel
driver. This panel has 1440x2560 resolution in 5.7-inch physical
panel in the TM2 device.
Signed-off-by: Donghwa Lee
Signed-off-by: Hyungwon Hwang
Signed-off-by: Hoegeun Kwon
Tested-by: Chanwoo Choi
Reviewed-by: Andrzej Hajda
---
Dear Thierry,
I understand that your opinion is:
It is better to handle the error every time it is input to the
register, rather than error handling at once in the struct using
error. This not only makes the code easier to maintain, but also
reduces unnecessary computation.
So I modified the pane
https://bugs.freedesktop.org/show_bug.cgi?id=100058
--- Comment #9 from Michel Dänzer ---
(In reply to Adam Wolk from comment #7)
> Regarding the display flicking on/off (the effect feels like changing
> resolution - the way it goes out and back). This is completely mitigated by
> running DRI_PRI
Hi Paul,
After merging the rcu tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
In file included from include/linux/resource_ext.h:19:0,
from include/linux/pci.h:32,
from include/drm/drmP.h:50,
from drivers/gpu/drm/i915/i915
2017년 03월 07일 18:58에 Andrzej Hajda 이(가) 쓴 글:
> On 07.03.2017 10:12, Inki Dae wrote:
>> Thanks for fixing it.
>>
>> Andrzej,
>> DECON_CRFMID register is new to me. Where did you refer this register
>> description from? I couldn't find this register in datasheet I have for
>> Exynos5433.
>
> I h
Hi,
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
This is true for both channels, though we handle them differently.
>
> Signed-off-by: Maxime Ripard
> ---
>
Hi Neil,
On 07-03-2017 16:42, Neil Armstrong wrote:
> From: Laurent Pinchart
>
> In preparation for adding PHY operations to handle RX SENSE and HPD,
> group all the PHY interrupt setup code in a single location and extract
> it to a separate function.
>
> Signed-off-by: Laurent Pinchart
> Sign
On Tue, Mar 07, 2017 at 10:14:20AM -0700, Jordan Crouse wrote:
> Support per-instance pagetables for 5XX targets. Per-instance
> pagetables allow each open DRM instance to have its own VM memory
> space to prevent accidently or maliciously copying or overwriting
> buffers from other instances. It a
On Tue, Mar 07, 2017 at 06:16:51PM +0200, Jani Nikula wrote:
> On Mon, 06 Mar 2017, Javi Merino wrote:
> > I found these two minor issues while building an EDID. I'm not sure
> > whether the second patch (Add O= to support) is upstream material, but
> > I'm sending it just in case.
>
> I'm not o
Hi Neil,
On 07-03-2017 16:42, Neil Armstrong wrote:
> The HDMI TX controller support HPD and RXSENSE signaling from the PHY
> via it's STAT0 PHY interface, but some vendor PHYs can manage these
> signals independently from the controller, thus these STAT0 handling
> should be moved to PHY specifi
Hi Maxime,
On Tue, Mar 7, 2017 at 7:56 PM, Maxime Ripard
wrote:
> The video PLLs are used directly by the HDMI controller. Export them so
> that we can use them in our DT node.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi-ng/ccu-sun5i.h | 6 --
> include/dt-bindings/clock
On Wed, Feb 22, 2017 at 10:09:54AM +0900, Hoegeun Kwon wrote:
> From: Hyungwon Hwang
>
> This patch add the panel device tree node for S6E3HA2 display
> controller to TM2 dts.
>
> Signed-off-by: Hyungwon Hwang
> Signed-off-by: Andrzej Hajda
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Hoege
On Sun, 2017-02-26 at 22:45 +0100, Daniel Vetter wrote:
> On Tue, Feb 21, 2017 at 06:52:24PM +0200, Andy Shevchenko wrote:
> > On Tue, 2017-02-21 at 18:26 +0200, Jani Nikula wrote:
> > > On Tue, 21 Feb 2017, Andy Shevchenko > > l.co
> > > m> wrote:
> > > > The commit 213e08ad60ba ("drm/i915/bxt: a
Hi Neil,
On 07-03-2017 16:42, Neil Armstrong wrote:
> Some display pipelines can only provide non-RBG input pixels to the HDMI TX
> Controller, this patch takes the pixel format from the plat_data if provided.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |
On Tue, Mar 7, 2017 at 7:59 AM, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the sunxi tree got a conflict in:
>
> drivers/gpu/drm/sun4i/sun4i_drv.c
>
> between commit:
>
> 50480a78e282 ("drm: sun4i: use vblank hooks in struct drm_crtc_funcs")
>
> from the drm-misc tree an
On Mon, Jan 30, 2017 at 10:10:15AM +0100, Thierry Reding wrote:
> On Mon, Jan 30, 2017 at 10:03:44AM +0100, Daniel Vetter wrote:
> > On Mon, Jan 30, 2017 at 09:58:48AM +0100, Thierry Reding wrote:
> > > On Fri, Jan 27, 2017 at 03:05:46PM +0100, Daniel Vetter wrote:
> > > > On Fri, Jan 27, 2017 at 1
https://bugs.freedesktop.org/show_bug.cgi?id=100089
LunarG changed:
What|Removed |Added
QA Contact|intel-3d-bugs@lists.freedes |dri-devel@lists.freedesktop
On Sat, Feb 11, 2017 at 07:48:52PM +0100, Noralf Trønnes wrote:
> +const struct file_operations tinydrm_fops = {
> + .owner = THIS_MODULE,
> + .open = drm_open,
> + .release= drm_release,
> + .unlocked_ioctl = drm_ioctl,
> +#ifdef CONFIG_COMPAT
> + .co
https://bugs.freedesktop.org/show_bug.cgi?id=100095
--- Comment #1 from Marek Olšák ---
Not sure but this might help: https://reviews.llvm.org/D30717
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d
https://bugs.freedesktop.org/show_bug.cgi?id=100071
--- Comment #2 from Marek Olšák ---
Not sure but this might help: https://reviews.llvm.org/D30717
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d
On Tue, Mar 07, 2017 at 09:35:11PM +0100, Tomeu Vizoso wrote:
> Gabriel Krisman reported these warnings when building the documentation:
>
> ./drivers/gpu/drm/drm_dp_helper.c:1165: warning: No description found
> for parameter 'crtc'
> ./drivers/gpu/drm/drm_dp_helper.c:1166: warning: No descripti
On Tue, Mar 07, 2017 at 10:14:14AM -0700, Jordan Crouse wrote:
> Using the framework described here
>
> https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html
>
> This implements per-instance pagetables for the GPU driver creating an
> individual pagetable for each file descript
Hi Stephen, Daniel,
On Tue, Mar 07, 2017 at 11:10:19AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the sunxi tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> drivers/gpu/drm/sun4i/sun4i_crtc.c: In function 'sun4i_crtc_enable_vblank':
> drivers/gpu/dr
https://bugs.freedesktop.org/show_bug.cgi?id=99974
--- Comment #1 from Marek Olšák ---
Has it ever been fast? Even with a different GPU?
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dri-devel@list
Move the contents of msm_debugfs_cleanup() to msm_drm_uninit() to free
up the drm_driver->debugfs_cleanup callback. Also remove the
mdp_kms_funcs->debugfs_cleanup callback which has no users.
Cc: robdcl...@gmail.com
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/msm/msm_debugfs.c | 15 ---
Remove the .debugfs_cleanup() callback now that all the users are gone.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/drm_debugfs.c | 5 -
include/drm/drm_drv.h | 1 -
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
inde
drm_debugfs_cleanup() now removes all minor->debugfs_list entries
automatically, so it's not necessary to call drm_debugfs_remove_files().
Cc: airl...@linux.ie
Cc: kra...@redhat.com
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/qxl/qxl_debugfs.c | 13 -
drivers/gpu/drm/qxl/qxl_dr
This is a follow up that removes the drm_driver.debugfs_cleanup callback.
Tegra is the only remaining user of drm_debugfs_remove_files().
Note:
Patches are only compile tested.
Noralf.
Noralf Trønnes (3):
drm/msm: Remove msm_debugfs_cleanup()
drm/debugfs: Remove the drm_driver.debugfs_clea
On Tue, Mar 7, 2017 at 10:56 AM, Alex Deucher wrote:
> On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter wrote:
>> Hi all,
>>
>> In the 4.11 drm pull request Linus raised a few things that we need to
>> discuss:
>>
>> Late driver/enabling pull requests
>> --
>>
>> Imo
On Fri, Feb 24, 2017 at 2:19 PM, Lukas Wunner wrote:
> An external Thunderbolt GPU can neither drive the laptop's panel nor be
> powered off by the platform, so there's no point in registering it with
> vga_switcheroo. In fact, when the external GPU is runtime suspended,
> vga_switcheroo will cut
On Tue, Mar 07, 2017 at 10:56:49AM -0500, Alex Deucher wrote:
> On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter wrote:
> I've always tried to have all major new features sent to Dave by rc5,
> so no problems with the timelines. Dave and Linus have generally been
> ok with new asic support at strang
https://bugs.freedesktop.org/show_bug.cgi?id=99553
Vedran Miletić changed:
What|Removed |Added
Depends on||100105
Referenced Bugs:
https://bugs.
https://bugs.freedesktop.org/show_bug.cgi?id=100105
Vedran Miletić changed:
What|Removed |Added
Blocks||99553
URL|
https://bugs.freedesktop.org/show_bug.cgi?id=100105
Bug ID: 100105
Summary: Make Theano OpenCL support work on Clover and RadeonSI
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: m
Tomeu Vizoso writes:
> +
> +/**
> + * drm_dp_start_crc() - start capture of frame CRCs
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
> +{
> + u8 buf;
> +
Am Dienstag, den 28.02.2017, 15:18 +0100 schrieb Philipp Zabel:
> The DP (display processor) channel disable code tried to busy wait for
> the DP sync flow end interrupt status bit when disabling the partial
> plane without a full modeset. That never worked reliably, and it was
> disabled completel
Am Dienstag, den 28.02.2017, 15:18 +0100 schrieb Philipp Zabel:
> drm_atomic_helper_cleanup_planes only calls the cleanup_fb plane
> helpers, which we don't implement as a CMA framebuffer based driver.
> There is no reason to wait for vblanks in commit_tail only to do nothing
> afterwards.
>
> Sig
https://bugs.freedesktop.org/show_bug.cgi?id=100104
Bug ID: 100104
Summary: Gallium-9 hitting LLVM assert when trying to start
EVE-Online
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.
Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighbo
Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more
Since we have the infrastructure for IOMMU function tables it makes
sense to use it to differentiate between v1 and v2 targets. It adds
a bit more infrastructure but it also gives us the freedom to expand
on each flavor (especially v2) for things like dynamic domains.
Signed-off-by: Jordan Crouse
Use a TTBR1 pagetable for the GPU IOMMU domain and map all
the GPU kernel side buffer objects into that range. This
will make it easier to switch out TTBR0 for per-process
pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 --
drivers/gpu/d
Using the framework described here
https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html
This implements per-instance pagetables for the GPU driver creating an
individual pagetable for each file descriptor (so not strictly per-process
but in practice we can't share buffers betw
A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing in either case but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit a
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/drm/msm/msm_drv.h| 6 +-
drivers/gpu/drm/msm/msm_gem.h| 1 +
driver
Some A3XX and A4XX GPU targets required that the GPU clock be
programmed to a non zero value when it was disabled so
27Mhz was chosen as the "invalid" frequency.
Even though newer targets do not have the same clock restrictions
we still write 27Mhz on clock disable and expect the clock subsystem
t
If a OPP table is defined for the GPU device in the device tree use
that in lieu of the downstream style GPU frequency table. If we do
use the downstream table convert it to a OPP table so that we can
take advantage of the OPP lookup facilities later.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Instead of using a fixed list of clock names use the clock-names
list in the device tree to discover and get the list of clocks
that we need.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpu.c | 76 ++-
drivers/gpu/drm/msm/msm_gpu.h | 4 ++-
2
There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses
User space needs to know where the GMEM whole starts so that they
can set up the addressing correctly.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
include/uapi/drm/msm_drm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/m
Zero sized buffer objects tend to make various bits of the GEM
infrastructure complain:
WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389
drm_mm_insert_node_generic+0x258/0x2f0
Modules linked in:
CPU: 1 PID: 2323 Comm: drm-api-test Tainted: GW
4.9.0-rc4-00906-g693af44 #213
H
Hey Rob - here are a handful of new features and more extensive bug fixes that
might be suitable for 4.12.
Of note is the reference count for address spaces which is a pre-requisite for
per-instance pagetables and the move to OPP tables which is a stepping stone for
all sorts of clock related shen
There isn't any generic code that uses ->idle so remove it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 -
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 +
d
Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.
The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets
Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a5xx
In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple index
Add the infrastructure to support the idea of multiple ringbuffers.
Assign each ringbuffer an id and use that as an index for the various
ring specific operations.
The biggest delta is to support legacy fences. Each fence gets its own
sequence number but the legacy functions expect to use a unique
We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c. Plus it is better symmetry to have
the attach and detach at the same code level.
Signed-off-by: Jordan Crous
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++--
dri
Simply the code, use snprintf correct and make sure that we memset
the rest of the segment if the memory size in the ELF file is larger
than the file size.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 70 +
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 23
Here is v2 of the preemption series - Changes:
* Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov)
* Removed preemption worker and fixed atomics (Thanks Stephen Boyd)
* Various fixes and improvements based on testing
Thanks!
Jordan
Jordan Crouse (11):
drm/msm: Make sure to deta
On Tue, 7 Mar 2017 17:40:35 +0100
Daniel Vetter wrote:
> Jon, can you pls pick this one up, or want me to resend stand-alone?
I got it; I should get both applied before too long.
jon
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On Tue, 07 Mar 2017, Sean Paul wrote:
> On Tue, Mar 07, 2017 at 01:11:43AM +0100, Daniel Vetter wrote:
>> Linus shitting on dri-devel
>> ---
>>
> IMO, the best approach is to do exactly what danvet did last time:
> praise the contributor for their work and reiterate the li
priv->num_aspaces is increased and then checked to see if it still fits
in the priv->aspace array. If it doesn't, we warn and exit but
priv->num_aspaces remains incremented.
Don't incremement the count until we know that it fits in the array.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/ms
The interrupt status was being cleared before processing the handlers.
a5xx_rbbm_err_irq() was checking the interrupt status again, which would
likely turn out bad because the interrupt status would be 0 (or at least
different). Pass the original status to the function instead.
Also, skip clearing
Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR
section while maintaining backwards compatibility for tools that
only understand 32 bit iovas.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_rd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/
Instead of checking for a5xx_gpu->gpmu_iova during destroy we
accidently check a5xx_gpu->gpmu_bo.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/dr
Hey Rob, here are a handful of things that might be fixable for 4.11 but if not
consider them for -next.
Jordan
Jordan Crouse (4):
drm/msm: Fix wrong pointer check in a5xx_destroy
drm/msm: Don't increase priv->num_aspaces until we know that it fits
drm/msm: Pass interrupt status to a5xx_rbb
The HDMI TX controller support HPD and RXSENSE signaling from the PHY
via it's STAT0 PHY interface, but some vendor PHYs can manage these
signals independently from the controller, thus these STAT0 handling
should be moved to PHY specific operations and become optional.
The existing STAT0 HPD and
Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 322 +-
include/drm/bridge/dw_hdmi.h
The Amlogic GX SoCs implements a Synopsys DesignWare HDMI TX Controller
in combination with a very custom PHY.
Thanks to Laurent Pinchart's changes, the HW report the following :
Detected HDMI TX controller v2.01a with HDCP (Vendor PHY)
The following differs from common PHY integration as manage
In order to describe the RGB and YUB bus formats used to feed the
Synopsys DesignWare HDMI TX Controller, add missing formats to the
list of Bus Formats.
Documentation for these formats is added in a separate patch.
Signed-off-by: Neil Armstrong
---
include/uapi/linux/media-bus-format.h | 13 ++
This patch adds a new DRM documentation entry and links to the input
format table added in the dw_hdmi header.
Signed-off-by: Neil Armstrong
---
Documentation/gpu/dw-hdmi.rst | 15 +++
Documentation/gpu/index.rst | 1 +
2 files changed, 16 insertions(+)
create mode 100644 Documen
Add documentation for added Bus Formats to describe RGB and YUS formats used
as input to the Synopsys DesignWare HDMI TX Controller.
Signed-off-by: Neil Armstrong
---
Documentation/media/uapi/v4l/subdev-formats.rst | 4992 ++-
1 file changed, 3963 insertions(+), 1029 deletion
From: Laurent Pinchart
In preparation for adding PHY operations to handle RX SENSE and HPD,
group all the PHY interrupt setup code in a single location and extract
it to a separate function.
Signed-off-by: Laurent Pinchart
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/synopsys/dw-h
On Tue, 07 Mar 2017, Daniel Vetter wrote:
> Hi all,
>
> In the 4.11 drm pull request Linus raised a few things that we need to
> discuss:
>
> Late driver/enabling pull requests
> --
>
> Imo this isn't as one-sided as Linus made it sound, we've had the policy of
> p
On Thu, Mar 02, 2017 at 04:16:33PM +0100, Daniel Vetter wrote:
> We already had a super-short blurb, but worth extending it I think:
> We're still pretty far away from anything like a consensus, but
> there's clearly a lot of people who prefer an as-light as possible
> approach to converting existi
On Mon, 06 Mar 2017, Javi Merino wrote:
> I found these two minor issues while building an EDID. I'm not sure
> whether the second patch (Add O= to support) is upstream material, but
> I'm sending it just in case.
I'm not opposed to fixing existing issues like this, but really I think
there shou
The index overflow check in host1x_syncpt_get was incorrect,
and would return a pointer past the syncpt array if the
syncpt index given was the total number of syncpts. Fix
this.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/syncpt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletio
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