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that DAL
would have also had them.
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https://bugzilla.kernel.org/show_bug.cgi?id=86351
--- Comment #23 from Andy Furniss ---
I don't have a 270X anymore which I was using when first commenting in this
bug.
My current R9285 Tonga also has this issue and I've just tried setting 2048
(runtime) for prealloc and it doesn't help me.
I d
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https://bugzilla.kernel.org/show_bug.cgi?id=86351
--- Comment #22 from Alex Deucher ---
This should be re-assigned to the audio driver then.
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--- Comment #21 from Christian Birchinger ---
I was under the impression, that i already gave feedback about the
"Pre-allocated buffer size" value, but i guess i did not.
Anyway, a value of 2048 seems to fix the issue. I've tried normal stereo,
D
Allow the possibility to return an copy of the injected EDID when the connector
has been forced and an EDID has been specified over the debugfs interface.
Signed-off-by: Marius Vlad
---
drivers/gpu/drm/drm_edid.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
dif
ri-devel/attachments/20160323/0eb36752/attachment-0001.html>
Hey
On Wed, Mar 16, 2016 at 2:34 PM, Noralf Trønnes wrote:
> tinydrm provides a very simplified view of DRM for displays that has
> onboard video memory and is connected through a slow bus like SPI/I2C.
>
> Signed-off-by: Noralf Trønnes
> ---
> drivers/gpu/drm/Kconfig
On Wed, Mar 23, 2016 at 06:07:56PM +0100, Noralf Trønnes wrote:
>
> Den 18.03.2016 18:47, skrev Daniel Vetter:
> >On Thu, Mar 17, 2016 at 10:51:55PM +0100, Noralf Trønnes wrote:
> >>Den 16.03.2016 16:11, skrev Daniel Vetter:
> >>>On Wed, Mar 16, 2016 at 02:34:15PM +0100, Noralf Trønnes wrote:
>
Den 18.03.2016 18:47, skrev Daniel Vetter:
> On Thu, Mar 17, 2016 at 10:51:55PM +0100, Noralf Trønnes wrote:
>> Den 16.03.2016 16:11, skrev Daniel Vetter:
>>> On Wed, Mar 16, 2016 at 02:34:15PM +0100, Noralf Trønnes wrote:
tinydrm provides a very simplified view of DRM for displays that has
The CHIP has a composite output available muxed with the microphone in the
micro-jack plug.
Enable the composite output in its DTS.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-r8-c
The TCON, tv-encoder and display engine backends and frontends are combined
to create our display pipeline.
Add them to the R8 DTSI. It's supposed to be perfectly compatible with the
A10s and A13, but since we haven't tested it on them yet, it's safer to
just enable it on the R8. Eventually, it sh
Add the settings to support the NTSC standard.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index ccf275a90132..b
Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tv.c | 42
1 file changed, 42 insertions(+)
dif
Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.
Add support for that TV encoder.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile | 2 +
drivers/gpu/drm/sun4i/sun4i_
One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile | 1 +
drivers/gpu/drm/sun4i/sun
The display pipeline of the Allwinner A10 is involving several loosely
coupled components.
Add a documentation for the bindings.
Signed-off-by: Maxime Ripard
---
.../bindings/display/sunxi/sun4i-drm.txt | 254 +
1 file changed, 254 insertions(+)
create mode 100644
The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.
Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually
Sig
Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.
It is a 480x272 panel connected through a 24-bits RGB interface.
Signed-off-by: Maxime Ripard
Acked-by: Rob Herring
---
.../display/panel/olimex,lcd-olinuxino-43-ts.txt | 7 ++
drivers/gpu/drm/panel/pan
Otherwise, building with DEBUG_FS enabled will trigger a build warning
because we're using a structure that has not been declared.
Signed-off-by: Maxime Ripard
---
include/drm/drm_fb_cma_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/
It turns out that the A13 / R8 also have a tve encoder block, and a gate
for it.
Add it to the DT.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i-a13.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13.dt
The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.
Enable it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 22 +-
arch/arm/boot/dts/sun5i-r8.dtsi | 2 +-
2 files changed, 22 insertions(+), 2 de
Enable the display and TCON (channel 0 and channel 1) clocks that are going
to be needed to drive the display engine, tcon and TV encoders.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 38 +-
arch/arm/boot/dts/sun
Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i.dtsi | 43 +++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/su
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support the one found in the A13 / R8 SoCs.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu T
The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.
It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).
Add a driver for the channel 1 clock.
Signed-off-by: Maxime Ripard
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
Documentatio
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.
Add a driver to support both.
Signed-off-by: Maxime Ripard
Acked-by: Rob Herring
---
Documentation/d
The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.
While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.
Add a clk_unregister_com
Hi everyone,
The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.
Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
exa
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got artifacts without any feedback from kernel\xorg
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; bridge drivers as part of the panel
tree, but I have no objections at all for this to go in via one of the
trees where it is used and can actually be tested.
Thierry
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Hi
On Wed, Mar 23, 2016 at 12:56 PM, Chris Wilson
wrote:
> On Wed, Mar 23, 2016 at 12:30:42PM +0100, David Herrmann wrote:
>> My question was rather about why we do this? Semantics for EINTR are
>> well defined, and with SA_RESTART (default on linux) user-space can
>> ignore it. However, looping
As of current version the picture aspect ratio and active
aspect ratio are not being set when the video mode changes.
This patch fixes this problem by setting the picture aspect
ratio according to the current video mode and also sets the
active aspect ratio to be the same as picture aspect ratio.
On 19 January 2016 at 17:12, John Harrison wrote:
> On 19/01/2016 15:23, Gustavo Padovan wrote:
>>
>> Hi Daniel,
>>
>> 2016-01-19 Daniel Vetter :
>>
>>> On Fri, Jan 15, 2016 at 12:55:10PM -0200, Gustavo Padovan wrote:
From: Gustavo Padovan
This patch series de-stage the sync f
From: Gustavo Padovan
Let atomic_commit() wait on a collection of fences before proceed with
the scanout.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/drm_atomic.c| 9 +
drivers/gpu/drm/drm_atomic_helper.c | 9 +
include/drm/drm_crtc.h | 2 +-
3 files
From: Gustavo Padovan
Iterate over the array of fences and wait for all of the to finish.
Signed-off-by: Gustavo Padovan
---
drivers/dma-buf/fence.c | 16
include/linux/fence.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/dma-buf/fence.c b/drivers/dma-buf/
From: Gustavo Padovan
Put fence_collection data. For that calls fence_put() on all fences
and the user put callback.
Signed-off-by: Gustavo Padovan
---
drivers/dma-buf/fence.c | 17 +
include/linux/fence.h | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/dma-b
From: Gustavo Padovan
Creates a function that given an sync file descriptor returns a
fence_collection containing all fences in the sync_file.
Signed-off-by: Gustavo Padovan
---
drivers/dma-buf/sync_file.c | 36
include/linux/sync_file.h | 8
2
From: Gustavo Padovan
The struct aggregates fences that we need to wait on before proceed with
some specific operation. In DRM, for example, we may wait for a group of
fences to signal before we scanout the buffers related to those fences.
Signed-off-by: Gustavo Padovan
---
include/linux/fence
From: Gustavo Padovan
FENCE_FD can now be set by the user during an atomic IOCTL, it
will be used by atomic_commit to wait until the sync_file is signalled,
i.e., the framebuffer is ready for scanout.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/drm_atomic.c| 4
drivers/gpu/
From: Gustavo Padovan
Hi,
This is a first proposal to discuss the addition of in-fences support
to DRM. It adds a new struct to fence.c to abstract the use of sync_file
in DRM drivers. The new struct fence_collection contains a array with all
fences that a atomic commit needs to wait on
/**
*
On Wed, Mar 23, 2016 at 04:32:59PM +0100, David Herrmann wrote:
> Hi
>
> On Wed, Mar 23, 2016 at 12:56 PM, Chris Wilson
> wrote:
> > On Wed, Mar 23, 2016 at 12:30:42PM +0100, David Herrmann wrote:
> >> My question was rather about why we do this? Semantics for EINTR are
> >> well defined, and wi
Some sinks need some time during the process of resuming the system from
sleep before they're ready to handle transactions. While it would be
nice if they responded with NACKs in these scenarios, this isn't always
the case as a few sinks will just timeout on all of the transactions
they receive.
T
Some sinks need some time during the process of resuming the system from
sleep before they're ready to handle transactions. While it would be
nice if they responded with NACKs in these scenarios, this isn't always
the case as a few sinks will just timeout on all of the transactions
they receive.
T
n
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On Thu, 17 Mar 2016, Sebastian Reichel wrote:
> On Thu, Mar 17, 2016 at 02:14:26PM +0200, Laurent Pinchart wrote:
>> [...]
>> > +
>> > + /* panel is 480x464 with top and bottom 5 lines not visible */
>>
>> I assume you mean 480x864 ?
>
> Yes, nice catch. Basically the screen is 480x864,
clock_enable callback is used only by FIMD->DP pipeline. Similar but more
universal functionality provides pipeline clock.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_dp_core.c | 8 ++--
drivers/gpu/drm/exynos/exynos_drm_drv.h | 5 -
drivers/gpu/drm/exynos/exynos_d
According to documentation HDMI-PHY must be on prior to MIXER configuration.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_mixer.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 0a5a600
According to documentation and tests HDMI-PHY must be on prior
to MIXER configuration.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
b/drivers/gpu/drm/exynos/ex
HDMI-PHY clock should be accessible from other components in the pipeline.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 67 ++--
1 file changed, 48 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/driv
Components belonging to the same pipeline often requires
synchronized clocks. Such clocks are sometimes provided
by external clock controller, but they can be also provided by
pipeline components. In latter case there should be a way
to access them from another component belonging to the same pipel
The helper abstracts out conversion from pipeline
to crtc. Currently it is used in two places, but
there will be more uses in next patches.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 10 --
drivers/gpu/drm/exynos/exynos_drm_drv.h | 8
2 files c
Hi Inki,
In case of some pipielines there is need to set clock in one component
by driver of another component, for example:
1. Decon and Mixer driver must enable HDMI-PHY clock before configuration.
2. DP driver must enable DP clock provided by FIMD.
This set of patches provide more generic solu
decon_atomic_begin and decon_atomic_flush protects all windows already.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
b/drivers/gpu/drm/exynos/exynos5433_drm_de
Resetting IP at starting ensures that DECON will be in known state
regardless of changes by bootloader.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
b/drivers/gp
DECON should be updated after un-protecting windows and after changing
output parameters, otherwise image is not displayed in case of HDMI path.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
d
HDMI registry dump unnecessary spoils console and is not very helpful.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 263 ---
1 file changed, 263 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/ex
To ensure HDMI-PHY reprogramming will not affect
HDMI the latter should be reset.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 16951
HDMI-PHY power off bit defaults to 0 in older HDMI versions.
In case of Exynos5433 it defaults to 1. To make code
consistent across all versions this bit is always unset/set in
power on/off sequences.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 4
1 file changed,
Proper PHY configuration should be as follow:
1. set HDMI clock parents to OSCCLK.
2. reconfigure PHY.
3. set HDMI clock parents to PHY.
4. wait for PLL stabilization.
The patch fixes it and consolidates the code.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 22 ++
Hi Inki,
This set of patches provides set of different fixes and enhancements
for DECON -> HDMI path. It is based on:
- my HDMI patches which are not yet merged[1], could you look at them
by the way, they were posted about 5 months ago :)
- IOMMU patches by Marek (for some mysterious reason HDMI
e very helpful.
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On Tue, Mar 22, 2016 at 11:55:45PM +0900, Minchan Kim wrote:
> On Tue, Mar 22, 2016 at 02:50:37PM +0900, Joonsoo Kim wrote:
> > On Mon, Mar 21, 2016 at 03:31:02PM +0900, Minchan Kim wrote:
> > > We have allowed migration for only LRU pages until now and it was
> > > enough to make high-order pages.
https://bugzilla.kernel.org/show_bug.cgi?id=115141
Alex Deucher changed:
What|Removed |Added
CC||alexdeucher at gmail.com
--- Comment #3 f
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
index b108756..939d5c6 100644
--- a/drivers/gpu/drm/amd/dal/Kconfig
+++ b/drivers/gpu/drm/amd/dal/Kconf
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vi.c| 79 ++
2 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdg
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
index 1564485..5b3edb8 100644
--- a/drivers/gpu/dr
This adds core dc support for polaris 10 and 11.
v2: add missing files
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/Makefile|4 +
drivers/gpu/drm/amd/dal/dc/adapter/Makefile|4 +
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 12 +
.../adapt
From: Flora Cui
Signed-off-by: Flora Cui
Reviewed-by: Rex Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 6efd459..61
From: Rex Zhu
Signed-off-by: Rex Zhu
Acked-by: Flora Cui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 6 ++
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/
From: Rex Zhu
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris1
From: Rex Zhu
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index d0
From: Rex Zhu
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/p
From: Rex Zhu
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hw
From: Flora Cui
Signed-off-by: Flora Cui
Reviewed-by: Alex Deucher
Reviewed-by: Jammy Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 5bff0
From: Flora Cui
Signed-off-by: Flora Cui
Reviewed-by: Jammy Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +
drivers/gpu/drm/amd/amdgpu/vi.c| 87 ++
2 files changed, 89 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/
From: Flora Cui
46c34bcb6a15dd85329a39a5e72c62108626acdc put all blockâs clockgating
support in SMC. The sequence in suspend routine should be adjusted
accordingly, otherwise it causes asic hang.
Signed-off-by: Flora Cui
Reviewed-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
From: Eric Huang
Reviewed-by: Alex Deucher
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index faa0682..
From: Eric Huang
Signed-off-by: Eric Huang
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 ++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 353 +-
2 files changed, 364 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/a
From: Flora Cui
This is to workaround regression introduced in
46c34bcb6a15dd85329a39a5e72c62108626acdc. It should be reverted with a
final fix.
Signed-off-by: Flora Cui
Reviewed-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 --
1 file changed, 4 insertions(+), 2 delet
From: Eric Huang
Reviewed-by: Alex Deucher
Acked-by: Christian König
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 95 +++
1 file changed, 95 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgp
From: Eric Huang
Reviewed-by: Alex Deucher
Acked-by: Christian König
Signed-off-by: Eric Huang
---
.../powerplay/hwmgr/ellesmere_clockpowergating.c | 28 ++
.../powerplay/hwmgr/ellesmere_clockpowergating.h | 1 +
.../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c |
From: Eric Huang
Reviewed-by: Alex Deucher
Acked-by: Christian König
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 ++-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/
Needed for per CU powergating.
Reviewed-by: Alex Deucher
Acked-by: Christian König
Signed-off-by: Eric Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 +
drivers/gpu/drm/amd/include/cgs_common.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/driv
From: Eric Huang
Reviewed-by: Alex Deucher
Acked-by: Christian König
Signed-off-by: Eric Huang
---
.../powerplay/hwmgr/ellesmere_clockpowergating.c | 247 +
.../powerplay/hwmgr/ellesmere_clockpowergating.h | 2 +
.../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c |
From: Eric Huang
Reviewed-by: Alex Deucher
Acked-by: Christian König
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 81 +++
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +
2 files changed, 84 insertions(+)
diff --git a/drivers
From: yanyang1
sync the code form catalyst CL:#1230866.
Signed-off-by: yanyang1
Rviewed-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c | 51 ++-
.../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h | 1 +
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h|
From: yanyang1
update relational h files.
Signed-off-by: yanyang1
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h| 1 +
drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h| 10 --
drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h | 1 +
3
From: yanyang1
add CGS_UCODE_ID_SMU_SK.
Signed-off-by: yanyang1
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 12 +---
drivers/gpu/drm/amd/include/cgs_common.h | 1 +
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
From: Eric Huang
Signed-off-by: Eric Huang
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 3 +-
.../powerplay/hwmgr/ellesmere_clockpowergating.c | 153 +
.../powerplay/hwmgr/ellesmere_clockpowergating.h | 37 +
.../gpu/drm/amd/
From: Eric Huang
Signed-off-by: Eric Huang
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c | 39 +-
.../drm/amd/powerplay/hwmgr/ellesmere_thermal.c| 711 +
.../drm/amd/powerpl
From: Rex Zhu
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 3cb6d6c..261748c 100644
--- a/drivers/gpu/drm/amd/amd
From: Rex Zhu
Reviewed-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 5fb98aa..2c68199 100644
--- a
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