pointed to the most appropriate component of the two.
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aphics-drivers ppa)
xserver-xorg-video-radeon 1:7.5.99+git1508070731.3791fc~gd~t (same ppa)
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Hi,
On 16/12/2015 at 18:14:06 +0100, Thierry Reding wrote :
> Also, please use "drm/panel: " as the prefix (instead of "drm: panel: ")
> to make it easier for me to pick up things. I was about to send out a
> pull request for drm/panel when I noticed that there was this patch. The
> v4 wasn't Cc:
Different than kms_mmap_write_crc that captures the coherency issues within the
scanout mapped buffer, this one is meant for test dma-buf mmap on !llc
platforms mostly and provoke coherency bugs so we know where we need the sync
ioctls.
I tested this with !llc and llc platforms, BTY and IVY respec
This program can be used to detect when CPU writes in the dma-buf mapped object
don't land in scanout due cache incoherency.
Although this seems a problem inherently of non-LCC machines ("Atom"), this
particular test catches a cache dirt on scanout on LLC machines as well. It's
inspired in Ville's
This patch adds dma-buf mmap synchronization ioctls that can be used by tests
for cache coherency management e.g. when CPU and GPU domains are being accessed
through dma-buf at the same time.
Signed-off-by: Tiago Vignatti
---
lib/ioctl_wrappers.c | 26 ++
lib/ioctl_wrappe
This patch adds test_correct_cpu_write, which maps the texture buffer through a
prime fd and then writes directly to it using the CPU. It stresses the driver
to guarantee cache synchronization among the different domains.
This test also adds test_forked_cpu_write, which creates the GEM bo in one
p
From: Rob Bradford
This test has the following subtests:
- test_correct for correctness of the data
- test_map_unmap checks for mapping idempotency
- test_reprime checks for dma-buf creation idempotency
- test_forked checks for multiprocess access
- test_refcounting checks for buffer referen
This patch moves userptr definitions and helpers implementation that were
locally in gem_userptr_benchmark and gem_userptr_blits to the library, so other
tests can make use of them as well. There's no functional changes.
v2: added __ function to differentiate when errors want to be handled back in
Userspace is the one in charge of flush CPU by wrapping mmap with
begin{,end}_cpu_access.
v2: Remove LLC check cause we have dma-buf sync providers now. Also, fix return
before transferring ownership when mmap fails.
v3: Fix return values.
v4: !obj->base.filp is user triggerable, so removed the WA
This function is meant to be used with dma-buf mmap, when finishing the CPU
access of the mapped pointer.
The error case should be rare to happen though, requiring the buffer become
active during the sync period and for the end_cpu_access to be interrupted. So
we use a uninterruptible mutex_lock t
From: Daniel Vetter
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing dma-buf device drivers vfunc
This patch removes range-based information used for optimizations in
begin_cpu_access and end_cpu_access.
We don't have any user nor implementation using range-based flush. It seems a
consensus that if we ever want something like that again (or even more robust
using 2D, 3D sub-range regions) we c
From: Daniel Thompson
Currently DRM_IOCTL_PRIME_HANDLE_TO_FD rejects all flags except
(DRM|O)_CLOEXEC making it difficult (maybe impossible) for userspace
to mmap() the resulting dma-buf even when this is supported by the
DRM driver.
It is trivial to relax the restriction and permit read/write a
Hi all,
The last version of this work was sent a while ago here:
http://lists.freedesktop.org/archives/dri-devel/2015-August/089263.html
So let's recap this series:
1. it adds a vendor-independent client interface for mapping gem objects
through prime, IOW it implements userspace mma
On Wed, Dec 16, 2015 at 12:33 PM, Emil Velikov
wrote:
> Hi Laurent,
>
> On 14 December 2015 at 20:33, Laurent Pinchart
> wrote:
>> Hi Emil,
>>
>> On Monday 07 December 2015 14:13:43 Emil Velikov wrote:
>>> On 4 December 2015 at 22:27, Laurent Pinchart wrote:
>>> > The 8 high order bits of the bu
Hi Dave,
The following changes since commit 663a233eef643b38f36c05535cb5c9a4972edcc1:
Merge branch 'drm-header-fixes' of https://github.com/GabrielL/linux into
drm-next (2015-12-11 13:46:05 +1000)
are available in the git repository at:
git://anongit.freedesktop.org/tegra/linux tags/drm/te
Hi Dave,
The following changes since commit 8005c49d9aea74d382f474ce11afbbc7d7130bec:
Linux 4.4-rc1 (2015-11-15 17:00:27 -0800)
are available in the git repository at:
git://anongit.freedesktop.org/tegra/linux tags/drm/panel/for-4.5-rc1
for you to fetch changes up to d2a6f0f5597696ebf5bb34
Another pile of vfuncs from the old gpu.tmpl xml documentation that
I've forgotten to delete. I spotted a few more things to
clarify/extend in the new kerneldoc while going through this once
more.
Cc: Laurent Pinchart
Cc: Thierry Reding
Signed-off-by: Daniel Vetter
---
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https://bugzilla.kernel.org/show_bug.cgi?id=109481
Alex Deucher changed:
What|Removed |Added
CC||alexdeucher at gmail.com
--- Comment #1 f
og it seems like that's okay, though.
Thierry
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Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v6:
- Do not use bridge driver (Thierry Reding)
- Optimization the phy init sequence
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/
From: Liu Ying
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Change
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller
IP. This series adds support for a Synopsys DesignWare MIPI DSI host
controller DRM driver.
The MIPI DSI feature is tested on rk3288 evb board, backport them to
chrome os kernel chrome_v3.14, and it can display normally.
This
map2/omapfb/dss/hdmi4_core.c
> create mode 100644 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.h
> create mode 100644 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
> create mode 100644 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
> create mode 100644 drivers/video/fbdev/oma
ts framework, but that would be more complex to
> implement.
Well, even with this patch aliases are optional. The difference is that
if you don't have any aliases, and omapdrm starts, and one of the
multiple displays has not been probed yet, that display will be
unavailable. If you do have aliases, omapdrm ensures that the displays
with an alias are probed.
But... You are probably right, travelling the graph is better.
Tomi
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Hi Laurent,
On 14 December 2015 at 20:33, Laurent Pinchart
wrote:
> Hi Emil,
>
> On Monday 07 December 2015 14:13:43 Emil Velikov wrote:
>> On 4 December 2015 at 22:27, Laurent Pinchart wrote:
>> > The 8 high order bits of the buffer flags are reserved for internal use.
>> > Mask them out from th
https://bugzilla.kernel.org/show_bug.cgi?id=109481
Bug ID: 109481
Summary: Radeon Module crashing/freezing on ATI/AMD Evergreen
(Radeon HD6250, Wrestler)
Product: Drivers
Version: 2.5
Kernel Version: 4.3.3
Hardware: All
On Wed, Dec 16, 2015 at 10:52 AM, Tomi Valkeinen
wrote:
> Hi Dave,
>
> On 10/12/15 16:25, Tomi Valkeinen wrote:
>> Hi,
>>
>> Here's an RFC series to fix the mess we have at the moment with
>> omapdrm/omapfb/omapdss.
>
> There hasn't been any NACKs for this series, so I'd like to get this in
> for
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On Wed, Dec 16, 2015 at 11:19 AM, Thierry Reding
wrote:
> Hi Dave,
>
> The following changes since commit 8005c49d9aea74d382f474ce11afbbc7d7130bec:
>
> Linux 4.4-rc1 (2015-11-15 17:00:27 -0800)
>
> are available in the git repository at:
>
> git://anongit.freedesktop.org/tegra/linux tags/drm/p
On Tue, Dec 15, 2015 at 09:22:56AM -0800, Dmitry Torokhov wrote:
> On Tue, Dec 15, 2015 at 5:30 AM, Gustavo Padovan
> wrote:
> > 2015-12-14 Dmitry Torokhov :
> >
> >> Userspace can close the sync device while there are still active fence
> >> points, in which case kernel produces the following wa
On Tue, Dec 15, 2015 at 11:08:01AM -0800, Dmitry Torokhov wrote:
> On Tue, Dec 15, 2015 at 11:00 AM, Gustavo Padovan
> wrote:
> > 2015-12-15 Daniel Vetter :
> >
> >> On Mon, Dec 14, 2015 at 05:29:55PM -0800, Dmitry Torokhov wrote:
> >> > Userspace can close the sync device while there are still a
*/
Thanks,
Thierry
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, thanks.
Thierry
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There's a regression in the stable 4.2.x series.
With 4.2.7 I get the following within kern.log:
Dec 16 14:58:41 t44 kernel: [111050.930350] dvb-usb: found a 'Terratec Cinergy
T USB XXS (HD)/ T3' in cold state, will try to load a firmware
Dec 16 14:58:41 t44 kernel: [111050.930436] dvb-usb: down
On Wed, Dec 16, 2015 at 02:28:36PM +0100, Daniel Vetter wrote:
> On Wed, Dec 16, 2015 at 01:21:43PM +0100, Marek Szyprowski wrote:
> > This patch adds all infrastructure to make zpos plane property
> > configurable from userspace.
> >
> > Signed-off-by: Marek Szyprowski
>
> Imo zpos should be a
On 16.12.2015 15:31, Thierry Reding wrote:
> From: Thierry Reding
>
> Commit 88e72717c2de ("drm/irq: Use unsigned int pipe in public API")
> updated the prototype of this function but not the implementation. This
> wasn't noticed even through compile tests because the prototype is part
> of the so
From: Thierry Reding
Commit 88e72717c2de ("drm/irq: Use unsigned int pipe in public API")
updated the prototype of this function but not the implementation. This
wasn't noticed even through compile tests because the prototype is part
of the source file that uses it and hence the compiler won't kn
Hello,
On 2015-12-16 15:21, Daniel Vetter wrote:
> On Wed, Dec 16, 2015 at 02:54:04PM +0100, Marek Szyprowski wrote:
>> On 2015-12-16 14:28, Daniel Vetter wrote:
>>> On Wed, Dec 16, 2015 at 01:21:43PM +0100, Marek Szyprowski wrote:
This patch adds all infrastructure to make zpos plane propert
On Wed, Dec 16, 2015 at 02:54:04PM +0100, Marek Szyprowski wrote:
> Hello,
>
> On 2015-12-16 14:28, Daniel Vetter wrote:
> >On Wed, Dec 16, 2015 at 01:21:43PM +0100, Marek Szyprowski wrote:
> >>This patch adds all infrastructure to make zpos plane property
> >>configurable from userspace.
> >>
> >
Hello,
On 2015-12-16 14:28, Daniel Vetter wrote:
> On Wed, Dec 16, 2015 at 01:21:43PM +0100, Marek Szyprowski wrote:
>> This patch adds all infrastructure to make zpos plane property
>> configurable from userspace.
>>
>> Signed-off-by: Marek Szyprowski
> Imo zpos should be a generic atomic proper
On Wed, Dec 16, 2015 at 01:21:43PM +0100, Marek Szyprowski wrote:
> This patch adds all infrastructure to make zpos plane property
> configurable from userspace.
>
> Signed-off-by: Marek Szyprowski
Imo zpos should be a generic atomic property with well-defined semantics
shared across drivers. So
rnel: ---[ end trace 33afaf6a1bc49614 ]---
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Always use macro instead of hard-coded '2' value in conditions related
to video processor window. Additional checks are not needed, because
video layer is registered only when video processor is available.
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/exynos_mixer.c | 4 ++--
1 file
From: Tobias Jakobi
Allow the remaining alpha formats now that blending
is properly setup.
Signed-off-by: Tobias Jakobi
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/exynos_mixer.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/
Properly configure blending properties of given hardware layer based on
the selected pixel format. Currently only per-pixel-based alpha is possible
when respective pixel format has been selected. Configuration of global,
per-plane alpha value, color key and background color will be added later.
Th
From: Tobias Jakobi
Previously blending setup was static and most of it was
done in mixer_win_reset().
Signed-off-by: Tobias Jakobi
---
drivers/gpu/drm/exynos/exynos_mixer.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/dri
'zpos' plane property is configurable, so adjust hardware layers
priority based on the zpos value. 'zpos' value shifted by one can be
used directly as hw priority value and stored to the registers, because
mixer accepts priority values from 1 to 15 (0 means that layer is
disabled).
This patch also
This patch adds all infrastructure to make zpos plane property
configurable from userspace.
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/exynos_drm_drv.h | 4 ++-
drivers/gpu/drm/exynos/exynos_drm_plane.c | 51 ---
2 files changed, 49 insertions(+), 6
This patch renames zpos entry to index, because in most places it is
used as index for selecting hardware layer/window instead of
configurable layer position. This will later enable to make the zpos
property configurable.
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/exynos5433_drm_
Hello all,
This is a continuation of the work started by Tobias Jakobi. The goal of
this patch set is to remove hardcoded blending setup from Exynos Mixer
driver. This patch also enables other Exynos DRM CRTC drivers to use the
configurable plane zpos feature, however patches for FIMD or Decon are
On 12.11.2015 14:48, Thierry Reding wrote:
> On Wed, Nov 11, 2015 at 09:12:33PM +0100, poma wrote:
>> On 10.11.2015 17:25, Mario Kleiner wrote:
>>> On 11/10/2015 05:00 PM, Thierry Reding wrote:
On Tue, Nov 10, 2015 at 03:54:52PM +0100, Mario Kleiner wrote:
> From: Daniel Vetter
>
It may caused a dead lock if we flush the hpd work in bridge disable time.
The normal flow would like:
IN --> DRM IOCTL
1. Acquire crtc_ww_class_mutex (DRM IOCTL)
IN --> analogix_dp_bridge
2. Acquire hpd work lock (Flush hpd work)
3. HPD work already in idle, no need to
Turn off the panel power in suspend time would help to reduce
power waste.
Signed-off-by: Yakir Yang
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
After test on rockchiop platform, i found sometims driver would failed
at reading EDID message. After debugging more, i found that it's okay
to read_a byte from i2c, but it would failed at AUX transcation if we
try to ready multi-bytes from i2c.
Driver just can't received the AUX CH reply command,
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not s
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Tested-by: Javier Marti
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10:
- Remove the surplus "plat_data" check. (Heiko)
- switc
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes i
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
C
Add dt binding documentation for rockchip display port PHY.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v11:
- Correct the title of this rockchip dp phy document(Rob)
- Add the ack from Rob Herring
Changes in v10: None
Changes in v9: None
Changes
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v11: None
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
BIT(4) ->
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v11: None
Changes in v10:
- Add the ack from Rob Herring
Changes
Hi all,
Today's linux-next merge of the drm-misc tree got conflicts in:
drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
between commit:
8fbf9d92a7bc ("drm/vmwgfx: Implement the cursor_set2 callback v2")
from Linus' tree and
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP inde
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compati
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Tested-by: Javie
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Signed-off-by: Yakir
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7G
On 12/15/15 21:43, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20151215:
>
on i386, when CONFIG_PM_SLEEP is not enabled:
../drivers/gpu/drm/vc4/vc4_v3d.c: In function 'vc4_v3d_set_power':
../drivers/gpu/drm/vc4/vc4_v3d.c:157:29: error: called object is not a function
or function pointe
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Chang
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
contro
Hi Daniel,
Am Dienstag, den 15.12.2015, 02:57 +0800 schrieb Daniel Kurtz:
> HI Philipp,
>
> This driver is looking really good.
>
> But, still some things to think about (mostly small) inline below...
Most of my answers below seem to be "ok" or some form thereof, but I
have one or two questions
i
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On Tue, Dec 15, 2015 at 09:03:14PM +0200, Jyri Sarha wrote:
> From: Tomi Valkeinen
>
> LCDC hardware does not support fb pitch that is different (i.e. larger)
> than the screen size. The driver currently does no checks for this, and
> the results of too big pitch are are flickering and lower fps.
Op 15-12-15 om 18:19 schreef Dmitry Torokhov:
> On Tue, Dec 15, 2015 at 2:01 AM, Maarten Lankhorst
> wrote:
>> Op 15-12-15 om 02:29 schreef Dmitry Torokhov:
>>> Userspace can close the sync device while there are still active fence
>>> points, in which case kernel produces the following warning:
>
On Tue, Dec 15, 2015 at 05:25:56PM -0500, Lyude wrote:
> We currently call drm_helper_hpd_irq_event() to handle reprobing
> displays on resume, however drm_helper_hpd_irq_event() only checks the
> status of hpd. HPD doesn't update if the displays connected changed
> before resuming the system, and
Hi Heiko,
On 12/15/2015 08:06 AM, Heiko Stübner wrote:
> Hi Yakir,
>
> Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang:
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into brid
> -Original Message-
> From: Kristian Høgsberg [mailto:hoegsberg at gmail.com]
> Sent: Tuesday, December 15, 2015 4:09 AM
> To: Song, Ruiling ; krh at bitplanet.net;
> Winiarski,
> Michal
> Cc: intel-gfx at lists.freedesktop.org; mesa-dev at lists.freedesktop.org; Ben
> Widawsky ; dri-
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