On 2015ë
02ì 19ì¼ 22:22, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Hi,
>
> Here goes some clean ups to the exynos drivers. The main clean ups is
> the presetting and zpos making the property immutable and the removal
> of *_win_data structures.
With your cleanup patch set, the pla
cool.. something along the lines of:
git pull --rebase drm-next
and then
git mergetool
should do the job
Thanks :-)
BR,
-R
On Thu, Mar 12, 2015 at 11:31 PM, John Hunter wrote:
> Fine, I will try to catch up.
> Thanks anyway.
>
> Have a nice day,
> John
>
> On Fri, Mar 13, 2015 at 11:07 A
On some board, TE GPIO should be configured properly thoughout pinctrl driver
as an wakeup interrupt. So this gpio should be configurable in the board's DT,
not being requested as a input pin.
Signed-off-by: Hyungwon Hwang
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 4 ++--
1 file changed, 2 i
MIC must be initilized by MIPI DSI when it is being bound.
Signed-off-by: Hyungwon Hwang
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
in
From: Donghwa Lee
This patch adds support for Exynos5433. The goal is achieved by
1. Getting the address of registers from driver data
2. Getting the fixed value for registers from driver data
3. Getting different number of clocks using driver data
4. Getting max frequency of pixel clock from dri
MIC(Mobile image compressor) is newly added IP in Exynos5433. MIC
resides between decon and mipi dsim, and compresses frame data by 50%.
With dsi, not display port, to send frame data to the panel, the
bandwidth is not enough. That is why this compressor is introduced.
Signed-off-by: Hyungwon Hwan
When there are multiple ports or multiple endpoints in a port, they have to be
distinguished by the value of reg property. It is common. The drivers can get
the specific endpoint in the specific port via this function. Now the drivers
have to implement this code in themselves or have to force the o
From: Joonyoung Shim
DECON(Display and Enhancement Controller) is new IP replacing FIMD in
Exynos5433. This patch adds Exynos5433 decon driver.
Signed-off-by: Joonyoung Shim
Signed-off-by: Hyungwon Hwang
---
.../devicetree/bindings/video/exynos-decon.txt | 65 +++
drivers/gpu/drm/exynos/
This patchset is based on the git(branch name: exynos-drm-next) which is
maintained by Inki Dae.
https://kernel.googlesource.com/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
This patchset adds 2 new device drivers, decon and mic, and adds support for
Exynos5433 mipi dsi. To enable display in a
The number of overlay planes is one less than the maximum number of
planes, because the one is used for primary plane.
Signed-off-by: Hyungwon Hwang
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_d
Since commit abc0b1447d4974963548777a5ba4a4457c82c426 ("drm: Perform
basic sanity checks on probed modes"), it became mandatory to set
the pixel clock of the panel. This patch sets the pixel clock properly.
Signed-off-by: Hyungwon Hwang
---
arch/arm/boot/dts/exynos4412-trats2.dts | 2 +-
1 file
On Thu, Mar 12, 2015 at 10:53 PM, John Hunter wrote:
> Got it, maybe I should work on the drm-next or latest linux master.
>
> I am working on the drm git repo below for now as Daniel Vetter told me
> git://people.freedesktop.org/~airlied/linux
> I am quite confused now 'cause there are a bounch o
ion :)
>>> Here you remove code added in the previous patch.
>>> It would be better to just apply patch 2 first and then rebase patch 1
>>> on top of it.
>> Thanks, I will reorder patch 1 & patch 2, in next vesion :)
> regards
> Philipp
>
regards :)
Yakir
>
>
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On Thu, Mar 12, 2015 at 4:02 AM, John Hunter wrote:
> From: John Hunter
>
> IMHO, some annotations were copypaste from somewhere else, it is
> obviously not rightly modified. Hope I am right with that.
> ---
> drivers/gpu/drm/drm_crtc.c | 115
> ++---
> 1
;> +
>> +hdmi->id.gpaud = config3_id & HDMI_CONFIG3_ID_GPAUD ? true : false;
>> +hdmi->id.ahbauddma = config3_id & HDMI_CONFIG3_ID_AHBAUDDMA ?
>> + true : false;
>> +
>> +hdmi->id.design = hdmi_readb(hdmi, HD
Hi Philipp,
On 2015å¹´03æ12æ¥ 18:24, Philipp Zabel wrote:
> Am Samstag, den 28.02.2015, 21:32 -0500 schrieb Yakir Yang:
>> Signed-off-by: Yakir Yang
>> ---
>> Changes in v4: None
>> Changes in v3:
>> - Setting the .pm member instead of suspend/resume
>>
>> Changes in v2:
>> - Add suspend/resum
Hi Philipp,
On 2015å¹´03æ12æ¥ 18:24, Philipp Zabel wrote:
> Hi Yakir,
>
> Am Samstag, den 28.02.2015, 21:28 -0500 schrieb Yakir Yang:
>> Wrap irq control in functions, and then we can call in
>> dw_hdmi_bind/dw_hdmi_unbind/dw_hdmi_resume/dw_hdmi_suspend
>> functions.
>>
>> Signed-off-by: Yakir
;
> uint64_t valid_mask = 0;
> +
> for (i = 0; i < property->num_values; i++)
> valid_mask |= (1ULL << property->values[i]);
> return !(value & ~valid_mask);
> @@ -3326,6 +3321,7 @@ int drm_mode_obj_get_properties_ioctl(struct
> drm_device *dev, void *data,
> }
> }
> arg->count_props = props_count;
> +
> out:
> mutex_unlock(&dev->mode_config.mutex);
> return ret;
> @@ -3487,7 +3483,6 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
> out:
> mutex_unlock(&dev->mode_config.mutex);
> return ret;
> -
> }
>
> int drm_mode_gamma_get_ioctl(struct drm_device *dev,
> @@ -3535,6 +3530,7 @@ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
> ret = -EFAULT;
> goto out;
> }
> +
> out:
> mutex_unlock(&dev->mode_config.mutex);
> return ret;
> @@ -3668,6 +3664,7 @@ int drm_mode_create_dumb_ioctl(struct drm_device
> *dev,
>
> if (!dev->driver->dumb_create)
> return -ENOSYS;
> +
> return dev->driver->dumb_create(file_priv, dev, args);
> }
>
> --
> 1.9.1
>
>
>
--
Best regards
Junwang Zhao
Microprocessor Research and Develop Center
Department of Computer Science &Technology
Peking University
Beijing, 100871, PRC
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Add the recently added hdmi power supplies to evb and firefly boards.
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rk3288-evb.dtsi | 2 ++
arch/arm/boot/dts/rk3288-firefly.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dt
At least the Rockchip variant of the dw_hdmi can have controllable power
supplies
providing 1.0 and 1.8V. Therefore add the possibility for the generic bridge
driver to enable supplies provided by the hw-specific drivers.
Signed-off-by: Heiko Stuebner
---
changes since v2:
- rename supplies to t
On Thu, Mar 12, 2015 at 8:49 PM, John Hunter wrote:
> Hi Rob,
>
> On Thu, Mar 12, 2015 at 10:34 PM, Rob Clark wrote:
>>
>> On Thu, Mar 12, 2015 at 10:15 AM, John Hunter wrote:
>> > Hi,
>> > I really don't whether I am doing things on right workflow of
>> > dri-devel.
>> > I am new to this commu
Unfortunately we used the enabled flag in struct drm_crtc instead of the
enabled flag in struct atmel_hlcdc_crtc. This obviously leads to
discrepancies on crtc enable state.
This patch fixes the issue by using the struct atmel_hlcdc_crtc enabled
flag in PM support.
Signed-off-by: Sylvain Rochet
Hi Philipp
On 12 March 2015 at 10:58, Philipp Zabel wrote:
> Currently the imx-drm driver misuses the V4L2_PIX_FMT constants to describe
> the
> pixel format on the parallel bus between display controllers and encoders. Now
> that MEDIA_BUS_FMT is available, use that instead.
I've tested this s
On 12.03.2015 17:48, Oded Gabbay wrote:
> From: Ben Goz
>
> The current CP firmware can handle Usermode Queues only on MEC1.
> To reflect this firmware change, this commit reduces number of compute
> pipelines
> to 4 - 1, from 8 - 1 (the first pipeline is allocated for kgd).
>
> Signed-off-by:
On 12.03.2015 06:14, Alex Deucher wrote:
> On Wed, Mar 11, 2015 at 4:51 PM, Alex Deucher
> wrote:
>> On Wed, Mar 11, 2015 at 2:21 PM, Christian König
>> wrote:
>>> On 11.03.2015 16:44, Alex Deucher wrote:
radeon_bo_create() calls radeon_ttm_placement_from_domain()
before ttm_bo_i
From: Jeff McGee
New test core_getparams consists of 2 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: subslice total or EU total. drm/i915 implementation of
these queries is required for Cherryview and Gen9+ devices (non-
simulated).
v2:
ceiving this mail because:
You are the assignee for the bug.
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Introduce msm_drm_sub_dev for each mdp interface component such as
HDMI/eDP/DSI to contain common information shared with MDP.
Signed-off-by: Jilai Wang
---
drivers/gpu/drm/msm/edp/edp.c | 18 +--
drivers/gpu/drm/msm/edp/edp.h | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c
From: John Hunter
IMHO, some annotations were copypaste from somewhere else, it is
obviously not rightly modified. Hope I am right with that.
---
drivers/gpu/drm/drm_crtc.c | 115 ++---
1 file changed, 56 insertions(+), 59 deletions(-)
diff --git a/driver
2015-03-12 Inki Dae :
> On 2015ë
02ì 19ì¼ 22:22, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > Hi,
> >
> > Here goes some clean ups to the exynos drivers. The main clean ups is
> > the presetting and zpos making the property immutable and the removal
> > of *_win_data structures.
Hi Yakir,
Am Donnerstag, den 12.03.2015, 22:31 +0800 schrieb yakir:
> Hi Philipp,
>
> On 2015å¹´03æ12æ¥ 18:24, Philipp Zabel wrote:
> > Hi Yakir,
> >
> > Am Samstag, den 28.02.2015, 21:28 -0500 schrieb Yakir Yang:
> >> Wrap irq control in functions, and then we can call in
> >> dw_hdmi_bind/dw
In intel_crtc_page_flip, intel_display.c, the code changed the framebuffer
assigned to plane crtc->primary by
crtc->primary->fb = fb;
However, it forgot to change crtc->primary->state->fb. However, when we
switch to console, some kernel code will read crtc->primary->state->fb
to get the framebuff
Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda
Reviewed-by: Javier Martinez Canillas
Tested-by: Javier Martinez Canillas
---
arch/arm/boot/dts/exynos5420.dtsi | 2 ++
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda
Reviewed-by: Javier Martinez Canillas
Tested-by: Javier Martinez Canillas
Reviewed-by: Sylwester Nawrocki
---
arch/arm/bo
Since Exynos5420 there are async-bridges (ASB) between different IPs. These
bridges must be operational during power domain on/off, ie. clocks used
by these bridges should be enabled.
This patch enabled these clocks during domain on/off.
Signed-off-by: Andrzej Hajda
Reviewed-by: Javier Martinez C
The patch adds bindings for clocks required by async-bridges
present in the particular power domain.
Signed-off-by: Andrzej Hajda
Reviewed-by: Javier Martinez Canillas
Tested-by: Javier Martinez Canillas
---
Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 3 +++
1 file changed,
Hi Kukjin,
This is resend of my patchset with added (Reviewed|Tested)-by tags and removed
RFC
prefix.
Exynos chipsets since 542x have asynchronous bridges connecting different IPs.
These bridges should be operational during power domain switching, ie associated
clocks cannot be gated.
This patch
Hi,
On 03/09/2015 06:41 PM, Stephane Viau wrote:
> This change adds the hw configuration for msm8x16 chipsets in
> mdp5_cfg module.
>
> Note that only one external display interface is present in this
> configuration (DSI) but has not been enabled yet. It will be enabled
> once drm/msm driver supp
On 05/02/15 13:35, Andrzej Hajda wrote:
> Since Exynos5420 there are async-bridges (ASB) between different IPs. These
> bridges must be operational during power domain on/off, ie. clocks used
> by these bridges should be enabled.
> This patch enabled these clocks during domain on/off.
>
> Signed-o
On 06/02/15 11:55, Andrzej Hajda wrote:
> FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
> therefore their clocks should be enabled during power domain switch.
>
> Signed-off-by: Andrzej Hajda
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 6 --
> 1 file changed, 4 in
On Thu, Mar 12, 2015 at 10:08:54AM +0800, Zhigang Gong wrote:
> LGTM,
>
> Reviewed-by: Zhigang Gong
>
> Thanks.
>
Thanks for the review, Zhigang.
With beignet portion reviewed, review should be able to proceed for
the i915, libdrm, and igt parts. These are all quite simple. Can someone(s)
ple
On Wed, Mar 11, 2015 at 08:21:36AM +0100, Daniel Vetter wrote:
> On Tue, Mar 10, 2015 at 01:06:44PM -0700, Jeff McGee wrote:
> > On Tue, Mar 10, 2015 at 07:47:03PM +0100, Daniel Vetter wrote:
> > > On Tue, Mar 10, 2015 at 01:58:52PM -0400, Rob Clark wrote:
> > > > On Tue, Mar 10, 2015 at 12:59 PM,
From: Jeff McGee
New test core_getparams consists of 2 subtests, each one testing
the ability of userspace to query the correct value of a GT config
attribute: subslice total or EU total. drm/i915 implementation of
these queries is required for Cherryview and Gen9+ devices (non-
simulated).
v2:
Since commit 0f04cf8df0b20a97369cb634663fef0578cbf273 ("drm/exynos:
fix wrong pipe calculation for crtc"), fimd_clear_channel() can be
called when is_drm_iommu_supported() returns true. In this case,
the kernel is going to be panicked because crtc is not set yet.
[1.211156] [drm] Initialized d
Checking whether the iommu mapping allocated is not enough to determine
whether iommu is supported properly or not. Even though there is mapping,
the kernel is going to be panicked without the iommu being allocated.
So this patch adds the additional condition to check whether iommu is
really suppor
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Each HW component's driver such as HDMI/eDP/DSI should be able to
compiled as a module which allows user to prevent this part of code
to be compiled if not needed.
Signed-off-by: Jilai Wang
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 13 +--
drivers/gpu/drm/msm/edp/edp.c |
On Thu, 12 Mar 2015 18:02:56 +0900
Michel Dänzer wrote:
> struct ttm_place::lpfn is honoured even with TTM_PL_FLAG_TOPDOWN, so
> latter should work with RADEON_GEM_CPU_ACCESS. It sounds like the
> problem is really that some BOs are expected to be within a certain
> range from the beginning of V
2015-03-12 Inki Dae :
> On 2015ë
02ì 19ì¼ 22:22, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > Hi,
> >
> > Here goes some clean ups to the exynos drivers. The main clean ups is
> > the presetting and zpos making the property immutable and the removal
> > of *_win_data structures.
2015-03-11 7:18 GMT+01:00 CK Hu :
> Add devicetree bindings for IT6151 MIPI to eDP bridge chip driver.
>
> Signed-off-by: CK Hu
> Signed-off-by: Jitao Shi
Please use scripts/get_maintainer.pl for all people to which send the
next version of the patch set.
Thanks,
Matthias
> ---
> Documentatio
On 03/12/2015 11:23 AM, Christian König wrote:
> On 12.03.2015 10:02, Michel Dänzer wrote:
>> On 12.03.2015 06:14, Alex Deucher wrote:
>>> On Wed, Mar 11, 2015 at 4:51 PM, Alex Deucher
>>> wrote:
On Wed, Mar 11, 2015 at 2:21 PM, Christian König
wrote:
> On 11.03.2015 16:44, Al
Am Samstag, den 28.02.2015, 21:35 -0500 schrieb Yakir Yang:
> By parsing the identification registers we can know what functions
> are present on the hdmi ip.
>
> Signed-off-by: Yakir Yang
> ---
> Changes in v4:
> -Correct phy_type assignment bug
>
> Changes in v3:
> - Add ID registers parse and
Am Samstag, den 28.02.2015, 21:32 -0500 schrieb Yakir Yang:
> Signed-off-by: Yakir Yang
> ---
> Changes in v4: None
> Changes in v3:
> - Setting the .pm member instead of suspend/resume
>
> Changes in v2:
> - Add suspend/resume support for dw_hdmi_rockchip driver
>
> drivers/gpu/drm/rockchip/dw
Hi Yakir,
Am Samstag, den 28.02.2015, 21:28 -0500 schrieb Yakir Yang:
> Wrap irq control in functions, and then we can call in
> dw_hdmi_bind/dw_hdmi_unbind/dw_hdmi_resume/dw_hdmi_suspend
> functions.
>
> Signed-off-by: Yakir Yang
[...]
> @@ -1702,17 +1722,8 @@ EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
Am Donnerstag, 12. März 2015, 10:00:47 schrieb Paul Bolle:
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/it6151.c
> >
> > +#include
>
> This file can only be built-in. So I couldn't help but notice this
> include. And if I remove it
> make drivers/gpu/drm/bridge/it6151.o
>
> still run
On 03/12/2015 11:04 AM, Michel Dänzer wrote:
> On 12.03.2015 17:48, Oded Gabbay wrote:
>> From: Ben Goz
>>
>> The current CP firmware can handle Usermode Queues only on MEC1.
>> To reflect this firmware change, this commit reduces number of compute
>> pipelines
>> to 4 - 1, from 8 - 1 (the fir
Hi Philipp,
On 03/12/15 10:58, Philipp Zabel wrote:
> Currently the imx-drm driver misuses the V4L2_PIX_FMT constants to describe
> the
> pixel format on the parallel bus between display controllers and encoders. Now
> that MEDIA_BUS_FMT is available, use that instead.
>
> I'd like to get the V4
This patch makes the fsl,data-width and fsl,data-mapping device tree
properties optional if a panel is connected to the ldb output port
via the of_graph bindings. The data mapping is determined from the
display_info.bus_format field provided by the panel.
Signed-off-by: Philipp Zabel
---
drivers
The LDB driver changes the attached display interface's input clock mux
to the LDB_DI clock reference. Change it back again when disabling the
LVDS display. Changing back to the PLL5 for example allows to configure
the same DI for HDMI output later.
Signed-off-by: Philipp Zabel
---
drivers/gpu/d
This patch allows to optionally attach the lvds-channel to a panel
supported by a drm_panel driver using of-graph bindings, instead of
supplying the modes via display-timings in the device tree.
This depends on of_graph_get_port_by_id and uses the OF graph to
link the optional DRM panel to the LDB
This patch consolidates the different interface_pix_fmt, pixel_fmt, pix_fmt,
and pixfmt variables to a common name "bus_format" wherever they describe the
pixel format on the bus between display controller and encoder hardware.
At the same time, it renames imx_drm_panel_format to imx_drm_set_bus_fo
imx-drm internally misused the V4L2_PIX_FMT constants, which are supposed to
describe the pixel format of frame buffers in memory, to describe the pixel
format on the bus between the display controller and the encoder hardware.
Now that MEDIA_BUS_FMT constants are available to drm drivers, use thos
Commit 9e74d2926a28 ("staging: imx-drm: add LVDS666 support for parallel
display") describes a 24-bit bus format where three 6-bit components each
take the lower part of 8 bits with the two high bits zero padded. Add a
component-wise padded media bus format RGB666_1X24_CPADHI to support this
connec
This patch adds the media bus format for a 24-bit bus format with three
8-bit YUV components.
Signed-off-by: Philipp Zabel
Acked-by: Laurent Pinchart
---
Documentation/DocBook/media/v4l/subdev-formats.xml | 37 ++
include/uapi/linux/media-bus-format.h | 3 +-
2
This patch adds two more 24-bit RGB formats. BGR888 is more or less common,
GBR888 is used on the internal connection between the IPU display interface
and the TVE (VGA DAC) on i.MX53 SoCs.
Signed-off-by: Philipp Zabel
Acked-by: Laurent Pinchart
---
Documentation/DocBook/media/v4l/subdev-format
This patch adds three new RGB media bus formats that describe
18-bit or 24-bit samples transferred over an LVDS bus with three
or four differential data pairs, serialized into 7 time slots,
using standard SPWG/PSWG/VESA or JEIDA data ordering.
Signed-off-by: Philipp Zabel
Acked-by: Sakari Ailus
From: Boris Brezillion
Add RGB444_1X12 and RGB565_1X16 format definitions and update the
documentation.
Signed-off-by: Boris Brezillon
Acked-by: Mauro Carvalho Chehab
Acked-by: Sakari Ailus
Acked-by: Laurent Pinchart
Signed-off-by: Philipp Zabel
---
Documentation/DocBook/media/v4l/subdev-f
Currently the imx-drm driver misuses the V4L2_PIX_FMT constants to describe the
pixel format on the parallel bus between display controllers and encoders. Now
that MEDIA_BUS_FMT is available, use that instead.
I'd like to get the V4L2 maintainers' acks for the four necessary media
bus format patch
From: Ben Goz
The current CP firmware can handle Usermode Queues only on MEC1.
To reflect this firmware change, this commit reduces number of compute pipelines
to 4 - 1, from 8 - 1 (the first pipeline is allocated for kgd).
Signed-off-by: Ben Goz
Signed-off-by: Oded Gabbay
---
drivers/gpu/drm
Hi Dave -
More i915 fixes, three out of four are fixes to old bugs, cc: stable.
BR,
Jani.
The following changes since commit 9eccca0843205f87c00404b663188b88eb248051:
Linux 4.0-rc3 (2015-03-08 16:09:09 -0700)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel
On 12.03.2015 10:30, Oded Gabbay wrote:
>
> On 03/12/2015 11:23 AM, Christian König wrote:
>> On 12.03.2015 10:02, Michel Dänzer wrote:
>>> On 12.03.2015 06:14, Alex Deucher wrote:
On Wed, Mar 11, 2015 at 4:51 PM, Alex Deucher
wrote:
> On Wed, Mar 11, 2015 at 2:21 PM, Christian KÃ
On Thu, Mar 12, 2015 at 10:15 AM, John Hunter wrote:
> Hi,
> I really don't whether I am doing things on right workflow of dri-devel.
> I am new to this community and I want to help.
> Could anybody spare some time to tell me the right way .
> Thanks.
Hi John,
I don't actually see the original
On 12.03.2015 10:02, Michel Dänzer wrote:
> On 12.03.2015 06:14, Alex Deucher wrote:
>> On Wed, Mar 11, 2015 at 4:51 PM, Alex Deucher
>> wrote:
>>> On Wed, Mar 11, 2015 at 2:21 PM, Christian König
>>> wrote:
On 11.03.2015 16:44, Alex Deucher wrote:
> radeon_bo_create() calls radeon_tt
Convert the timestamping in the amdkfd driver to use
a timespec64 and 64bit time accessors.
Cc: Arnd Bergmann
Cc: Oded Gabbay
Cc: David Airlie
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: John Stultz
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 +-
1 file changed, 5 inse
LGTM,
Reviewed-by: Zhigang Gong
Thanks.
> -Original Message-
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> jeff.mcgee at intel.com
> Sent: Tuesday, March 10, 2015 7:36 AM
> To: beignet at lists.freedesktop.org
> Cc: intel-gfx at lists.freedesktop.org;
Just a few nits, I'm afraid.
On Wed, 2015-03-11 at 14:18 +0800, CK Hu wrote:
> drivers/gpu/drm/bridge/Kconfig | 10 +
> drivers/gpu/drm/bridge/Makefile | 1 +
I applied 1/2 and 2/2 on top of next-20150312 to check a trivial issue.
The chunks for these two files needed context cha
Hi Dave,
Some additional radeon fixes for 4.0
The following changes since commit cd961bb9eebb630452f49dcbf3e5f0059428614a:
drm/mst: fix recursive sleep warning on qlock (2015-03-10 13:44:31 +1000)
are available in the git repository at:
git://people.freedesktop.org/~agd5f/linux drm-fixes-4
On Thu, Mar 12, 2015 at 5:23 AM, Christian König
wrote:
> On 12.03.2015 10:02, Michel Dänzer wrote:
>>
>> On 12.03.2015 06:14, Alex Deucher wrote:
>>>
>>> On Wed, Mar 11, 2015 at 4:51 PM, Alex Deucher
>>> wrote:
On Wed, Mar 11, 2015 at 2:21 PM, Christian König
wrote:
>
Reviewed-by: Sinclair Yeh
On Thu, Mar 12, 2015 at 03:42:34AM +0800, kbuild test robot wrote:
>
> Signed-off-by: Fengguang Wu
> ---
> vmwgfx_kms.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
> b/drivers/gpu/drm/vmwgfx/vmwgfx
assignee for the bug.
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Signed-off-by: Fengguang Wu
---
vmwgfx_kms.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 8344504..5a3be8d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwg
tree: git://people.freedesktop.org/~thomash/linux vmwgfx-next
head: 51850be6365084dc3ff6516bb9d89c6d7e3a98f1
commit: fd465bad8cb18eb6e99aa81bc1349c221250391f [4/7] drm/vmwgfx: Major KMS
refactoring / cleanup in preparation of screen targets
reproduce:
# apt-get install sparse
git checkout
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On 2015ë
02ì 19ì¼ 22:22, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> We already set each plane zpos at init, after that changes to zpos are
> not expected. This patch turns zpos into a read-only property so now it is
> impossible to set zpos.
>
> Signed-off-by: Gustavo Padovan
> ---
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