Hi Thierry,
Ping~.
Or is it ok to pick up this patch to my tree, exynos-drm-next? It
doesn't seem to care for a long time.
Thanks,
Inki Dae
On 2014ë
12ì 09ì¼ 18:29, Hyungwon Hwang wrote:
> From: Inki Dae
>
> This patch adds MIPI-DSI based S6E63J0X03 AMOLED LCD panel driver
> which uses m
> The long-term solution
That was the part that I missed in the description. Please note
somewhere that we still need to improve this.
Apart from that the patches look fine to me, but I need more time to
review them in detail.
Regards,
Christian.
Am 31.12.2014 um 15:06 schrieb Oded Gabbay:
>
>
This patch adds support for Himax HX8369A panel.
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm menuconfig and manually choose to build in
the Himax HX8369A panel driver
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/configs/imx_v
This patch adds support for MIPI DSI host controller.
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm menuconfig and manually choose to build in
the MIPI DSI host controller driver
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/con
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* Replace the bs[
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v3->v4:
* None.
v2->v3:
* As suggested by Phillip Zabel, change the clocks and the clock-names
properties to use the pllref and core_cfg clocks only.
v1->
This patch adds support for Himax HX8369A MIPI DSI panel.
Reviewed-by: Andrzej Hajda
Signed-off-by: Liu Ying
---
v7->v8:
* Remove several unnecessary headers included in the driver.
v6->v7:
* Address Andrzej Hajda's following comments.
* Simplify the return logic in hx8369a_dcs_write().
* R
This patch adds device tree bindings for Himax HX8369A DRM panel driver.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* Merge the bs[3:0]-gpios properties into one property - bs-gpios.
This addresses Andrzej Hajda's comment.
v3->v4:
* Newly intro
This patch adds support for Synopsys DesignWare MIPI DSI host controller
which is embedded in the i.MX6q/sdl SoCs.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Make the checkpatch.pl script be happier.
v4->v5:
* None.
v3->v4:
* Move the relevant dt-bindings to a
This patch adds device tree bindings for i.MX specific Synopsys DW MIPI DSI
driver.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless pllref_gate clock from the requir
This patch adds Synopsys DesignWare MIPI DSI host controller driver support.
Currently, the driver supports the burst with sync pulses mode only.
Signed-off-by: Liu Ying
---
v7->v8:
* Fix the driver's Kconfig so that we may pass the allmodconfig for ARM.
v6->v7:
* None.
v5->v6:
* Make the ch
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Add the #address-cells and #size-cells properties in the example 'ports'
node.
* Remove the useless input-port pr
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* Address the over 80 characters in one line warning reported by the
checkpatch.pl script.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp()
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripher
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output. The MIPI DSI host controller embedded in the
i.MX
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals. This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output. So, this patch changes the
hsi_tx clock to be a s
According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr
clock's parent should be the video_27m clock. The i.MX6DL reference manual
has the same statement. This patch changes the hdmi_isfr clock's parent
from the pll3_pfd1_540m clock to the video_27m clock.
Suggested-by: Philipp
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
arch/arm/mach-imx/clk-imx6q.c |
This patch adds a macro to define the GPR3 MIPI muxing control register field
shift bits.
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 +
1
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ven
Signed-off-by: Liu Ying
---
v7->v8:
* None.
v6->v7:
* None.
v5->v6:
* None.
v4->v5:
* None.
v3->v4:
* Fix an ordering issue to address Stefan Wahren's comment.
v2->v3:
* None.
v1->v2:
* None.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
--
Hi,
This version mainly fixes the Kconfig for the Synopsys DesignWare MIPI DSI
host controller bridge driver so that we may pass the allmodconfig for ARM.
Also, this version contains a minor change for the Himax HX8369A panel
driver to remove several unnecessary headers included.
The i.MX MIPI DS
On 12/31/2014 03:49 PM, Christian König wrote:
> Am 31.12.2014 um 14:39 schrieb Oded Gabbay:
>> Background:
>>
>> amdkfd needs GART memory for several things, such as runlist packets,
>> MQDs, HPDs and more. Unfortunately, all of this memory must be always
>> pinned (due to several reasons which
Reviewed-by: Alexey Skidanov
Signed-off-by: Oded Gabbay
---
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 47d0b87..448
Reviewed-by: Alexey Skidanov
Signed-off-by: Oded Gabbay
---
drivers/gpu/drm/radeon/radeon_kfd.c | 99 +
1 file changed, 1 insertion(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c
b/drivers/gpu/drm/radeon/radeon_kfd.c
index ddd2afd..56bf
This patch change the calls throughout the amdkfd driver from the old kfd-->kgd
interface to the new kfd gtt sa inside amdkfd
Reviewed-by: Alexey Skidanov
Signed-off-by: Oded Gabbay
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 23
drivers/gpu/drm/amd/amdkfd/kfd_kernel_q
This patch changes the calls to allocate the gart memory for amdkfd from the
old interface (radeon_sa) to the new one (kfd_gtt_sa)
The new gart sub-allocator is initialized with chunk size equal to 512 bytes.
This is because the KV MQD is 512 Bytes and most of the sub-allocations are
MQDs.
Review
This patch makes the gart's buffer size calculation more accurate. This buffer
is needed per GPU.
It takes into account maximum number of MQDs, runlist packets, kernel queues
and reserves 512KB for other misc allocations.
The total size is just shy of 4MB, for 32 processes and 128 queues per
proc
This patch adds new kfd gtt sub-allocator functions that service the amdkfd
driver when it wants to use gtt memory.
The sub-allocator uses a bitmap to handle the memory area that was transferred
to it during init. It divides the memory area into chunks, according to chunk
size parameter.
The allo
This patch adds new fields to kfd_dev struct that are necessary for the new kfd
gtt sa module
Reviewed-by: Alexey Skidanov
Signed-off-by: Oded Gabbay
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/
This patch adds the implementation of the gtt interface functions.
The allocate function will allocate a single bo, pin and map it to kernel
memory. It will return the gpu address and cpu ptr as arguments.
Reviewed-by: Alexey Skidanov
Signed-off-by: Oded Gabbay
---
drivers/gpu/drm/radeon/radeo
This patch adds two new functions to the kfd-->kgd interface:
init_gtt_mem_allocation, which allocate a large enough buffer on the amdkfd
needs, such as mqds, hpds, kernel queue, fence and runlists. This function
is only called once per GPU device. The size of the allocated buffer is
based on the
Background:
amdkfd needs GART memory for several things, such as runlist packets,
MQDs, HPDs and more. Unfortunately, all of this memory must be always
pinned (due to several reasons which were discussed during the
initial review of amdkfd).
Current Solution:
The current (short/mid-term) sol
Am 31.12.2014 um 14:39 schrieb Oded Gabbay:
> Background:
>
> amdkfd needs GART memory for several things, such as runlist packets,
> MQDs, HPDs and more. Unfortunately, all of this memory must be always
> pinned (due to several reasons which were discussed during the
> initial review of amdkfd).
c: OpenPGP digital signature
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Jonas,
On Wed, Dec 31, 2014 at 09:55:19AM +0100, Jonas Lundqvist wrote:
> Hi Jeremiah,
>
> On 12/30/2014 11:52 PM, Jeremiah Mahler wrote:
> > You changed 'i' but you didn't explain in your log message why you did this.
>
> I can change the commit message to something more generic. "Move code
> o
eiving this mail because:
You are the assignee for the bug.
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mments seem related to
r600g only.
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