https://bugzilla.kernel.org/show_bug.cgi?id=86431
--- Comment #4 from Alex Deucher ---
The radeon driver has initialized fine. There are no displays wired to the
radeon card at all. It's purely for rendering offload. If you are not getting
a display it's an issue with the intel driver.
--
Yo
https://bugzilla.kernel.org/show_bug.cgi?id=86431
--- Comment #3 from brent s. ---
Dmesg output attached.
The panel isn't attached to the AMD card? The ACPI issues in the other bug seem
related to AMD, and it affects the display, even in TTY, so I had thought
otherwise.
Let me know if you need
https://bugzilla.kernel.org/show_bug.cgi?id=86431
--- Comment #2 from brent s. ---
Created attachment 154051
--> https://bugzilla.kernel.org/attachment.cgi?id=154051&action=edit
dmesg output on 3.16.4-1
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Alex Deucher changed:
What|Removed |Added
CC||alexdeucher at gmail.com
--- Comment #1 fr
https://bugzilla.kernel.org/show_bug.cgi?id=86431
brent s. changed:
What|Removed |Added
Regression|No |Yes
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brent s. changed:
What|Removed |Added
Blocks||84221
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Bug ID: 86431
Summary: ATI/AMD Radeon HD 8670A/8670M/8750M not initializing
Product: Drivers
Version: 2.5
Kernel Version: >= 3.16.0
Hardware: All
OS: Linux
Tre
Well, making a long story short:
http://yarchive.net/comp/linux/bitfields.html
Regards,
Christian.
Am 16.10.2014 um 16:14 schrieb Alex Deucher:
> As part of the amdgpu transition, we are moving to using database
> generated register and packet headers. We have a number of options
> for formatti
https://bugzilla.kernel.org/show_bug.cgi?id=86401
Bug ID: 86401
Summary: radeon: fatal exception in interrupt
Product: Drivers
Version: 2.5
Kernel Version: 3.14.14
Hardware: All
OS: Linux
Tree: Mainline
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Hi Dave,
First round of fixes for 3.18.
- Use gart for DMA ring tests to avoid caching issues with HDP
- SI dpm stability fixes
- Performance stabilization fixes
- misc other things
The following changes since commit dfda0df3426483cf5fc7441f23f318edbabecb03:
drm/mst: rework payload table alloc
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On 16/10/14 15:33, Cheng, Yao wrote:
> Hi Emil,
> Sorry, what do you mean by "correctly aligned"? does it mean the paddings in
> this data structure?
>
Afaict for compatibility reasons the struct size have to be "aligned"
(multiple of 8 bytes), or if you prefer - the struct is missing the
require
Hi
On Thu, Oct 16, 2014 at 3:39 PM, Cheng, Yao wrote:
> Accepted :) I will update the patch to implement the mmap interface and
> remove the legacy MMAP_IOCTL.
> BTW I didn't see a field to get mmap_offset in struct drm_gem_open, I guess
> something like a new "GET_MMAP_OFFSET_IOCTL" need be a
> Ok, bunch of comments. First a high-level one: I think this qualifies as a new
> subsystem of i915, and so it would be good to extract this into a new file
> (i915_ved.c maybe), including adding kerneldoc for the setup function, a
> short DOC: overview section and pulling it all into the drm kern
On Wed, Oct 15, 2014 at 4:13 AM, Thierry Reding
wrote:
> Finally, if this IP block is a VP8 video decoding engine only, I'm not
> sure DRM is the best subsystem for it. Traditionally video decoding has
> been done primarily in V4L2. I'm not sure that's the best fit given that
> it was originally d
Hi Daniel, this patch
[RFC PATCH 3/3] libdrm: user mode helper for ipvr drm driver
adds the ipvr part into libdrm.
Do you mean this patch is missing?
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Thursday, October
Hi Emil,
Sorry, what do you mean by "correctly aligned"? does it mean the paddings in
this data structure?
> -Original Message-
> From: Emil Velikov [mailto:emil.l.velikov at gmail.com]
> Sent: Wednesday, October 15, 2014 5:24 PM
> To: Cheng, Yao; intel-gfx at lists.freedesktop.org
> Cc:
ping!
On Fri, Oct 10, 2014 at 6:33 PM, Ajay kumar wrote:
> On Wed, Oct 8, 2014 at 12:39 PM, Thierry Reding
> wrote:
>> On Tue, Oct 07, 2014 at 05:49:24PM +0300, Laurent Pinchart wrote:
>>> Hi Ajay,
>>>
>>> On Tuesday 07 October 2014 16:06:55 Ajay kumar wrote:
>>> > On Tue, Oct 7, 2014 at 4:00 PM
We need ww mutexes and need to rewrite i915 a bit fo fix this all. I.e.
known issue. As long as your userspace isn't nasty nothing bad will ever
happen though.
-Daniel
On Mon, Oct 13, 2014 at 08:40:33PM +0200, Marcin ?lusarz wrote:
> =
> [ INFO: possible
On Mon, Oct 13, 2014 at 08:15:00PM +0800, Yao Cheng wrote:
> drm/ipvr is a new GEM driver for baytrail's vxd392, which accelerates VP8
> video decoding.
> The driver name "ipvr" means the PowerVR's IP wrapped by Intel. In the
> future, ipvr may support other platforms such as Merrifield.
> Code i
Hi Daniel/Hermann,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Thursday, October 16, 2014 6:29 PM
> To: Cheng, Yao
> Cc: David Herrmann; Vetter, Daniel; Intel Graphics Development; Jiang, Fei;
> dri-devel at lists.freed
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On Wed, Oct 15, 2014 at 10:13:15AM +0200, Thierry Reding wrote:
> On Tue, Oct 14, 2014 at 08:50:35AM -0700, Sean V Kelley wrote:
> > On Tue, Oct 14, 2014 at 4:53 AM, Thierry Reding
> > wrote:
> > > On Mon, Oct 13, 2014 at 08:15:00PM +0800, Yao Cheng wrote:
> > >> drm/ipvr is a new GEM driver for b
On Wed, Oct 15, 2014 at 02:14:33AM +, Cheng, Yao wrote:
> Hi Herrmann
>
> > -Original Message-
> > From: David Herrmann [mailto:dh.herrmann at gmail.com]
> > Sent: Monday, October 13, 2014 10:27 PM
> > To: Cheng, Yao
> > Cc: Intel Graphics Development; Jiang, Fei; dri-devel at
> > lis
The page offset is 12 bits. For example if we have an
8 GB VM, we'd need 33 bits. The number of bits needed
for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20
(log2(8) + 17).
Noticed by Alexey during code review.
Signed-off-by: Alex Deucher
Cc: stable at vger.kernel.org
---
drivers/gpu/drm/r
On Mon, Oct 13, 2014 at 08:15:01PM +0800, Yao Cheng wrote:
> Setup following resources during i915_driver_load:
> 1. create a child platform and resource
> 2. allocate a new IRQ line and irq chip
> 3. set up IRQ mask/unmask callbacks
> vxd392 driver (if installed) will bind itself to the
> platform
Hi Ajay,
On Friday 10 October 2014 18:33:05 Ajay kumar wrote:
> On Wed, Oct 8, 2014 at 12:39 PM, Thierry Reding wrote:
> > On Tue, Oct 07, 2014 at 05:49:24PM +0300, Laurent Pinchart wrote:
> >> On Tuesday 07 October 2014 16:06:55 Ajay kumar wrote:
> >> > On Tue, Oct 7, 2014 at 4:00 PM, Tomi Valkei
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On 10/16/2014 10:14 AM, Alex Deucher wrote:
> Are there any strong objections to these sorts of structures?
You may want to blacklist certain compiler version/arch combinations,
or get the affected arches to do it.
gcc up to 4.7.1 on ia64 and ppc64 generates 64-bit wide RMW cycles
on bitfields, r
From: Thierry Reding
The memory allocated for a nouveau_cli object in nouveau_cli_create() is
never freed. Free the memory in nouveau_cli_destroy() to plug this leak.
kmemleak recorded this after running a couple of nouveau test programs.
Note that kmemleak points at drm_open_helper() because fo
ng on here.
Thierry
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Hi
On Wed, Oct 15, 2014 at 4:14 AM, Cheng, Yao wrote:
> Hi Herrmann
>
>> -Original Message-
>> From: David Herrmann [mailto:dh.herrmann at gmail.com]
>> Sent: Monday, October 13, 2014 10:27 PM
>> To: Cheng, Yao
>> Cc: Intel Graphics Development; Jiang, Fei; dri-devel at
>> lists.freedesk
Limit primary to qemu vgamem size, to avoid reaching
qemu guest bug "requested primary larger than framebuffer"
on resizing screen too large to fit.
Remove unneeded and misleading variables.
Related to:
https://bugzilla.redhat.com/show_bug.cgi?id=1127552
Signed-off-by: Marc-Andr? Lureau
---
dr
On Thu, Oct 16, 2014 at 10:14:27AM -0400, Alex Deucher wrote:
> As part of the amdgpu transition, we are moving to using database
> generated register and packet headers. We have a number of options
> for formatting, some of which involve bitfields (don't worry there
> will also be shift/mask styl
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On Tue, Oct 14, 2014 at 12:25 PM, Michele Curti
wrote:
> remove some dpm functions never called, mostly xxx_dpm_reset_asic
> functions. Here the list:
> * btc_dpm_reset_asic
> * ci_power_control_set_level
> * ci_set_boot_state
> * ci_dpm_power_control_set_level
> * ci_dpm_reset_asic
> * cyp
On Tue, Oct 14, 2014 at 12:25 PM, Michele Curti
wrote:
> include radeon_asic.h header file in the various xxx_dpm.c files
> to reduce sparse false positive warnings. Not so great patch
> in itself, but reducing warning count from 391 to 258 may help
> to see real problems..
>
> Signed-off-by: Mic
As part of the amdgpu transition, we are moving to using database
generated register and packet headers. We have a number of options
for formatting, some of which involve bitfields (don't worry there
will also be shift/mask style headers as well which is mainly what we
use in the code). I think t
radeon: clean up coding style differences in radeon_get_bios()
Signed-off-by: Wilfried Klaebe
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c
b/drivers/gpu/drm/radeon/radeon_bios.c
index 6a03624..63ccb8f 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bio
On Thu, Oct 16, 2014 at 7:36 AM, Cheng, Yao wrote:
> Hi Daniel, this patch
> [RFC PATCH 3/3] libdrm: user mode helper for ipvr drm driver
> adds the ipvr part into libdrm.
> Do you mean this patch is missing?
The umd (ipvr_vaapi_driver) is needed to fully exercise the APIs
exposed. That
On 10/13/2014 12:16 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> Add a function, of_find_mipi_dsi_device_by_node(), that can be used to
> resolve a phandle to a MIPI DSI device.
>
> Signed-off-by: Thierry Reding
Acked-by: Andrzej Hajda
--
Regards
Andrzej
> ---
> drivers/gpu/drm/drm_mi
On 10/13/2014 12:16 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> Many peripherals require DCS commands to be sent in low power mode and
> will fail to correctly process them in high speed mode. Section 5.2 of
> the MIPI DSI specification also mandates that on bidirectional lanes,
> data sh
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