On Monday, July 07, 2014 10:06:59 PM Daniel Vetter wrote:
> On Mon, Jul 07, 2014 at 10:01:27PM +0200, Rafael J. Wysocki wrote:
> > On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
> > > On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
> > > > On Tuesday, June 24, 2014 02:
On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
wrote:
> The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller supports at least one primary plane and might
>
or the bug.
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Hi Greg,
On 2 July 2014 11:07, Greg KH wrote:
> On Tue, Jul 01, 2014 at 12:57:02PM +0200, Maarten Lankhorst wrote:
>> So after some more hacking I've moved dma-buf to its own subdirectory,
>> drivers/dma-buf and applied the fence patches to its new place. I believe
>> that the
>> first patch sho
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Hi Daniel,
The patch below also works. You can use my Tested By for it.
Thanks
Ed Tomlinson
PS. I _really_ need to get a serial console working on my i7 box.
On Monday 07 July 2014 14:26:54 Daniel Vetter wrote:
> On Mon, Jul 07, 2014 at 06:45:49AM -0400, Ed Tomlinson wrote:
> > Daniel,
> >
>
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the bug.
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ssignee for the bug.
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But maybe I did something wrong
somewhere, that's very possible.
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On Mon, Jul 07, 2014 at 10:01:27PM +0200, Rafael J. Wysocki wrote:
> On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
> > On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
> > > On Tuesday, June 24, 2014 02:43:02 PM Jani Nikula wrote:
> > > > On Thu, 19 Jun 2014, Randy Dun
ttp://lists.freedesktop.org/archives/dri-devel/attachments/20140707/9b60d2f7/attachment.html>
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On Monday, July 07, 2014 04:54:23 PM Daniel Vetter wrote:
> On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
> > On Tuesday, June 24, 2014 02:43:02 PM Jani Nikula wrote:
> > > On Thu, 19 Jun 2014, Randy Dunlap wrote:
> > > > On 06/18/14 23:16, Stephen Rothwell wrote:
> > > >> Hi
use mm.h definition
Cc: Alex Deucher
Cc: David Airlie
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Fabian Frederick
---
drivers/gpu/drm/radeon/radeon_fb.c | 2 +-
drivers/gpu/drm/radeon/radeon_gem.c| 2 +-
drivers/gpu/drm/radeon/radeon_object.c | 2 +-
3 files changed, 3 inser
use mm.h definition
Cc: David Airlie
Cc: Patrik Jakobsson
Cc: Daniel Vetter
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Fabian Frederick
---
drivers/gpu/drm/gma500/framebuffer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/gma500/framebuffe
On Mon, Jul 07, 2014 at 07:58:30PM +0200, Paolo Bonzini wrote:
> Il 07/07/2014 19:54, Daniel Vetter ha scritto:
> >On Mon, Jul 07, 2014 at 04:57:45PM +0200, Paolo Bonzini wrote:
> >>Il 07/07/2014 16:49, Daniel Vetter ha scritto:
> >>>So the correct fix to forward intel gpus to guests is indeed to s
https://bugzilla.kernel.org/show_bug.cgi?id=79591
--- Comment #4 from Stefan Ringel ---
static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo)
{
if (bo->bdev->driver->move_notify)
bo->bdev->driver->move_notify(bo, NULL);
if (bo->ttm) {
ttm_tt_unbind(bo->ttm)
org/archives/dri-devel/attachments/20140707/7cfd09c9/attachment.html>
Il 07/07/2014 19:54, Daniel Vetter ha scritto:
> On Mon, Jul 07, 2014 at 04:57:45PM +0200, Paolo Bonzini wrote:
>> Il 07/07/2014 16:49, Daniel Vetter ha scritto:
>>> So the correct fix to forward intel gpus to guests is indeed to somehow
>>> fake the pch pci ids since the driver really needs them.
On Mon, Jul 07, 2014 at 04:57:45PM +0200, Paolo Bonzini wrote:
> Il 07/07/2014 16:49, Daniel Vetter ha scritto:
> >So the correct fix to forward intel gpus to guests is indeed to somehow
> >fake the pch pci ids since the driver really needs them. Gross design, but
> >that's how the hardware works.
form
the game developers about my analysis and then close this bug.
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https://bugzilla.kernel.org/show_bug.cgi?id=79591
--- Comment #3 from Martin Peres ---
I was referring to freedesktop's bug tracker. Reporting bugs to Nouveau is
explained here: http://nouveau.freedesktop.org/wiki/Bugs/
But that's ok, no need to report it once again ;)
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Enable LCD related nodes and reference panel node in the hlcdc (HLCD
Controller) node.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d31ek.dts | 24
arch/arm/boot/dts/sama5d33ek.dts | 24
arch/arm/boot/dts/sama5d34ek.dts | 24
Add LCD panel related nodes (backlight, regulators and panel) to sama5d3
Display Module dtsi.
Reference LCD pin muxing used by sama5d3xek boards.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3xdm.dtsi | 43 +++
1 file changed, 43 insertions(+)
Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boo
Define alternative pin muxing for the LCDC pins.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 50 ++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi
b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 2186b8
The HLCDC (HLCD Controller) IP supports 4 different output mode (RGB444,
RGB565, RGB666 and RGB888) and the pin muxing will depend on the chosen
RGB mode.
Split pin definitions to be able to set pin config according to the
selected mode.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
The HLCDC block provides a single RGB output port, and only supports LCD
panels connection to LCD panels for now.
The atmel,panel propert
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
This display controller supports at least one primary plane and might
provide several overlays and an hardware cursor depending on the IP
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
The DT bindings used for this PWM device is following the default 3 cells
bindings described in Documentation/devicetree/bindings/pwm/pwm.txt.
Signed-off-by: Boris BR
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
This driver add support for a PWM chip exposing a single PWM device (which
will most likely be used to drive a backlight device).
Signed-off-by: Boris BREZILLON
---
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
This patch adds documentation for atmel-hlcdc DT bindings.
Signed-off-by: Boris BREZILLON
---
.../devicetree/b
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
The MFD device provides a regmap and several clocks (those connected
to this hardware block) to its subdevices.
Hello,
Sorry for the noise, but I forgot to add the LAKML in Cc.
This patch series adds support for Atmel HLCDC (HLCD Controller) available
on some Atmel SoCs (i.e. the sama5d3 family).
The first two versions of this series didn't receive any reviews from DRM
maintainers or experienced DRM devel
https://bugzilla.kernel.org/show_bug.cgi?id=79591
--- Comment #2 from Stefan Ringel ---
and witch bugtracker is it?
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On Mon, Jul 7, 2014 at 6:20 PM, David Herrmann wrote:
> Hi
>
> On Tue, Jul 8, 2014 at 12:10 AM, Alex Deucher
> wrote:
>> Render nodes are ready to leave the experimental state so
>> drop the kernel command line parameter which was hiding them
>> by default. I swore we had already enabled these
https://bugzilla.kernel.org/show_bug.cgi?id=79591
Martin Peres changed:
What|Removed |Added
CC||martin.peres at free.fr
--- Comment #1 fro
Render nodes are ready to leave the experimental state so
drop the kernel command line parameter which was hiding them
by default. I swore we had already enabled these by default,
that appears to not be the case.
v2: remove rnodes parameter description
Signed-off-by: Alex Deucher
---
drivers/g
In tda998x_encoder_destroy(), priv->cec is never NULL, so,
remove its test.
Signed-off-by: Jean-Francois Moine
---
drivers/gpu/drm/i2c/tda998x_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c
b/drivers/gpu/drm/i2c/tda998x_drv.c
index
On Mon, 7 Jul 2014 17:22:03 +0300
Dan Carpenter wrote:
> The patch 12473b7d8e60: "drm/i2c: tda998x: use irq for connection
> status and EDID read" from Jan 25, 2014, leads to the following
> static checker warning:
>
> drivers/gpu/drm/i2c/tda998x_drv.c:1199 tda998x_encoder_destroy()
>
art --
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On Sat, Jul 5, 2014 at 3:42 AM, Paul Menzel
wrote:
> Dear Linux folks,
>
>
> connecting a VGA monitor to the internal graphics device of the ASRock
> E350M1 [1], the brightness is much too high.
>
> $ lspci -tvnn
> [?]
> +-01.0 Advanced Micro Devices [AMD] nee ATI Wrestler
On Mon, Jul 7, 2014 at 5:16 AM, Christian K?nig
wrote:
> From: Christian K?nig
>
> Signed-off-by: Christian K?nig
Applied to my -fixes tree.
Thanks!
Alex
> ---
> drivers/gpu/drm/radeon/cik.c | 6 --
> drivers/gpu/drm/radeon/evergreen.c | 6 --
> drivers/gpu/drm/radeon/si.c
Render nodes are ready to leave the experimental state so
drop the kernel command line parameter which was hiding them
by default. I swore we had already enabled these by default,
that appears to not be the case.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/drm_stub.c | 6 +-
1 file chan
Hello Jean-Francois Moine,
The patch 12473b7d8e60: "drm/i2c: tda998x: use irq for connection
status and EDID read" from Jan 25, 2014, leads to the following
static checker warning:
drivers/gpu/drm/i2c/tda998x_drv.c:1199 tda998x_encoder_destroy()
warn: variable dereferenced before
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Il 07/07/2014 16:49, Daniel Vetter ha scritto:
> So the correct fix to forward intel gpus to guests is indeed to somehow
> fake the pch pci ids since the driver really needs them. Gross design, but
> that's how the hardware works.
A way that could work for virtualization is this: if you find the c
On Wed, Jun 25, 2014 at 01:01:36AM +0200, Rafael J. Wysocki wrote:
> On Tuesday, June 24, 2014 02:43:02 PM Jani Nikula wrote:
> > On Thu, 19 Jun 2014, Randy Dunlap wrote:
> > > On 06/18/14 23:16, Stephen Rothwell wrote:
> > >> Hi all,
> > >>
> > >> The powerpc allyesconfig is again broken more th
On Wed, Jun 25, 2014 at 10:28:21AM +0800, Chen, Tiejun wrote:
> On 2014/6/24 10:59, Zhenyu Wang wrote:
> >On 2014.06.19 17:53:51 +0800, Tiejun Chen wrote:
> >>Originally the reason to probe ISA bridge instead of Dev31:Fun0
> >>is to make graphics device passthrough work easy for VMM, that
> >>only
Enable LCD related nodes and reference panel node in the hlcdc (HLCD
Controller) node.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d31ek.dts | 24
arch/arm/boot/dts/sama5d33ek.dts | 24
arch/arm/boot/dts/sama5d34ek.dts | 24
Add LCD panel related nodes (backlight, regulators and panel) to sama5d3
Display Module dtsi.
Reference LCD pin muxing used by sama5d3xek boards.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3xdm.dtsi | 43 +++
1 file changed, 43 insertions(+)
Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boo
Define alternative pin muxing for the LCDC pins.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 50 ++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi
b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 2186b8
The HLCDC (HLCD Controller) IP supports 4 different output mode (RGB444,
RGB565, RGB666 and RGB888) and the pin muxing will depend on the chosen
RGB mode.
Split pin definitions to be able to set pin config according to the
selected mode.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
The HLCDC block provides a single RGB output port, and only supports LCD
panels connection to LCD panels for now.
The atmel,panel propert
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
This display controller supports at least one primary plane and might
provide several overlays and an hardware cursor depending on the IP
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
The DT bindings used for this PWM device is following the default 3 cells
bindings described in Documentation/devicetree/bindings/pwm/pwm.txt.
Signed-off-by: Boris BR
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
This driver add support for a PWM chip exposing a single PWM device (which
will most likely be used to drive a backlight device).
Signed-off-by: Boris BREZILLON
---
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
This patch adds documentation for atmel-hlcdc DT bindings.
Signed-off-by: Boris BREZILLON
---
.../devicetree/b
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
The MFD device provides a regmap and several clocks (those connected
to this hardware block) to its subdevices.
Hello,
This patch series adds support for Atmel HLCDC (HLCD Controller) available
on some Atmel SoCs (i.e. the sama5d3 family).
The first two versions of this series didn't receive any reviews from DRM
maintainers or experienced DRM developers.
Anyway, I hope I'll get some feedback on this versio
On Wed, Jun 25, 2014 at 08:48:32AM +0200, Paolo Bonzini wrote:
> It is only slightly better, but the right solution is to fix the driver.
> There is absolutely zero reason why a graphics driver should know about the
> vendor/device ids of the PCH.
There is a very valid reason to know about the PCH
because:
You are the assignee for the bug.
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