On Fre, 2012-06-01 at 08:19 +0200, Michel Dänzer wrote:
>
> I think this might introduce a race condition:
>
> Thread 0 Thread 1
>
> atomic_inc_return() returns 1
> spin_lock_irqsave()
> atomic_dec_and_test()
> radeon_irq_set()
>
> => the interrupt won't be enabled.
Hrmm, I m
On Don, 2012-05-31 at 22:16 +0200, Christian König wrote:
>
> So we can skip the looking.
'locking'
> diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c
> b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> index 73cd0fd..52f85ba 100644
> --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
> +++ b/driver
From: Christian Koenig
The shader preemption on cayman doesn't work
correctly with multiple rings. So to be able to
still make use of the compute rings we use a
semaphore to make sure that only one IB can execute
at the same time.
This isn't as effective as shader preemption, but
also isn't as b
Try to remove or replace the cs_mutex with a
vm_mutex where it is still needed.
Signed-off-by: Christian K?nig
---
drivers/gpu/drm/radeon/radeon.h| 44 +---
drivers/gpu/drm/radeon/radeon_cs.c |7 ++---
drivers/gpu/drm/radeon/radeon_device.c |2 +-
From: Christian Koenig
So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.
Signed-off-by: Christian Koenig
---
drivers/gpu/drm/radeon/evergreen.c | 32 -
drivers/gpu/drm/radeon/r100.c | 10 +++---
drivers/gpu/dr
From: Christian Koenig
1. It is really dangerous to have more than one
spinlock protecting the same information.
2. radeon_irq_set sometimes wasn't called with lock
protection, so it can happen that more than one
CPU would tamper with the irq regs at the same
time.
3. The pm.gui_idl
From: Christian Koenig
The spinlock was actually there to protect the
rptr, but rptr was read outside of the locked area.
v2: Keep the spinlock, looks like there is still something
in the ih that doesn't like irqs enabled.
Signed-off-by: Christian Koenig
---
drivers/gpu/drm/radeon/evergre
From: Christian Koenig
Signed-off-by: Christian Koenig
---
drivers/gpu/drm/radeon/radeon.h |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3e83480..618df9a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/
It is a rw_semaphore now and only write locked
while changing the clock. Also the lock is renamed
to better reflect what it is protecting.
v2: Keep the ttm_vm_ops on IGPs
Signed-off-by: Christian K?nig
---
drivers/gpu/drm/radeon/radeon.h|3 ++-
drivers/gpu/drm/radeon/radeon_device.c
Move inter ring syncing with semaphores into the
existing ring allocations, with that we need to
lock the ring mutex only once.
Signed-off-by: Christian K?nig
---
drivers/gpu/drm/radeon/evergreen_blit_kms.c |3 +-
drivers/gpu/drm/radeon/r600.c |5 +-
drivers/gpu/drm/radeon/
Signed-off-by: Christian K?nig
---
drivers/gpu/drm/radeon/radeon.h | 23 ++-
drivers/gpu/drm/radeon/radeon_fence.c | 73 +
2 files changed, 85 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/ra
It is completely unnecessary to create fences
before they are emitted, so remove it and a bunch
of checks if fences are emitted or not.
Signed-off-by: Christian K?nig
---
drivers/gpu/drm/radeon/evergreen.c|2 +-
drivers/gpu/drm/radeon/ni.c |2 +-
drivers/gpu/drm/rad
On 31.05.2012 20:15, Alex Deucher wrote:
> On Thu, May 24, 2012 at 11:35 AM, Alex Deucher
> wrote:
>> On Thu, May 24, 2012 at 3:49 AM, Christian K?nig
>> wrote:
>>> From: Christian Koenig
>>>
>>> 1. It is really dangerous to have more than one
>>>spinlock protecting the same information.
>>
On Thu, May 31, 2012 at 9:24 PM, Singh, Satyeshwar
wrote:
> Is there a reason for the 30 ms delay in the first place?
git blame says there is, it supposedely fixes a bug with tv detection.
-Daniel
--
Daniel Vetter
daniel.vetter at ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch
On Thu, May 31, 2012 at 11:34:37AM +0200, Lars-Peter Clausen wrote:
> >> + drm_helper_mode_fill_fb_struct(&fb_cma->fb, mode_cmd);
> >> +
> >> + for (i = 0; i < num_planes; i++)
> >> + fb_cma->obj[i] = obj[i];
> >
> > Check for valid num_planes before this loop?
> >
>
> Hm, I think the
Does this by extension mean that stride changes should also not be allowed
while page flipping?
Thanks,
Satyeshwar
-Original Message-
From: dri-devel-bounces+satyeshwar.singh=intel.com at lists.freedesktop.org
[mailto:dri-devel-bounces+satyeshwar.singh=intel@lists.freedesktop.org] O
Is there a reason for the 30 ms delay in the first place?
-Satyeshwar
-Original Message-
From: dri-devel-bounces+satyeshwar.singh=intel.com at lists.freedesktop.org
[mailto:dri-devel-bounces+satyeshwar.singh=intel@lists.freedesktop.org] On
Behalf Of Daniel Vetter
Sent: Thursday, May
From: Alex Deucher
Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and
simplify render backend map. This now properly sets up the backend map
on r6xx-9xx which should improve 3D performance.
Signed-off-by: Alex Deucher
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeo
From: Jerome Glisse
Bugs that should be fixed by this patch :
https://bugs.freedesktop.org/show_bug.cgi?id=49792
https://bugzilla.kernel.org/show_bug.cgi?id=43207
https://bugs.freedesktop.org/show_bug.cgi?id=39282
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c |4 ++--
From: Alex Deucher
Need to program an additional VM register. This doesn't not currently
cause any problems, but allows us to program the proper backend
map in a subsequent patch which should improve performance on these
asics.
Signed-off-by: Alex Deucher
Cc: stable at vger.kernel.org
---
dri
From: Alex Deucher
While there are cards with more than 8 mem banks, the max
number of banks from a tiling perspective is 8, so cap
the tiling config at 8 banks.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43448
Signed-off-by: Alex Deucher
Cc: stable at vger.kernel.org
---
drivers/gpu
Test whether the pixel format changes in the mode set handler, and
perform a full mode set instead of a mode set base if it does.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/drm_crtc_helper.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/drm_c
A page flip is not a mode set, changing the frame buffer pixel format
doesn't make sense and isn't handled by most drivers anyway. Disallow
it.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/drm_crtc.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/g
Hi everybody,
Here are two small fixes that disallow format changes in page flip operations,
and perform a full mode set instead of a mode set base in the CRTC helper set
config handler if the pixel format changed.
Laurent Pinchart (2):
drm: Don't allow page flip to change pixel format
drm: P
On Thu, May 31, 2012 at 4:15 PM, Christian K?nig
wrote:
> Signed-off-by: Christian K?nig
> ---
> ?drivers/gpu/drm/radeon/radeon.h ? ? ? | ? 23 ++-
> ?drivers/gpu/drm/radeon/radeon_fence.c | ? 73
> +
> ?2 files changed, 85 insertions(+), 11 deletions(-)
>
>
On Thu, May 31, 2012 at 4:16 PM, Christian K?nig
wrote:
> From: Christian Koenig
>
> 1. It is really dangerous to have more than one
> ? spinlock protecting the same information.
>
> 2. radeon_irq_set sometimes wasn't called with lock
> ? protection, so it can happen that more than one
> ? CPU wo
From: Alex Deucher
Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and
simplify render backend map. This now properly sets up the backend map
on r6xx-9xx which should improve 3D performance.
Signed-off-by: Alex Deucher
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeo
From: Jerome Glisse
Bugs that should be fixed by this patch :
https://bugs.freedesktop.org/show_bug.cgi?id=49792
https://bugzilla.kernel.org/show_bug.cgi?id=43207
https://bugs.freedesktop.org/show_bug.cgi?id=39282
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c |4 ++--
From: Alex Deucher
Need to program an additional VM register. This doesn't not currently
cause any problems, but allows us to program the proper backend
map in a subsequent patch which should improve performance on these
asics.
Signed-off-by: Alex Deucher
Cc: sta...@vger.kernel.org
---
driver
From: Alex Deucher
While there are cards with more than 8 mem banks, the max
number of banks from a tiling perspective is 8, so cap
the tiling config at 8 banks.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43448
Signed-off-by: Alex Deucher
Cc: sta...@vger.kernel.org
---
drivers/gpu/dr
On Thu, May 31, 2012 at 3:44 PM, Singh, Satyeshwar
wrote:
> Does this by extension mean that stride changes should also not be allowed
> while page flipping?
Everything beyond a crtc base address change should require a full modeset.
Alex
> Thanks,
> Satyeshwar
>
> -Original Message-
>
On Thu, May 31, 2012 at 2:15 PM, Alex Deucher wrote:
> On Thu, May 24, 2012 at 11:35 AM, Alex Deucher
> wrote:
>> On Thu, May 24, 2012 at 3:49 AM, Christian K?nig
>> wrote:
>>> From: Christian Koenig
>>>
>>> 1. It is really dangerous to have more than one
>>> ? spinlock protecting the same inf
Hi Linus,
as mentioned previously these are the extra bits of drm that relied on the
dma-buf pull to work, the first three just stub out the mmap interface,
and the next set provide vmap export to i915/radeon/nouveau and vmap
import to udl.
Dave.
The following changes since commit af56e0aa35
? ? ? ? ? ? ?radeon_irq_set(rdev);
>> ? ? ? ?}
>> - ? ? ? spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
>> + ? ? ? spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
>> ?}
>>
>> ?void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
>> @@ -260,12 +268,52 @@ void radeon_irq_kms_pflip_irq_put(struct radeon_device
>> *rdev, int crtc)
>> ? ? ? ?if (crtc < 0 || crtc >= rdev->num_crtc)
>> ? ? ? ? ? ? ? ?return;
>>
>> - ? ? ? spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
>> + ? ? ? spin_lock_irqsave(&rdev->irq.lock, irqflags);
>> ? ? ? ?BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <=
>> 0);
>> ? ? ? ?if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] ==
>> 0)) {
>> ? ? ? ? ? ? ? ?rdev->irq.pflip[crtc] = false;
>> ? ? ? ? ? ? ? ?radeon_irq_set(rdev);
>> ? ? ? ?}
>> - ? ? ? spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
>> + ? ? ? spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
>> +}
>> +
>> +void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block)
>> +{
>> + ? ? ? unsigned long irqflags;
>> +
>> + ? ? ? spin_lock_irqsave(&rdev->irq.lock, irqflags);
>> + ? ? ? rdev->irq.afmt[block] = true;
>> + ? ? ? radeon_irq_set(rdev);
>> + ? ? ? spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
>> +
>> +}
>> +
>> +void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block)
>> +{
>> + ? ? ? unsigned long irqflags;
>> +
>> + ? ? ? spin_lock_irqsave(&rdev->irq.lock, irqflags);
>> + ? ? ? rdev->irq.afmt[block] = false;
>> + ? ? ? radeon_irq_set(rdev);
>> + ? ? ? spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
>> ?}
>>
>
> Should probably also add radeon_irq_kms_[en|dis]able_hpd() function
> and call replaced the calls to *_irq_set() in the *_hpd_init() and
> *_hpd_fini() callbacks for display hotplug.
See attached follow on patch.
Alex
-- next part --
A non-text attachment was scrubbed...
Name: 0001-drm-radeon-apply-Murphy-s-law-to-the-kms-hpd-irq-cod.patch
Type: text/x-patch
Size: 13299 bytes
Desc: not available
URL:
<http://lists.freedesktop.org/archives/dri-devel/attachments/20120531/2386658a/attachment-0001.bin>
On Thu, May 31, 2012 at 4:15 PM, Christian König
wrote:
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/radeon/radeon.h | 23 ++-
> drivers/gpu/drm/radeon/radeon_fence.c | 73
> +
> 2 files changed, 85 insertions(+), 11 deletions(-)
>
>
On Thu, May 31, 2012 at 4:16 PM, Christian König
wrote:
> From: Christian Koenig
>
> 1. It is really dangerous to have more than one
> spinlock protecting the same information.
>
> 2. radeon_irq_set sometimes wasn't called with lock
> protection, so it can happen that more than one
> CPU wo
It is a rw_semaphore now and only write locked
while changing the clock. Also the lock is renamed
to better reflect what it is protecting.
v2: Keep the ttm_vm_ops on IGPs
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon.h|3 ++-
drivers/gpu/drm/radeon/radeon_device.c
From: Christian Koenig
The shader preemption on cayman doesn't work
correctly with multiple rings. So to be able to
still make use of the compute rings we use a
semaphore to make sure that only one IB can execute
at the same time.
This isn't as effective as shader preemption, but
also isn't as b
Try to remove or replace the cs_mutex with a
vm_mutex where it is still needed.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon.h| 44 +---
drivers/gpu/drm/radeon/radeon_cs.c |7 ++---
drivers/gpu/drm/radeon/radeon_device.c |2 +-
From: Christian Koenig
So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.
Signed-off-by: Christian Koenig
---
drivers/gpu/drm/radeon/evergreen.c | 32 -
drivers/gpu/drm/radeon/r100.c | 10 +++---
drivers/gpu/dr
From: Christian Koenig
1. It is really dangerous to have more than one
spinlock protecting the same information.
2. radeon_irq_set sometimes wasn't called with lock
protection, so it can happen that more than one
CPU would tamper with the irq regs at the same
time.
3. The pm.gui_idl
From: Christian Koenig
The spinlock was actually there to protect the
rptr, but rptr was read outside of the locked area.
v2: Keep the spinlock, looks like there is still something
in the ih that doesn't like irqs enabled.
Signed-off-by: Christian Koenig
---
drivers/gpu/drm/radeon/evergre
Move inter ring syncing with semaphores into the
existing ring allocations, with that we need to
lock the ring mutex only once.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/evergreen_blit_kms.c |3 +-
drivers/gpu/drm/radeon/r600.c |5 +-
drivers/gpu/drm/radeon/
From: Christian Koenig
Signed-off-by: Christian Koenig
---
drivers/gpu/drm/radeon/radeon.h |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3e83480..618df9a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/
It is completely unnecessary to create fences
before they are emitted, so remove it and a bunch
of checks if fences are emitted or not.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/evergreen.c|2 +-
drivers/gpu/drm/radeon/ni.c |2 +-
drivers/gpu/drm/rad
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon.h | 23 ++-
drivers/gpu/drm/radeon/radeon_fence.c | 73 +
2 files changed, 85 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/ra
On 31.05.2012 20:15, Alex Deucher wrote:
On Thu, May 24, 2012 at 11:35 AM, Alex Deucher wrote:
On Thu, May 24, 2012 at 3:49 AM, Christian König
wrote:
From: Christian Koenig
1. It is really dangerous to have more than one
spinlock protecting the same information.
2. radeon_irq_set somet
On Thu, May 31, 2012 at 3:44 PM, Singh, Satyeshwar
wrote:
> Does this by extension mean that stride changes should also not be allowed
> while page flipping?
Everything beyond a crtc base address change should require a full modeset.
Alex
> Thanks,
> Satyeshwar
>
> -Original Message-
>
Does this by extension mean that stride changes should also not be allowed
while page flipping?
Thanks,
Satyeshwar
-Original Message-
From: dri-devel-bounces+satyeshwar.singh=intel@lists.freedesktop.org
[mailto:dri-devel-bounces+satyeshwar.singh=intel@lists.freedesktop.org] On
On Thu, May 31, 2012 at 9:24 PM, Singh, Satyeshwar
wrote:
> Is there a reason for the 30 ms delay in the first place?
git blame says there is, it supposedely fixes a bug with tv detection.
-Daniel
--
Daniel Vetter
daniel.vet...@ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch
_
Is there a reason for the 30 ms delay in the first place?
-Satyeshwar
-Original Message-
From: dri-devel-bounces+satyeshwar.singh=intel@lists.freedesktop.org
[mailto:dri-devel-bounces+satyeshwar.singh=intel@lists.freedesktop.org] On
Behalf Of Daniel Vetter
Sent: Thursday, May 31,
2012/5/30 Dave Jones :
> On Wed, May 30, 2012 at 05:58:48PM -0400, Dave Jones wrote:
> ?> On Wed, May 30, 2012 at 11:51:54PM +0200, Daniel Vetter wrote:
> ?> ?> On Wed, May 30, 2012 at 11:31 PM, Dave Jones
> wrote:
> ?> ?> > On this hardware:
> ?> ?> >
> ?> ?> > 00:02.0 VGA compatible controller:
Hi Sascha,
On Wednesday 30 May 2012 18:40:56 Sascha Hauer wrote:
> On Wed, May 30, 2012 at 02:32:59PM +0200, Laurent Pinchart wrote:
> > The SH Mobile LCD controller (LCDC) DRM driver supports the main
> > graphics plane in RGB and YUV formats, as well as the overlay planes (in
> > alpha-blending
Hi Sascha,
On Wednesday 30 May 2012 18:28:12 Sascha Hauer wrote:
> On Wed, May 30, 2012 at 05:40:13PM +0200, Laurent Pinchart wrote:
> > Hi Sascha,
> >
> > Thank you for the patch. I've successfully tested the helper with the new
> > SH Mobile DRM driver. Just a couple of comments below in additi
On Thu, May 31, 2012 at 2:15 PM, Alex Deucher wrote:
> On Thu, May 24, 2012 at 11:35 AM, Alex Deucher wrote:
>> On Thu, May 24, 2012 at 3:49 AM, Christian König
>> wrote:
>>> From: Christian Koenig
>>>
>>> 1. It is really dangerous to have more than one
>>> spinlock protecting the same inform
Hi Sascha,
Thanks for the patch. Here's a bit more extensive review.
On Thursday 31 May 2012 10:08:54 Sascha Hauer wrote:
> Many embedded drm devices do not have a IOMMU and no dedicated
> memory for graphics. These devices use cma (Contiguous Memory
> Allocator) backed graphics memory. This patc
On 05/31/2012 10:13 AM, Sascha Hauer wrote:
> On Wed, May 30, 2012 at 05:30:15PM +0200, Lars-Peter Clausen wrote:
>> This patch introduces a set of helper function for implementing the KMS
>> framebuffer layer for drivers which use the drm gem CMA helper function.
>>
>> Signed-off-by: Lars-Peter Cl
On Thu, May 24, 2012 at 11:35 AM, Alex Deucher wrote:
> On Thu, May 24, 2012 at 3:49 AM, Christian König
> wrote:
>> From: Christian Koenig
>>
>> 1. It is really dangerous to have more than one
>> spinlock protecting the same information.
>>
>> 2. radeon_irq_set sometimes wasn't called with lo
On Thu, May 31, 2012 at 11:34:37AM +0200, Lars-Peter Clausen wrote:
> >> + drm_helper_mode_fill_fb_struct(&fb_cma->fb, mode_cmd);
> >> +
> >> + for (i = 0; i < num_planes; i++)
> >> + fb_cma->obj[i] = obj[i];
> >
> > Check for valid num_planes before this loop?
> >
>
> Hm, I think the
On Thu, May 24, 2012 at 09:26:49PM +0200, Daniel Vetter wrote:
> A 30 ms delay is simply way too big to waste cpu cycles on.
>
> Signed-off-by: Daniel Vetter
I've queued this patch here for -next with Chris' irc ack added.
-Daniel
--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 5
2012/5/31 Chris Wilson :
> Before that commit we had no idea that we had run out of property slots.
> I think the WARN is genuine, but maybe we should just bump the count set
> it to WARN_ONCE and hope the conversion to lists arrives sooner rather
> than latter.
> -Chris
>
Chris is right: this is
On Wed, May 30, 2012 at 05:30:15PM +0200, Lars-Peter Clausen wrote:
> This patch introduces a set of helper function for implementing the KMS
> framebuffer layer for drivers which use the drm gem CMA helper function.
>
> Signed-off-by: Lars-Peter Clausen
>
> ---
> Changes since v1:
> * Som
Many embedded drm devices do not have a IOMMU and no dedicated
memory for graphics. These devices use cma (Contiguous Memory
Allocator) backed graphics memory. This patch provides helper
functions to be able to share the code.
Signed-off-by: Sascha Hauer
---
changes since v1:
- map whole buffer
Hello all,
here are some warning I got after resuming from suspend.
It is not really clear to me how I could debug further. Please tell me if I can
do something else.
I also attached the whole dmesg.
Best Regards,
[170934.181984] [ cut here ]
[170934.181991] WARNING: at
Test whether the pixel format changes in the mode set handler, and
perform a full mode set instead of a mode set base if it does.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/drm_crtc_helper.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/drm_c
A page flip is not a mode set, changing the frame buffer pixel format
doesn't make sense and isn't handled by most drivers anyway. Disallow
it.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/drm_crtc.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/g
Hi everybody,
Here are two small fixes that disallow format changes in page flip operations,
and perform a full mode set instead of a mode set base in the CRTC helper set
config handler if the pixel format changed.
Laurent Pinchart (2):
drm: Don't allow page flip to change pixel format
drm: P
On Thu, May 31, 2012 at 3:09 AM, Daniel Vetter wrote:
> On Wed, May 30, 2012 at 11:21:32AM -0400, Sean Paul wrote:
>> On Wed, May 30, 2012 at 10:16 AM, Adam Jackson wrote:
>> > On 5/30/12 8:05 AM, Sean Paul wrote:
>> >
>> >> Yes, definitely. The reason I can't set it via xrandr (easily) is
>> >>
On Wed, May 30, 2012 at 11:21:32AM -0400, Sean Paul wrote:
> On Wed, May 30, 2012 at 10:16 AM, Adam Jackson wrote:
> > On 5/30/12 8:05 AM, Sean Paul wrote:
> >
> >> Yes, definitely. The reason I can't set it via xrandr (easily) is
> >> because we look for lvds downclock modes (in i915) on the driv
On Thu, May 31, 2012 at 12:35 AM, Eric Anholt wrote:
>
> Did you want pointer for timeout in the userspace api? ?I don't feel
> strongly about it, I just didn't see a use. ?The equivalent API I could
> think of was select(), where apparently linux returns time unwaited,
> while "everyone else" doe
On Wed, 30 May 2012 18:26:51 -0400, Dave Jones wrote:
> On Wed, May 30, 2012 at 05:58:48PM -0400, Dave Jones wrote:
> > On Wed, May 30, 2012 at 11:51:54PM +0200, Daniel Vetter wrote:
> > > On Wed, May 30, 2012 at 11:31 PM, Dave Jones
> wrote:
> > > > On this hardware:
> > > >
> > > > 00
Hi Sascha,
it's good try to avoid demand paging way by page fault handler.
actually, we don't need demand paging way on non-iommu system. I
looked into your previous patch and I realized that patch was based on
old exynos driver. now patch looks almostly good to me and below is my
comments minor.
2012/5/30 Dave Jones :
> On Wed, May 30, 2012 at 05:58:48PM -0400, Dave Jones wrote:
> > On Wed, May 30, 2012 at 11:51:54PM +0200, Daniel Vetter wrote:
> > > On Wed, May 30, 2012 at 11:31 PM, Dave Jones wrote:
> > > > On this hardware:
> > > >
> > > > 00:02.0 VGA compatible controller: In
Hi Linus,
as mentioned previously these are the extra bits of drm that relied on the
dma-buf pull to work, the first three just stub out the mmap interface,
and the next set provide vmap export to i915/radeon/nouveau and vmap
import to udl.
Dave.
The following changes since commit af56e0aa35
On Thu, May 31, 2012 at 3:09 AM, Daniel Vetter wrote:
> On Wed, May 30, 2012 at 11:21:32AM -0400, Sean Paul wrote:
>> On Wed, May 30, 2012 at 10:16 AM, Adam Jackson wrote:
>> > On 5/30/12 8:05 AM, Sean Paul wrote:
>> >
>> >> Yes, definitely. The reason I can't set it via xrandr (easily) is
>> >>
2012/5/31 Chris Wilson :
> Before that commit we had no idea that we had run out of property slots.
> I think the WARN is genuine, but maybe we should just bump the count set
> it to WARN_ONCE and hope the conversion to lists arrives sooner rather
> than latter.
> -Chris
>
Chris is right: this is
https://bugzilla.kernel.org/show_bug.cgi?id=43295
--- Comment #4 from Thanigaivelan 2012-05-31
02:51:44 ---
My System hangs when panic occurred switching back to text console. I have to
restart it again. it happen many time. Please tell me what is the problem in
kernel file.
I am using ke
Hi Sascha,
On Wednesday 30 May 2012 18:40:56 Sascha Hauer wrote:
> On Wed, May 30, 2012 at 02:32:59PM +0200, Laurent Pinchart wrote:
> > The SH Mobile LCD controller (LCDC) DRM driver supports the main
> > graphics plane in RGB and YUV formats, as well as the overlay planes (in
> > alpha-blending
Hi Sascha,
On Wednesday 30 May 2012 18:28:12 Sascha Hauer wrote:
> On Wed, May 30, 2012 at 05:40:13PM +0200, Laurent Pinchart wrote:
> > Hi Sascha,
> >
> > Thank you for the patch. I've successfully tested the helper with the new
> > SH Mobile DRM driver. Just a couple of comments below in additi
On 05/31/2012 10:13 AM, Sascha Hauer wrote:
> On Wed, May 30, 2012 at 05:30:15PM +0200, Lars-Peter Clausen wrote:
>> This patch introduces a set of helper function for implementing the KMS
>> framebuffer layer for drivers which use the drm gem CMA helper function.
>>
>> Signed-off-by: Lars-Peter Cl
Hi Sascha,
Thanks for the patch. Here's a bit more extensive review.
On Thursday 31 May 2012 10:08:54 Sascha Hauer wrote:
> Many embedded drm devices do not have a IOMMU and no dedicated
> memory for graphics. These devices use cma (Contiguous Memory
> Allocator) backed graphics memory. This patc
https://bugs.freedesktop.org/show_bug.cgi?id=49981
--- Comment #2 from Brad Campbell 2012-05-30 19:15:29
PDT ---
I can replicate this on all radeon enabled kernels including current.
It appears than when more than one head is enabled, a separate set of power
profiles is used which attempts to s
https://bugs.freedesktop.org/show_bug.cgi?id=49981
--- Comment #1 from Brad Campbell 2012-05-30 19:13:12
PDT ---
Created attachment 62305
--> https://bugs.freedesktop.org/attachment.cgi?id=62305
The hack I use to enable 3 heads on my iMac without torching the Radeon
--
Configure bugmail: htt
On Thu, May 24, 2012 at 09:26:49PM +0200, Daniel Vetter wrote:
> A 30 ms delay is simply way too big to waste cpu cycles on.
>
> Signed-off-by: Daniel Vetter
I've queued this patch here for -next with Chris' irc ack added.
-Daniel
--
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57 4
On Wed, May 30, 2012 at 05:30:15PM +0200, Lars-Peter Clausen wrote:
> This patch introduces a set of helper function for implementing the KMS
> framebuffer layer for drivers which use the drm gem CMA helper function.
>
> Signed-off-by: Lars-Peter Clausen
>
> ---
> Changes since v1:
> * Som
Many embedded drm devices do not have a IOMMU and no dedicated
memory for graphics. These devices use cma (Contiguous Memory
Allocator) backed graphics memory. This patch provides helper
functions to be able to share the code.
Signed-off-by: Sascha Hauer
---
changes since v1:
- map whole buffer
On Wed, 30 May 2012 18:26:51 -0400, Dave Jones wrote:
> On Wed, May 30, 2012 at 05:58:48PM -0400, Dave Jones wrote:
> > On Wed, May 30, 2012 at 11:51:54PM +0200, Daniel Vetter wrote:
> > > On Wed, May 30, 2012 at 11:31 PM, Dave Jones wrote:
> > > > On this hardware:
> > > >
> > > > 00:02
On Wed, May 30, 2012 at 11:21:32AM -0400, Sean Paul wrote:
> On Wed, May 30, 2012 at 10:16 AM, Adam Jackson wrote:
> > On 5/30/12 8:05 AM, Sean Paul wrote:
> >
> >> Yes, definitely. The reason I can't set it via xrandr (easily) is
> >> because we look for lvds downclock modes (in i915) on the driv
On Thu, May 31, 2012 at 12:35 AM, Eric Anholt wrote:
>
> Did you want pointer for timeout in the userspace api? I don't feel
> strongly about it, I just didn't see a use. The equivalent API I could
> think of was select(), where apparently linux returns time unwaited,
> while "everyone else" doe
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