[Discuss-gnuradio] Information FPGA

Hi, I am a student and I carry out a degree thesis about SDR in particular FPGA. I have seen some modules of FPGA but I haven't understood however these modules are interconnected between them. Could you give me any informations? Thank you very much. Calogero _

[Discuss-gnuradio] Modules Verilog in FPGA

Hi, thank you for answers. I have seen Quartus II and but I don't manage to see with Quartus II the content of bigger modules, for example "usrp_std". How do I do to see the content of these big modules, that is however these modules are interconnected between them with Quartus? Under the folder "u

[Discuss-gnuradio] How can I read the value of RSSI?

Hi, the PC receives packets BULK of 512 byte by USB. I have seen the form of packet and in several fields there is the field RSSI. I want to read the value of RSSI by packets but I don't understand where I can read this value by code C++. Could you suggest where I can read this value by files C++?

[Discuss-gnuradio] Information RSSI

Hi, I have executed the package "inband-usb" and I have seen the value of RSSI but I don't understand two things: 1) What's the value of the frequency of USRP which is setted of default in the test "test_usrp_inband_rx"? 2) There are two amplifiers. Could you know where their gains are setted whe

[Discuss-gnuradio] Others informations on RSSI

Hi, I am working on how to calcolate the value of Digital RSSI in FPGA (from output of ADCs). I have executed two tests,"test_usrp_inband_rx" and "test_ursp_inband_register", of package "inband-usb"in the same way as Mrs George Nychis has indicated me. http://lists.gnu.org/archive/html/discuss-gnu

[Discuss-gnuradio] How can I set the frequency of VCO?

Hi, I have written a code to set the frequency of VCO (ADF4360-0): bool flag = true; bool usrp_standard_rx::set_freq(double frequenza) { vector a; frequenza += -4e6; a = compute_regs(frequenza); if(a.at(0)==0) return false; write_all(a.at(0),a.at(1),a.at(2)); return true; }

[Discuss-gnuradio] Filter FIR on FPGA

Hello, I'm working on FPGA and in particulary on side RX. I want to insert a filter FIR pass band after the output of ADC and before the input of DDC. The filter is simulated across MATLAB in particulary across "fdatool" and it is written in verilog. What's the sampling frequency for this filter FI

[Discuss-gnuradio] Filter FIR on FPGA

Hi, I'm designing a pass band filter FIR on FPGA. This filter has 64MHz of sample rate and as window type "HAMMING". I'm using "MegaCore® IP Library" for design of the filter. Is correct to use this software for design of the filter? Could you suggest me other software for design of filter? Thank

[Discuss-gnuradio] Algorithm RSSI on FPGA

Hi, I'm working on RSSI value and reading mailing lists I have understood how RSSI is calculated. In the algorithm of RSSI in verilog alpha value is 2^-10 because the shift is made on 10 bits. I want to change alpha value (decrease or increase) but I don't understand how I can change it in the algo

Re: [Discuss-gnuradio] Algorithm RSSI on FPGA

Hi, I have read your answer but I have a doubt. If I change alpha value, for example putting 2^-10, according to me, it is not correct to change all [25:10] to [25:9] because writing "over_count = over_count_int[25:9]" and "rssi = rssi_int[25:9]" I lose MSB. Instead, if I want to change alpha val