Hi,
I want to monitor the I and Q samples being send over to the AD9777 DAC
(channel 1). I've noticed on the USRP2 schematic that the FPGA provides
io_tx[0:15] pins which are routed on the daughter board for probing (I
use the Basic Tx daugther board). Now, when I run the tx_samples app
examp
Hi,
I'm starting to see "E"s on the USRP2 UART output when my application is
running. I know that "U" means underrun but not "E"s. Anybody has an idea ?
Thanks
Leonard
--
Léonard Marziliano, Research Engineer
Communications Research Centre Canada (CRC)
3701 Carling, Ottawa, CANADA K2H 8S2
Te
n 06/05/2011 11:04 AM, Leonard Marziliano wrote:
Hi,
I'm starting to see "E"s on the USRP2 UART output when my application
is running. I know that "U" means underrun but not "E"s. Anybody has
an idea ?
Thanks
Leonard
--
Leonard Marziliano, Research E
Hi,
I have a USRP2 rev3.01 and I want to modify the FPGA code for
experimentation. However, I don't want to get the current FPGA code
version (head version) because , if I'm not mistaken, it supports the
new UHD interface which I don't use in my host application. So my
questions are:
1. Can