We have already implemented start_streaming_at(0) (see attached file). The
problem is that the FPGA doesn't reset the ddc on PPS so the sample marked with
'time stamp' = 0 is delayed by an unknown fractional number of samples realtive
to the output rate.
regards
Patrik and Ulrika
And again we are back to this misspelled topic.
Thank you Matt for your reply. It turned out that we used non synchronous 1PPS
and 10 MHz signals after all, and by using a 1PPS synchronous to the 10 MHz we
got different results.
However, we still don't get the time stamped samples to be perfec
We do call config_mimo(MC_WE_LOCK_TO_SMA) when we set up the usrp2 (before the
start of receiving). Is clocks_mimo_config() different from config_mimo()?
I also read about the troubles with config_mimo before revision 10471, but we
use 10899 of the software, so that problem should be solved i g
