Thanks for the clarification Eric. I was being a bit disingenuous by not
revealing what I was really trying to do. I don't actually care what's being
sent to the DAC. As I hinted at in an earlier email, what we've done is
create a custom verilog load that takes the data lines after the FIFO but
be
On Mon, May 21, 2007 at 04:19:58PM -0400, Steven Clark wrote:
> If I need pin-level access to the DAC chip, sink_s is my only option AFAIK.
> I understand that it's interleaved I&Q, don't worry about that.
> My original questions remain.
>
> On 5/21/07, Eric Blossom <[EMAIL PROTECTED]> wrote:
> >
If I need pin-level access to the DAC chip, sink_s is my only option AFAIK.
I understand that it's interleaved I&Q, don't worry about that.
My original questions remain.
On 5/21/07, Eric Blossom <[EMAIL PROTECTED]> wrote:
On Mon, May 21, 2007 at 10:48:04AM -0400, Steven Clark wrote:
> Hi all-
>
On Mon, May 21, 2007 at 10:48:04AM -0400, Steven Clark wrote:
> Hi all-
>
> Several quick questions.
> 1) For usrp sink_s, which bit of the short activates the MSB of the DAC
> chip? I.e., if I send 0bABCDEFGH IJKLMNOP, where each letter is either a 1
> or a 0, which letter matches the MSB?
First
Hi all-
Several quick questions.
1) For usrp sink_s, which bit of the short activates the MSB of the DAC
chip? I.e., if I send 0bABCDEFGH IJKLMNOP, where each letter is either a 1
or a 0, which letter matches the MSB?
2) If I want to generate a stream of alternating zeros and ones (stored in
byt
